LMP8100AEVAL

User's Guide SNOA490C – July 2007 – Revised May 2013 AN-1626 551013037 - LMP8100 Evaluation Board 1 Connectors, Jumpers, Test Points 1.1 Introduction This evaluation board contains the LMP8100, along with a logic circuit to program the register in the LMP8100. 1.2 Power Supply There are three banana plugs labeled GND, V+, and V− to power the evaluation board. A single supply of +5 V or a dual supply of ±2.5 V can be used. 1.3 Signal Connectors There are three connectors for signals: J1 J2 J3 1.4 is a BNC labeled VIN for the input signal. is a BNC labeled VOUT for the output signal is a 5-pin header that can be connected to a microcontroller. A microcontroller can be used to write the register of the LMP8100 if the logic circuitry on the evaluation board is not used. For more information, see Section 3.4. Jumpers The evaluation board has six jumpers: JP1 JP2 JP3 JP4 JP5 JP6 connects the SCK pin of the LMP8100 to either the on-board logic or to J3. connects the SDI pin of the LMP8100 to either the on-board logic or to J3. connects the CS pin of the LMP8100 to either the on-board logic or to J3. connects the V− pin of the LMP8100 to either the V− banana plug or to ground. connects the GRT pin of the LMP8100 to ground, a low-impedance DC source, or an AC ground. For more information, see Section 3.3. connects the enable pin of the op amp used in the low-impedance DC source to either +5 V (enabled) or ground (disabled). All trademarks are the property of their respective owners. SNOA490C – July 2007 – Revised May 2013 Submit Documentation Feedback AN-1626 551013037 - LMP8100 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 1 Hardware Setup 1.5 www.ti.com Test Points The test points are connected as follows: TP1 – +IN pin TP2 – GRT pin TP3 – SDO pin TP4 – VOUT pin TP5 – SCK pin TP6 – SDI pin TP7 – CS pin 2 Hardware Setup 2.1 Register Programming Setup • • 2.2 • +5 V supply: – Connect the jumper as follows: – JP4 – GND and the center pin – Connect a +5 V supply to the V+ and GND banana plugs. ±2.5 V supply: – Connect the jumper as follows: – JP4 – V− and the center pin – Connect a +2.5 V supply to the V+ banana plug, a −2.5 V supply to the V− banana plug, and supply grounds to the GND banana plug. GRT Pin Setup • • • 2 use the on-board logic circuit to program the LMP8100 register connect the jumpers as follows: JP1 – Pins 2 and 3 JP2 – Pins 2 and 3 JP3 – Pins 2 and 3 use an external microcontroller to program the LMP8100 register connect the jumpers as follows: JP1 – Pins 1 and 2 JP2 – Pins 1 and 2 JP3 – Pins 1 and 2 Connect the external microcontroller to J3. Power Supply Setup • 2.3 To – – – To – – – – Connect the jumpers as follows to connect the GRT pin to ground: – JP5 – GND and the center pin – JP6 – GND and the center pin Connect the jumpers as follows to connect the GRT pin to a low-impedance source: – JP5 – DC and the center pin – JP6 – V+ and the center pin Connect the jumpers as follows to connect the GRT pin to an AC ground: – JP5 – AC GND and the center pin – JP6 – GND and the center pin AN-1626 551013037 - LMP8100 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated SNOA490C – July 2007 – Revised May 2013 Submit Documentation Feedback Using the Board www.ti.com 2.4 Components Various loads can be installed on the evaluation board. The series resistance at R8 can be changed or replaced by a jumper. The resistive load at R4 can be changed. An AC coupled load can be added by using C24 and R9. A capacitive load can be added at C4. The evaluation board with a jumper at R8 has between 6 and 7 pF of parasitic capacitance. 3 Using the Board 3.1 Input and Output Signals The input signal is connected to the LMP8100 using J1 (VIN). The output signal is taken from J2 (VOUT). 3.2 Programming the LP8100 The register in the LMP8100 can be programmed using switches SW1 and SW2. SW1 consists of eight switches labeled G0, G1, G2, G3, PO, 0, C0, and C1 corresponding to the eight bits of the LMP8100 register. If the switch is up a “0” is programmed to the corresponding bit. SW2 is used to load the data into the register of the LMP8100. For example, to load a gain of 6 with a compensation level of 1, SW1 would be set as follows: G0 – Down = 1 G1 – Up = 0 G2 – Down = 1 G3 – Up = 0 PO – Up = 0 0 – Up = 0 C0 – Down = 1 C1 – Up = 0 Pushing SW2 will load the data into the register of the LMP8100. Table 1 shows the possible register values. Table 1. Register Values C1 C0 Zero PD G3 G2 G1 G0 Gain Comp. 0 0 0 0 0 0 0 0 1 00 0 0 0 0 0 0 0 1 2 00 0 0 0 0 0 0 1 0 3 00 0 0 0 0 0 0 1 1 4 00 0 0 0 0 0 1 0 0 5 00 0 0/1 0 0 0 1 0 1 6 00,01 0 0/1 0 0 0 1 1 0 7 00,01 0 0/1 0 0 0 1 1 1 8 00,01 0 0/1 0 0 1 0 0 0 9 00,01 0 0/1 0 0 1 0 0 1 10 00,01 0/1 0/1 0 0 1 0 1 0 11 00,01,10 0/1 0/1 0 0 1 0 1 1 12 00,01,10 0/1 0/1 0 0 1 1 0 0 13 00,01,10 0/1 0/1 0 0 1 1 0 1 14 00,01,10 0/1 0/1 0 0 1 1 1 0 15 00,01,10 0/1 0/1 0 0 1 1 1 1 16 00,01,10,11 X X X 1 X X X X NA NA Power Down X X 1 0 X X X X NA NA Zero Down SNOA490C – July 2007 – Revised May 2013 Submit Documentation Feedback Other AN-1626 551013037 - LMP8100 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 3 Schematic 3.3 www.ti.com Low-Impedance DC Source A DC voltage can be applied to the GRT pin. Because the GRT pin is connected to the internal gain setting resistors this DC source needs to be low impedance. Impedance on the GRT pin will change the gain of the LMP8100. The DC source on the evaluation board can use an op amp, U1, to provide a lowimpedance source. To use the DC source install an op amp, connect the DC and center pin of JP5, and connect the V+ and center pin of JP6. The voltage is set by adjusting R1. 3.4 Writing to the Register Using a Microcontroller A microcontroller can be used to program the LMP8100. The on-board register programmer is disconnected from the LMP8100 by connecting pins 1 and 2 of JP1, JP2, and JP3. The microcontroller signals are connected to the LMP8100 through J3. Schematic 3 V+ JP6 V+ 2 C1 + C6 0.1 PF 1 PF V+ 0.1 PF GND C20 1 PF V+ GND C23 C16 0.001 PF 0.1 PF + C21 4 3 V- V- U1 - 1 R1 1 PF C11 5k J1 R3 3 SW2 Y6 14 CLK CD4093 Y5 Y4 13 CLKEN Y3 Y2 15 8 RS Y1 VSS Y0 5 D5 G2 3 14 1 D6 G3 4 13 10 D7 PD 5 12 C14 + C19 0.1 PF 1 PF 7 D8 ³0´ 6 D9 C0 7 10 2 D10 C1 8 9 + U4 10 JP2 2 5 SDI TP6 3 TP5 JP3 SDO SCK 4 DIPSWITCH8 R TP3 2 JP1 CS TP7 J2 R8 13 Vout GRT GRT 11 11 4 3 TP2 V+ 15 V- D2 U2D 11 16 G1 2 6 R4 10k C24 C C4 C R9 R LMP8100 2 CD4017 R5 10k 1 2 3 4 5 3 CS SCK GND C8 C5 0.1 PF V- 1 PF 1 10 nF 3 U2A 330k 13 12 G0 1 D4 2 10 D1 CD4093 D3 6 12 SDI CD4093 8 9 1 2 C9 9 TP4 0.1 PF SDO U2C DC SW1 1 PF 2 Y8 4 11 + C7 1 1 PF R7 12 7 Y9 1 CO C3 0.1 PF C2 3 0.1 PF + C16 1 VDD C13 Y7 14 1 PF C10 10 nF CD4093 U2B 4 JP5 GND 2 3 + 7 C12 5 6 3 V+ AC GND U3 R6 330k 1 R2 10k 0.1 PF V+ R10 100 R 0.1 PF C17 TP1 + DGND 0.001 PF + 5 C15 6 C22 2 V+ + 4 J3 HEADER4 Figure 1. Schematic 4 AN-1626 551013037 - LMP8100 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated SNOA490C – July 2007 – Revised May 2013 Submit Documentation Feedback Board Layout www.ti.com 5 Board Layout Figure 2. Top Layout Figure 3. Bottom Layout SNOA490C – July 2007 – Revised May 2013 Submit Documentation Feedback AN-1626 551013037 - LMP8100 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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