LMP8358
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SNOSB09B – APRIL 2010 – REVISED MARCH 2013
LMP8358 Zero-Drift, Programmable Instrumentation Amplifier with Diagnostics
Check for Samples: LMP8358
FEATURES
1
Typical Values Unless Otherwise Noted, TA =
25°C
23
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supply Voltage 2.7V to 5.5V
Supply Current 1.8 mA
Max Gain Error 0.15%
Max Gain Drift 16 ppm/°C
Min CMRR 110 dB
Max Offset Voltage 10 µV
Max Offset Voltage Drift 50 nV/°C
GBW (Gain = 10) 8 MHz
Max Non-Linearity 100 ppm
Operating Temperature Range −40°C to 125°C
Input Fault Detection
SPI or Pin Configurable Modes
EMIRR at 1.8GHz 92 dB
14-Pin SOIC and 14-Pin TSSOP Package
APPLICATIONS
•
•
•
•
•
Bridge Sensor Amplifier
Thermopile Amplifier
Portable Instrumentation
Medical Instrumentation
Precision Low-side Current Sensing
DESCRIPTION
The LMP8358 is a precision programmable-gain
instrumentation amplifier in TI's LMP™ precision
amplifier family. Its gain can be programmed to 10,
20, 50, 100, 200, 500, or 1000 through an SPIcompatible serial interface or through a parallel
interface. Alternatively, its gain can be set to an
arbitrary value using two external resistors. The
LMP8358 uses patented techniques to measure and
continuously correct its input offset voltage,
eliminating offset drift over time and temperature and
the effect of 1/f noise. Its ground-sensing CMOS input
features a high CMRR and low input bias currents. It
is capable of sensing differential input voltages in a
common-mode range that extends from 100mV below
the negative supply to 1.4V below the positive supply,
making it an ideal solution for interfacing with groundreferenced sensors, supply-referenced sensor
bridges, and any other application requiring precision
and long-term stability. Additionally, the LMP8358
includes fault detection circuitry to detect open and
shorted inputs and deteriorating connections to the
signal source. Other features that make the LMP8358
a versatile solution for many applications are its railto-rail output, low input voltage noise and high gainbandwidth product.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
LMP8358
SNOSB09B – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Typical Application
+5V
0.1 PF
10 PF
+
EMI
R1
+
V
+IN
R4
1
7
OUT
6
-IN
R2
2
R3
5
VHSER/VLPAR
+3.3V
8
4
VLSER/VHPAR
10
VBRIDGE
3
FB
REFF
VREF
REFS
LMP8358
SDI/G1
MICRO
CONTROLLER
SCK/G2
CSB/SHDN
14
13
SDO/G0
To Next SPI Device
12
11
9
-
V
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance
(3)
(1) (2)
Human Body Model
2kV
Machine Model
200V
Charge Device
1kV
VIN Differential (V+IN − V−IN)
Output Short Circuit Duration
VS
(4)
Any pin relative to V−
6V, −0.3V
V+ +0.3V, V− −0.3V
+IN, −IN, OUT Pins
+IN, −IN Pins
±10 mA
−65°C to 150°C
Storage Temperature Range
Junction Temperature
(5)
150°C
For soldering specifications: see product folder at www.ti.com and http://www.ti.com/lit/SNOA549.
(1)
(2)
(3)
(4)
(5)
2
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but for which specific performance is not ensured. For ensured specifications and the test
conditions, see Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22–A115–A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22–C101–C (ESD FICDM std. of JEDEC).
The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit
operation at elevated ambient temperature can exceed the maximum allowable junction temperature of 150°C.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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Operating Ratings
(1)
−40°C to 125°C
Temperature Range
Supply Voltage (VS = V+ – V−)
2.7V to 5.5V
VIN Differential (V+IN − V−IN)
Package Thermal Resistance (θJA (2))
(1)
(2)
±100mV
14-Pin SOIC
145°C/W
14-Pin TSSOP
135°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but for which specific performance is not ensured. For ensured specifications and the test
conditions, see Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
3.3V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C. V+ = 3.3V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN,
FILT, PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
VOS
Input Offset Voltage
TCVOS
Typ (2)
Max (1)
VCM = V+/2
1
10
15
VCM = 0V
1
10
15
Parameter
Input Offset Voltage Temperature Drift (3)
Conditions
Min (1)
VCM = V+/2
50
VCM = 0V
50
CMRR
Common Mode Rejection Ratio
V− − 0.1V ≤ VCM ≤ V+ − 1.4V
110
105
CMVR
Common Mode Voltage Range
CMRR ≥ 110 dB
−0.1
V− + 0.1V ≤ VREFF ≤ V+ − 1.4V
110
105
145
PSRR
Power supply Rejection Ratio
2.7V ≤ V+ ≤ 5.5V
112
105
138
EMIRR
Electro Magnetic Interference Rejection
Ratio
+IN / −IN, VRF = 100 mVP, f = 900 MHz
83
+IN / −IN, VRF = 100 mVP, f = 1800 MHz
93
nV/°C
dB
1.9
ZINDM
Differential Input Impedance
50||1
ZINCM
Common Mode Input Impedance
50||1
VINDM
Differential Mode Input Voltage
IB
Input Bias Current
IOS
Input Offset Current
en
Input Voltage Noise Density
(3)
µV
139
VREFRR VREF Rejection Ratio
(1)
(2)
Units
V
dB
dB
dB
MΩ ‖ pF
MΩ ‖ pF
±100
mV
0.006
1.2
2
nA
0.1
112
pA
Gain = 10, f = 1 kHz
27
Gain = 20, f = 1 kHz
31
Gain = 50, f = 1 kHz
28
Gain = 100, f = 1 kHz
27
Gain = 200, f = 1 kHz
28
Gain = 500, f = 1 kHz
28
Gain = 1000, f = 1 kHz
27
Gain = External, f = 1 kHz
27
nV/√Hz
All limits are specified by testing or statistical analysis.
Typical Values indicate the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
The offset voltage average drift is determined by dividing the value of VOS at the temperature extremes by the total temperature change.
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SNOSB09B – APRIL 2010 – REVISED MARCH 2013
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3.3V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C. V+ = 3.3V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN,
FILT, PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
en
Parameter
Input Voltage Noise
Min (1)
Conditions
Typ (2)
Gain = 10, 0.1 Hz < f < 10 Hz
0.9
Gain = 20, 0.1 Hz < f < 10 Hz
0.6
Gain = 50, 0.1 Hz < f < 10 Hz
0.6
Gain = 100, 0.1 Hz < f < 10 Hz
0.7
Gain = 200, 0.1 Hz < f < 10 Hz
0.6
Gain = 500, 0.1 Hz < f < 10 Hz
0.6
Gain = 1000, 0.1 Hz < f < 10 Hz
0.6
Gain = External, 0.1 Hz < f < 10 Hz
0.6
Max (1)
Units
µVPP
In
Input Current Noise Density
Gain = 100, f = 1 kHz
0.5
GE
Gain Error
Gain = 10, 20, 50, 100, 200, 500
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.1
0.15
%
GE
Gain Error
Gain = 1000
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.15
0.25
%
GE
Gain Error Contribution from Chip
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
Gain Error Temperature Coefficient
For all gain settings (internal and external),
VOUT = VREF + 1V and
VOUT = VREF − 1V
3
16
ppm/°C
3.3
100
ppm
NL
Non-Linearity
GBW
Gain Bandwidth
BW
SR
(4)
4
−3 dB Bandwidth
Slew Rate (4)
COMP[2:0] =000b, Gain > 10
8
COMP[2:0] = 001b, Gain > 30
24
COMP[2:0] = 010b, Gain > 200
80
COMP[2:0] = 011b, Gain > 300
240
COMP[2:0] = 1xxb, Gain > 1
0.8
Gain = 10, COMP[2:0] = 000b
900
Gain = 10, COMP[2:0] = 1xxb
70
Gain = 20, COMP[2:0] = 000b
400
Gain = 20, COMP[2:0] = 1xxb
37
Gain = 50, COMP[2:0] = 001b
490
Gain = 50, COMP[2:0] = 1xxb
16
Gain = 100, COMP[2:0] = 010b
680
Gain = 100, COMP[2:0] = 1xxb
8
Gain = 200, COMP[2:0] = 010b
195
Gain = 200, COMP[2:0] = 1xxb
4
Gain = 500, COMP[2:0] = 011b
130
Gain = 500, COMP[2:0] = 1xxb
1.5
Gain = 1000, COMP[2:0] = 011b
89
Gain = 1000, COMP[2:0] = 1xxb
0.8
COMP[2:0] = 000b, 10% to 90% of Step,
VOUT = 2 VPP
1.6
COMP[2:0] = 001b, 10% to 90% of Step,
VOUT = 2 VPP
3.8
COMP[2:0] = 010b, 10% to 90% of Step,
VOUT = 2 VPP
6.5
COMP[2:0] = 011b, 10% to 90% of Step,
VOUT = 2 VPP
9.3
COMP[2:0] = 1xxb, 10% to 90% of Step,
VOUT = 2 VPP
0.17
pA/√Hz
%
MHz
kHz
V/µs
Slew rate is the average of the rising and falling slew rates.
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LMP8358
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SNOSB09B – APRIL 2010 – REVISED MARCH 2013
3.3V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C. V+ = 3.3V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN,
FILT, PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Min (1)
Conditions
Typ (2)
Max (1)
ts
0.01% Settling Time
2 V Step, CL = 10 pF, COMP[2:0] = 011b
VOUT
Output Voltage Swing High
RL = 2 kΩ to V+/2
32
40
RL = 10 kΩ to V+/2
12
17
RL > 1 MΩ to V+/2
7
12
RL = 2 kΩ to V+/2
28
38
RL = 10 kΩ to V+/2
12
17
RL > 1 MΩ to V+/2
8
13
Output Voltage Swing Low
IOUT
IS
µs
mV from
top rail
mV from
bottom
rail
Output Current Sourcing
VOUT tied to V+/2
21
15
28
Output Current Sinking
VOUT tied to V+/2
32
25
37
Supply Current
Fault detection off, VIN DIFF = 0V
1.8
2.1
mA
Fault detection on, VIN DIFF = 0V
1.9
2.2
mA
0.014
1
µA
15
mV
in Shutdown
TSD_ON
Turn-on time from Shutdown
PSE
Prescaler Error (Offset + Gain Error)
Fault Detection: Test Current
mA
85
VCM = V+/2
5
Prescaler Gain Factor
ITEST
Units
4
µs
0.02
+
Setting 1 (CUR[2:0] = 001b), VCM < V −
1.15V
V/V
10
+
Setting 2 (CUR[2:0] = 010b), VCM < V −
1.15V
100
Setting 3 (CUR[2:0] = 011b), VCM < V+ −
1.15V
1
+
Setting 4 (CUR[2:0] = 100b), VCM < V −
1.15V
10
Setting 5 (CUR[2:0] = 101b), VCM < V+ −
1.15V
100
nA
nA
µA
µA
µA
5.0V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C. V+ = 5.0V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN,
FILT, PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
VOS
Input Offset Voltage
TCVOS
(1)
(2)
(3)
Typ (2)
Max (1)
VCM = V+/2
0.9
10
15
VCM = 0V
0.9
10
15
Parameter
Input Offset Voltage Temperature Drift (3)
Conditions
Min (1)
VCM = V+/2
50
VCM = 0V
50
Units
µV
nV/°C
All limits are specified by testing or statistical analysis.
Typical Values indicate the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
The offset voltage average drift is determined by dividing the value of VOS at the temperature extremes by the total temperature change.
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LMP8358
SNOSB09B – APRIL 2010 – REVISED MARCH 2013
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5.0V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C. V+ = 5.0V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN,
FILT, PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Min (1)
Typ (2)
V − 0.1V ≤ VCM ≤ V − 1.4V
116
105
142
VREFRR VREF Rejection Ratio
V− + 0.1V ≤ VREFF ≤ V+ − 1.4V
115
105
150
CMVR
Common Mode Voltage Range
CMRR ≥ 115 dB
−0.1
PSRR
Power supply Rejection Ratio
2.7V ≤ V+ ≤ 5.5V
112
105
EMIRR
Electro Magnetic Interference Rejection
Ratio
+IN / −IN, VRF = 100 mVP, f = 900 MHz
83
+IN / −IN, VRF = 100 mVP, f = 1800 MHz
93
Symbol
CMRR
Parameter
Common Mode Rejection Ratio
Conditions
−
+
Differential Input Impedance
50||1
Common Mode Input Impedance
50||1
VINDM
Differential Mode Input Voltage
IB
Input Bias Current
IOS
Input Offset Current
en
Input Voltage Noise Density
Input Voltage Noise
dB
3.6
ZINCM
Units
dB
138
ZINDM
en
Max (1)
V
dB
dB
MΩ ‖ pF
MΩ ‖ pF
±100
mV
0.006
1.2
2
nA
0.2
113
pA
Gain = 10, f = 1 kHz
25
Gain = 20, f = 1 kHz
28
Gain = 50, f = 1 kHz
26
Gain = 100, f = 1 kHz
25
Gain = 200, f = 1 kHz
28
Gain = 500, f = 1 kHz
26
Gain = 1000, f = 1 kHz
25
Gain = External, f = 1 kHz
25
Gain = 10, 0.1 Hz < f < 10 Hz
0.7
Gain = 20, 0.1 Hz < f < 10 Hz
0.7
Gain = 50, 0.1 Hz < f < 10 Hz
0.5
Gain = 100, 0.1 Hz < f < 10 Hz
0.6
Gain = 200, 0.1 Hz < f < 10 Hz
0.6
Gain = 500, 0.1 Hz < f < 10 Hz
0.5
Gain = 1000, 0.1 Hz < f < 10 Hz
0.6
Gain = External, 0.1 Hz < f < 10 Hz
0.6
nV/√Hz
µVPP
In
Input Current Noise Density
Gain = 100, f = 1 kHz
0.5
GE
Gain Error
Gain = 10, 20, 50, 100, 200, 500
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.1
0.15
%
GE
Gain Error
Gain = 1000
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.15
0.25
%
GE
Gain Error Contribution from chip
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
Gain Error Temperature Coefficient
For all gain settings (internal and external),
VOUT = VREF + 1V and
VOUT = VREF − 1V
3
16
ppm/°C
3
100
ppm
NL
Non-Linearity
GBW
Gain Bandwidth
6
COMP[2:0] = 000b, Gain > 10
8
COMP[2:0] = 001b, Gain > 100
24
COMP[2:0] = 010b, Gain > 200
80
COMP[2:0] = 011b, Gain > 500
240
COMP[2:0] = 1xxb,
Gain => 1
0.8
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pA/√Hz
%
MHz
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Product Folder Links: LMP8358
LMP8358
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SNOSB09B – APRIL 2010 – REVISED MARCH 2013
5.0V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C. V+ = 5.0V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN,
FILT, PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
Parameter
−3 dB Bandwidth
BW
Slew Rate (4)
SR
Conditions
Min (1)
Typ (2)
Gain = 10, COMP[2:0] = 000b
930
Gain = 10, COMP[2:0] = 1xxb
74
Gain = 20, COMP[2:0] = 000b
385
Gain = 20, COMP[2:0] = 1xxb
37
Gain = 50, COMP[2:0] = 001b
460
Gain = 50, COMP[2:0] = 1xxb
16
Gain = 100, COMP[2:0] = 010b
640
Gain = 100, COMP[2:0] = 1xxb
8
Gain = 200, COMP[2:0] = 010b
195
Gain = 200, COMP[2:0] = 1xxb
4
Gain = 500, COMP[2:0] = 011b
130
Gain = 500, COMP[2:0] = 1xxb
1.5
Gain = 1000, COMP[2:0] = 011b
89
Gain = 1000, COMP[2:0] = 1xxb
0.8
COMP[2:0] = 000b, 10% to 90% of Step,
VOUT = 2 VPP
1.7
COMP[2:0] = 001b, 10% to 90% of Step,
VOUT = 2 VPP
5.0
COMP[2:0] = 010b, 10% to 90% of Step,
VOUT = 2 VPP
9.0
COMP[2:0] = 011b, 10% to 90% of Step,
VOUT = 2 VPP
11.0
COMP[2:0] = 1xxb, 10% to 90% of Step,
VOUT = 2 VPP
0.16
4
Max (1)
kHz
V/µs
ts
0.01% Settling Time
2 V Step, CL = 10 pF, COMP[2:0] = 011b
VOUT
Output Voltage Swing High
RL = 2 kΩ to V+/2
52
62
RL = 10 kΩ to V+/2
22
30
RL > 1 MΩ to V+/2
12
17
RL = 2 kΩ to V+/2
42
55
RL = 10 kΩ to V+/2
16
22
RL > 1 MΩ to V+/2
12
17
Output Voltage Swing Low
IOUT
IS
µs
mV from
top rail
mV from
bottom
rail
Output Current Sourcing
VOUT tied to V+/2
23
16
31
Output Current Sinking
VOUT tied to V+/2
34
30
41
Supply Current
Fault detection off, VIN DIFF = 0V
1.8
2.1
mA
Fault detection on, VIN DIFF = 0V
1.9
2.2
mA
0.006
1
µA
8
mV
in Shutdown
TSD_ON
Turn-on time from Shutdown
PSE
Prescaler Error (Offset + Gain Error)
mA
85
VCM = V+/2
Prescaler Gain Factor
(4)
Units
5
µs
0.02
V/V
Slew rate is the average of the rising and falling slew rates.
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5.0V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C. V+ = 5.0V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN,
FILT, PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
ITEST
Parameter
Fault Detection: Test Current
Min (1)
Conditions
Typ (2)
+
Max (1)
Units
Setting 1 (CUR[2:0] = 001b), VCM < V −
2.25V
10
nA
Setting 2 (CUR[2:0] = 010b), VCM < V+ −
2.25V
100
nA
Setting 3 (CUR[2:0] = 011b), VCM < V+ −
2.25V
1
µA
Setting 4 (CUR[2:0] = 100b), VCM < V+ −
2.25V
10
µA
Setting 5 (CUR[2:0] = 101b), VCM < V+ −
2.25V
100
µA
Electrical Characteristics (Serial Interface)
Unless otherwise specified, all limits ensured for TA = 25°C, V+ − V− ≥ 2.7V, V+ ≥ VHSER/VLPAR, V− ≤ VLSER/VHPAR, VD =
(VHSER/VLPAR) − (VLSER/VHPAR) ≥ 2.5V.
Symbol
Parameter
Conditions
Min (1)
Typ (2)
Max (1)
Units
0.3 × VD
V
VIL
Input Logic Low Threshold
VIH
Input Logic High Threshold
VOL
Output Logic Low Threshold
ISDO = 2mA
VOH
Output Logic High Threshold
ISDO = 2mA
ISDO
Output Source Current, SDO
VD = 3.3V or 5.0V,
CSB = 0V, VOH = V+ – 0.7V
−2
Output Sink Current, SDO
VD = 3.3V or 5.0V,
CSB = 0V, VOL = 1.0V
2
IOZ
Output Tri-state Leakage Current,
SDO
VD = 3.3V or 5.0V,
CSB = VD = 3.3V or 5V
t1
High Period, SCK
(3)
100
ns
t2
Low Period, SCK
(3)
100
ns
t3
Set Up Time, CSB to SCK
(3)
50
ns
t4
Set Up Time, SDI to SCK
(3)
30
ns
t5
Hold Time, SCK to SDI
(3)
10
t6
Prop. Delay, SCK to SDO
(3)
t7
Hold Time, SCK Transition to CSB
Rising Edge
(3)
50
ns
t8
CSB Inactive
(3)
50
ns
t9
Prop. Delay, CSB to SDO Active
(3)
50
ns
t10
Prop. Delay, CSB to SDO Inactive
(3)
50
ns
t11
Hold Time, SCK Transition to CSB
Falling Edge
(3)
10
tr/tf
Signal Rise and Fall Times
(3)
1.5
(1)
(2)
(3)
8
0.7 × VD
V
0.2
V
VD − 0.2V
mA
±1
µA
ns
60
ns
ns
5
ns
All limits are specified by testing or statistical analysis.
Typical Values indicate the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Load for these tests is shown in the Timing Diagram Test Circuit.
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Connection Diagram
+IN
-IN
REFS
REFF
FB
OUT
V
+
1
14
2
13
3
12
4
11
5
10
6
9
7
8
SDO/G0
SDI/G1
SCK/G2
CSB/SHDN
VLSER/VHPAR
-
V
VHSER/VLPAR
Figure 1. 14-Pin SOIC/ 14-Pin TSSOP
Top View
Pin Descriptions
Pin Name
Communication Mode
Serial
Parallel
+IN
Positive Input
−IN
Negative Input
REFS
Reference Sense
REFF
Reference Force
FB
Feedback
OUT
Output
V+
Positive Supply
VHSER/VLPAR
Set High
V−
VLSER/VHPAR
Set Low
Negative Supply
Set Low
Set High
CSB/SHDN
Chip Select
Shutdown (Active High)
SCK/G2
Serial Clock
Gain (MSB)
SDI/G1
Serial Data In
Gain
SDO/G0
Serial Data Out
Gain (LSB)
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Block Diagram
+
V
7
+IN
1
-IN
2
COMP[2:0]
Diff In
+
Zero/Cal
1/50
+IN/50
1/50
-IN/50
V
-
PIN
+
gm
-
OUTPUT
AMP
+
FB
4
REFF
3
REFS
S2
+
SH
DN
0]
[ 2:
MP
O
C
PIN
gm
CU
2: 0
R[
]
S1
GAIN SET
-
T
FIL
G[2:0]
VLSER/VHPAR 10
VHSER/VLPAR
5
POL MUX[1:0]
FAULT
DETECTION
:0]
]
X[1 OL
2:0
G[
P
MU
OUT
FILT
CUR[2:0]
V
6
CONTROL
INTERFACE
8
14
SDO/G0
13
SDI/G1
12
SCK/G2
11
CSB/SHDN
9
-
V
Figure 2. 14-Pin SOIC/ 14-Pin TSSOP
10
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Timing Diagrams
SCK
t11
t3
t2
t1
t4
t5
t7
t11
CSB
SDI
D15
t9
SDO
t8
D14
D0
t6
t10
OLD D15
OLD D1
OLD D0
Figure 3. SPI Timing Diagram
IOL
200 PA
+
TO PIN
V /2
CL
10 pF
IOH
200 PA
Figure 4. Timing Diagram Test Circuit
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Typical Performance Characteristics
V+ = 3.3V and TA = 25°C unless otherwise noted.
Gain
vs.
Frequency for Various COMP Settings
Gain
vs.
Frequency for Various COMP Settings
30
50
20
40
COMP = 000
10
GAIN (dB)
GAIN (dB)
COMP = 000
COMP = 100
0
COMP = 001
30 COMP = 010
COMP = 100
20
-10 GAIN = 10
GAIN = 100
+
+
V = +2.5V
V = +2.5V
-
-
V = -2.5V
-20
100
V = -2.5V
1k
10k
100k
1M
10
100
10M
1k
10k
FREQUENCY (Hz)
100k
1M
10M
FREQUENCY (Hz)
Figure 5.
Figure 6.
Gain
vs.
Frequency for Various COMP Settings
Gain
vs.
Frequency for Various Cap Loads
70
CL = 200 pF
30
COMP = 011
60
50
GAIN (dB)
GAIN (dB)
20
COMP = 010
40 COMP = 001
COMP = 000
COMP = 100
30 GAIN = 1000
10
CL = 100 pF
0
-10
GAIN = 10
COMP = 000
-20 V+ = +2.5V
+
V = +2.5V
-
-
V = -2.5V
20
100
1k
CL = 10 pF
V = -2.5V
10k
100k
1M
CL = 200 pF
CL = 10 pF
100k
10M
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7.
Figure 8.
Gain
vs.
Frequency for Various Cap Loads
Gain Error
vs.
Common Mode Voltage, VS = 5V
0.03
50
GAIN = 10
0.02
30
GAIN ERROR (%)
GAIN (dB)
40
CL = 200 pF
20
10
GAIN = 100 CL = 100 pF
COMP = 000
CL = 10 pF
0 V+ = +2.5V
C
L = 200 pF
V = -2.5V
10k
100k
1M
0.01
0
-0.01
-0.02
+
V = +5V
-
10M
V = 0V
-0.03
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FREQUENCY (Hz)
VCM (V)
Figure 9.
12
GAIN = 100
Figure 10.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA = 25°C unless otherwise noted.
Gain Error
vs.
Common Mode Voltage, VS = 3.3V
Gain Error Distribution, Gain = 10, VS = 3.3V
25
0.03
SAMPLE SIZE = 10000
GAIN = 10
RELATIVE FREQUENCY (%)
GAIN ERROR (%)
+
V = +1.65V
0.02
0.01
0
-0.01
GAIN = 100
-0.02
GAIN = 10
+
-
20
V = -1.65V
15
10
5
V = +3.3V
-
-0.03
-0.5
V = 0V
0.0
0.5
1.0
1.5
0
-0.1
2.0
-0.06
VCM (V)
-0.02
0.02
0.06
GAIN ERROR (%)
0.1
Figure 11.
Figure 12.
Gain Error Distribution, Gain = 100, VS = 3.3V
Gain Error Distribution, Gain = 1000, VS = 3.3V
SAMPLE SIZE = 10000
SAMPLE SIZE = 10000
+
40
RELATIVE FREQUENCY (%)
25
GAIN = 100
-
V = -1.65V
35
GAIN = 1000
+
V = +1.65V
V = +1.65V
RELATIVE FREQUENCY (%)
45
30
25
20
15
10
-
20
V = -1.65V
15
10
5
5
0
-0.1
-0.06
-0.02
0.02
0.06
GAIN ERROR (%)
0
-0.1
0.1
-0.06
-0.02
0.02
0.06
GAIN ERROR (%)
Figure 13.
Figure 14.
VOS Distribution, VS = 3.3V
35
35
GAIN = 1000
30
VOS Distribution, VS = 5.0V
SAMPLE SIZE = 10000
GAIN = 1000
+
+
V = +1.65V
RELATIVE FREQUENCY (%)
RELATIVE FREQUENCY (%)
SAMPLE SIZE = 10000
0.1
-
V = -1.65V
25
20
15
10
V = +2.5V
30
-
V = -2.5V
25
20
15
10
5
5
0
-7
0
-7
-5
-3
-1
1
3
5
7
-5
-3
-1
1
3
5
7
VOS (PV)
VOS (PV)
Figure 15.
Figure 16.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA = 25°C unless otherwise noted.
TCVOS Distribution, VS = 3.3V
SAMPLE SIZE = 8400
TCVOS Distribution, VS = 5V
SAMPLE SIZE = 8400
Gain = 1000
Gain = 1000
+
V = +2.5V
+
-
40
35
30
25
20
15
10
5
0
V = -1.65V
-0.02
-0.01
0
0.01
RELATIVE FREQUENCY (%)
RELATIVE FREQUENCY (%)
V = +1.65V
-
40
35
30
25
20
15
10
5
0
V = -2.5V
-0.02
0.02
-0.01
Figure 18.
VOS
vs.
VCM, VS = 3.3V
VOS
vs.
VCM, VS = 3.3V
-40°C
-40°C
VOS (PV)
-0.25
25°C
-0.50
125°C
-0.75
25°C
-0.50
-0.75
GAIN = 100
+
V = +1.65V
-1.00
125°C
GAIN = 1000
+
V = +1.65V
-1.00
-
-
V = -1.65V
-1.9
-1.5
-1.1
-0.7
-0.3
0.1
V = -1.65V
0.5
-1.9
-0.8
-0.7
-0.3
0.1
Figure 19.
Figure 20.
VOS
vs.
VCM, VS = 5.0V
VOS
vs.
VCM, VS = 5.0V
0.5
0.2
0
VOS (PV)
-40°C
-0.4
-0.6
-1.1
VCM (V)
0
-0.2
-1.5
VCM (V)
0.2
25°C
125°C
-0.2
-40°C
-0.4
-0.6
25°C
-0.8
GAIN = 100
+
V = +2.5V
-1.0
-1.0
GAIN = 1000
125°C
+
V = +2.5V
-
-
V = -2.5V
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5
14
0.02
0.00
-0.25
VOS (PV)
0.01
Figure 17.
0.00
VOS (PV)
0
TCVOS (PV/oC)
TCVOS (PV/oC)
0
V = -2.5V
0.5 1.0 1.5
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5
VCM (V)
VCM (V)
Figure 21.
Figure 22.
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0.5 1.0 1.5
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA = 25°C unless otherwise noted.
VOS
vs.
VREF, VS = 3.3V
CMRR
vs.
Frequency
140
-40°C
0
120
-0.3
GAIN = 10
+
CMR (dB)
VOS (PV)
V = +1.65V
-
-0.6 V = -1.65V
25°C
100
80
-0.9
125°C
60 GAIN = 1000
+
-1.2
V = +2.5V
-
-1.9
-1.5
-1.1
-0.7
-0.3
0.1
40
0.5
V = -2.5V
10
100
1k
Figure 23.
Figure 24.
CMRR
vs.
Frequency
PSRR
vs.
Frequency
140
140
120
130
100
120
80
100k
+
V = +4.5V to +1.7V
-
V = -1.65V
100
10k
110
-
1k
10k
FREQUENCY (Hz)
90
10
100k
V = -1V
100
1k
FREQUENCY (Hz)
Figure 26.
Voltage Noise
vs.
Time
Voltage Noise
vs.
Frequency
INPUT REFERRED VOLTAGE NOISE (nV/€Hz)
Figure 25.
200 nV/DIV
10
100k
100 GAIN = 1000
60 GAIN = 1000
+
V = +1.65V
40
10k
FREQUENCY (Hz)
PSR (dB)
CMR (dB)
VREF (V)
GAIN = 1000
+
V = +2.5V
-
V = -2.5V
1 s/DIV
50
40
30
20
10 GAIN = 1000
+
V = +2.5V
-
0
1
V = -2.5V
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 27.
Figure 28.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA = 25°C unless otherwise noted.
Small Signal Step Response for Various COMP Settings
Small Signal Step Response for Various COMP Settings
COMP = 011
GAIN = 1000
+
V = +2.5V
-
V = -2.5V
20 mV/DIV
20 mV/DIV
COMP = 010
COMP = 001
COMP = 000
COMP = 100
COMP = 100
COMP = 011
COMP = 000
COMP = 001
COMP = 010
GAIN = 1000
+
V = +2.5V
-
V = -2.5V
100 Ps/DIV
100 Ps/DIV
Figure 29.
Figure 30.
Large Signal Step Response for Various COMP Settings
Large Signal Step Response for Various COMP Settings
GAIN = 1000
+
V = +2.5V
-
V = -2.5V
COMP = 100
COMP = 011
0.5V/DIV
0.5V/DIV
COMP = 010
COMP = 001
COMP = 000
COMP = 100
COMP = 000
COMP = 001
COMP = 010
GAIN = 1000
+
V = +2.5V
COMP = 011
-
V = -2.5V
100 Ps/DIV
100 Ps/DIV
Figure 31.
Figure 32.
Positive Overshoot
vs.
CLOAD
Supply Current
vs.
Supply Voltage
2.2
2.1
125°C
2.0
25°C
IS (mA)
200 mV/DIV
CL = 100 pF
CL = 200 pF
CL = 10 pF
GAIN = 10
COMP = 000
VIN = 0.1V
1.9
1.8
1.7
-40°C
+
V = +2.5V
1.6
-
V = -2.5V
CUR[2:0] = 000b
1.5
2.7
1 Ps/DIV
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VS (V)
Figure 33.
16
Figure 34.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA = 25°C unless otherwise noted.
Input Bias Current
vs.
VCM, VS = 3.3V
1.0
Input Bias Current
vs.
VCM, VS = 5.0V
1.0
0.5
0.5
0
IB (nA)
IB (nA)
25°C
25°C
0
-40°C
-0.5
-40°C
-0.5
-1.0
-1.0
-1.5
-1.5
+
-2.0
+
V = +2.5V
V = +1.65V
-1.5
-1.1
-0.7
-0.3
0.1
-
V = -2.5V
125°C
-
V = -1.65V
125°C
-2.0
-1.9
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
0.5
VCM (V)
VCM (V)
1
Figure 35.
Figure 36.
THD+N
vs.
Frequency
THD+N
vs.
VOUT
+
-50
-
V = +2.5V, V = -2.5V
GAIN = 1000
VOUT = 2VPP
-60
THD+N (%)
THD+N (dBV)
Gain = 1000
0.1
Gain = 100
0.01
-70
GAIN = 100
-80
+
V = +2.5V
Gain = 10
0.001
10
100
1k
10k
-90
GAIN = 10
-100
0
1
-
V = -2.5V
f = 1 kHz
BW = 22 kHz
2
FREQUENCY (Hz)
Figure 37.
Figure 38.
ITEST1
vs.
VCM
ITEST2
vs.
VCM
12.0
106
CUR[2:0] = 001b
11.5
5
+
V = +2.5V
-
-
V = -2.5V
V = -2.5V
105
-40°C
ITEST (nA)
ITEST (nA)
4
CUR[2:0] = 010b
+
V = +2.5V
11.0
3
VOUT (V)
10.5
25°C
104
10.0
25°C
103
125°C
9.5
125°C
9.0
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
- 40°C
102
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
VCM (V)
VCM (V)
Figure 39.
Figure 40.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA = 25°C unless otherwise noted.
ITEST3
vs.
VCM
ITEST4
vs.
VCM
1.10
10.40
CUR[2:0] = 011b
CUR[2:0] = 100b
+
+
V = +2.5V
1.08
10.38
V = -2.5V
ITEST (PA)
ITEST (PA)
V = +2.5V
-
1.06
-40°C
1.04
1.02
-
V = -2.5V
25°C
10.36
-40°C
10.34
10.32
25°C
125°C
125°C
10.30
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
1.00
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
VCM (V)
VCM (V)
Figure 41.
Figure 42.
ITEST5
vs.
VCM
Output Swing High
vs.
Supply Voltage
103.0
125°C
15
VOUT FROM RAIL (mV)
25°C
ITEST (PA)
102.5
102.0
- 40°C
101.5
13
25°C
11
9
-40°C
7
CUR[2:0] = 101b
125°C
+
5
V = +2.5V
RL = 10 kÖ
-
V = -2.5V
101.0
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
VCM (V)
Figure 44.
Output Swing Low
vs.
Supply Voltage
EMIRR IN+
vs.
Frequency
140
GAIN = 10
+
120 V = +2.5V
V = -2.5V
100
125°C
12
10
25°C
9
EMIRR (dB)
VOUT FROM RAIL (mV)
Figure 43.
7
6
80
60
40
-40°C
4
20
RL = 10 kÖ
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
0.1
1
10
100
1000
10000
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
Figure 45.
18
Figure 46.
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APPLICATION INFORMATION
INTRODUCTION
The LMP8358 is a precision programmable gain instrumentation amplifier. Its gain can be programmed to 10, 20,
50, 100, 200, 500 or 1000 through an SPI-compatible serial interface or through a parallel interface. Alternatively,
its gain can be set to an arbitrary value using external resistors. Note that at low gains the dynamic range is
limited by the maximum input differential voltage of ±100mV. The LMP8358 uses patented techniques to
measure and continuously correct its input offset voltage, eliminating offset drift over time and temperature, and
the effect of 1/f noise. Its ground sensing CMOS input features a high CMRR and low input bias currents. It is
capable of sensing differential input voltages in a common-mode range that extends from 100 mV below the
negative supply to 1.4V below the positive supply, making it an ideal solution for interfacing with groundreferenced sensors, supply-referenced sensor bridges, and any other application requiring precision and long
term stability. Additionally, the LMP8358 includes fault detection circuitry, so open and shorted inputs can be
detected, as well a deteriorating connection to the signal source. Other features that make the LMP8358 a
versatile solution for many applications are: its rail-to-rail output, low input voltage noise and high gain-bandwidth
product.
TRANSIENT RESPONSE TO FAST INPUTS
The LMP8358 is a current-feedback instrumentation amplifier that consists of two auto-zeroed input stages.
These two input stages are operated in a ping-pong fashion: as one stage is auto-zeroed the other stage
provides the path between the input pins and the output. The auto-zeroing decreases offset, offset drift, and 1/f
noise while the ping-pong architecture provides a continuous path between the input and the output. As with all
devices that use auto-zeroing, care must be taken with the signal frequency used with the device. On-chip
continuous auto-zero correction circuitry eliminates the 1/f noise and significantly reduces the offset voltage and
offset voltage drift; all of which are very low-frequency events. For slow-changing sensor signals, below 2kHz,
this correction is transparent. Higher-frequency signals as well as fast changing edges will show a settling and
ramping time lasting about 1μs. Like all auto-zeroing devices, if the input frequency is above the auto-zero
frequency, aliasing will occur. This can occur both at the auto-zeroing frequency of about 12kHz and the pingpong frequency of about 50kHz. If needed, a low-pass filter should be placed on the output of the LMP8358 to
filter out this disturbance.
COMMUNICATION WITH THE PART AND REGISTER DESCRIPTION
The LMP8358 supports a serial and a parallel digital interface mode as shown in Figure 47 and Figure 48.
Parallel user mode Gain is set using G0, G1 and G2 pins. The shutdown mode can be activated by asserting
SHDN. Fault detection features are unavailable.
Serial user mode The part is SPI-programmable through SDI, SCK, SDO and CSB. All features are available.
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LMP8358
G0..G2
SHDN
CONTROLLER
LMP8358
G0..G2
SHDN
LMP8358
G0..G2
SHDN
Figure 47. (A) Communication with LMP8358 in Parallel Mode
LMP8358
LMP8358
LMP8358
MISO
SCK
SCK
SCK
SCK
CONTROLLER
MOSI
SDO
SDI
CSB
SDO
SDI
CSB
SDO
SDI
CSB
CSB
Figure 48. (B) Communication with LMP8358 in Serial Mode
Communication Mode Selection
The interface mode is determined by the two interface level pins VLSER/VHPAR and VHSER/VLPAR.
VLSER/VHPAR < VHSER/VLPAR Serial Interface. VLSER= Logic low level, VHSER = Logic high level.
VLSER/VHPAR > VHSER/VLPAR Parallel interface. VLPAR = Logic low level, VHPAR = Logic high level.
The levels applied to the VLSER/VHPAR and VHSER/VLPAR pins should be between the V+ and V− levels as
shown in Figure 49.
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V+
VLSER/VHPAR
LOGIC
I/O LEVELS
VHSER/VLPAR
VSERIAL MODE
PARALLEL MODE
Figure 49. Communication Mode Selection.
PARALLEL CONTROL INTERFACE MODE
The LMP8358 is put into Parallel Mode by setting VLSER/VHPAR > VHSER/VLPAR. The register in the
LMP8358 does not control the settings of the LMP8358 in this mode. Gain and shutdown are set by placing a
high or low logic level on pins 11 (SHDN), 12 (G2), 13 (G1), and 14 (G0), as shown in Table 1 and Table 2. The
logic high and low levels are defined by the voltages on the VLSER/VHPAR and VHSER/VLPAR pins. See the
START UP AND POWER ON RESET section for power on requirements when using the parallel mode.
Table 1. Function of Digital IO Pins, Parallel Mode
Pin Name
Description
G0
Gain setting (LSB)
G1
Gain setting
G2
Gain setting (MSB)
SHDN
Shutdown (Active High)
VHPAR
Positive logic level
VLPAR
Negative logic level
Table 2. Pin Levels for Setting Gain, Parallel Mode
G2
G1
G0
Gain Setting
Bandwidth
Compensation Setting (Automatically
Set)
0
0
0
10x (power-up default)
930 kHz
000b
0
0
1
20x
385 kHz
000b
0
1
0
50x
460 kHz
001b
0
1
1
100x
640 kHz
010b
1
0
0
200x
195 kHz
010b
1
0
1
500x
130 kHz
011b
1
1
0
1000x
89 kHz
011b
1
1
1
User defined
800 kHz
1xxb
SERIAL CONTROL INTERFACE MODE
The LMP8358 is put into Serial Mode by setting VLSER/VHPAR < VHSER/VLPAR. In the Serial Mode the
LMP8358 can be programmed by using pins 11 – 14 as shown in Table 3 and the SPI Timing Diagram. The
LMP8358 contains a 16 bit register which controls the performance of the part. These bits can be changed using
the Serial Mode of communication. The register of the LMP8358 is shown in Table 4. Immediately after power on
the register should be written with the value needed for the application. See the START UP AND POWER ON
RESET section.
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Table 3. Function of Digital IO Pins, Serial Mode
Pin Name
Description
SDO
Serial Data Out
SDI
Serial Data In
SCK
Serial Clock
CSB
Chip Select
VLSER
Negative Logic level
VHSER
Positive Logic Level
Table 4. LMP8358 Register Description, Serial Mode
Bit No
Name
Description
0
G0
Gain setting (LSB)
1
G1
Gain setting
2
G2
Gain setting (MSB)
3
COMP0
Frequency compensation setting (LSB)
4
COMP1
Frequency compensation setting
5
COMP2
Frequency compensation setting (MSB)
6
MUX0
Input multiplexer selection (LSB)
7
MUX1
Input multiplexer selection (MSB)
8
POL
Input polarity switch
9
SHDN
Shutdown Enable
10
FILT
Enable filtering using external cap
11
PIN
Fault detection pin selection
12
CUR0
Fault detection current setting (LSB)
13
CUR1
Fault detection current setting
14
CUR2
Fault detection current setting (MSB)
15
N/A
Unused, set to 0
Serial Control Interface Operation
The LMP8358 gain, bandwidth compensation, shutdown, input options, and fault detection are controlled by an
on board programmable register. Data to be written into the control register is first loaded into the LMP8358 via
the serial interface. The serial interface employs an 16-bit double-buffered register for glitch-free transitions
between settings. Data is loaded through the serial data input, SDI. Data passing through the shift register is
output through the serial data output, SDO. The serial clock, SCK controls the serial loading process. All sixteen
data bits are required to correctly program the amplifier. The falling edge of CSB enables the shift register to
receive data. The SCK signal must be high during the falling and rising edge of CSB. Each data bit is clocked
into the shift register on the rising edge of SCK. Data is transferred from the shift register to the holding register
on the rising edge of CSB. Operation is shown in the SPI Timing Diagram.
The serial control pins can be connected in one of two ways when two or more LMP8358s are used in an
application.
Star Configuration
The configuration shown in Figure 50 can be used if each LMP8358 will always have the same value in each
register. After the microcontroller writes, all registers will have the same value. Using multiple CSB lines as
shown in Figure 51 allows different values to be written into each register.
22
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MOSI
LMP8358
LMP8358
LMP8358
SCK
SDI
SCK
SDI
SCK
SDI
SCK
CONTROLLER
SDO
SDO
CSB
SDO
CSB
CSB
CSB
Figure 50. Star Configuration for Writing the Same Value Into Each Register
MOSI
LMP8358
LMP8358
LMP8358
SCK
SDI
SCK
SDI
SCK
SDI
SCK
CONTROLLER
SDO
SDO
SDO
CSB1
CSB
CSB2
CSB
CSB
CSB3
Figure 51. Star Configuration for Writing Different Values Into Each Register
Daisy Chain Configuration
This configuration can be used to program the same or different values in the register of each LMP8358. The
connections are shown in Figure 52. In this configuration the SDO pin of each LMP8358 is connected to the SDI
pin of the following LMP8358.
LMP8358
LMP8358
LMP8358
MISO
SCK
SCK
SCK
SCK
CONTROLLER
MOSI
SDO
SDI
SDO
SDI
CSB
SDO
SDI
CSB
CSB
CSB
Figure 52. Daisy Chain Configuration
The following two examples show how the registers are written in the Daisy Chain Configuration.
Table 5. If all three LMP8358s need a gain of 100 with a compensation level of 010. (0000 0000 0001 0011)
Power on
Register of LMP8358 #1
Register of LMP8358 #2
Register of LMP8358 #3
Notes
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Default power on state
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Table 5. If all three LMP8358s need a gain of 100 with a compensation level of 010. (0000 0000 0001
0011) (continued)
After first two bytes are
sent
0000 0000 0001 0011
0000 0000 0000 0000
0000 0000 0000 0000
After second two bytes
are sent
0000 0000 0001 0011
0000 0000 0001 0011
0000 0000 0000 0000
After third two bytes are
sent
0000 0000 0001 0011
0000 0000 0001 0011
0000 0000 0001 0011
The data in the register of
LMP8358 #1 is shifted
into the register of
LMP8358 #2, the data in
the register of LMP8358
#2 is shifted into the
register of LMP8358 #3.
Table 6. If LMP8358 #1 needs a gain of 20 (0000 0000 0000 0001), LMP8358 #2 needs a gain of 1000 with
a compensation level of 011 (0000 0000 0001 1110), and LMP8358 #3 needs a gain of 100 with a
compenstation level of 010 (0000 0000 0001 0011).
Register of LMP8358 #1
Register of LMP8358 #2
Register of LMP8358 #3
Notes
Power on
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Default power on state
After first two bytes are
sent
0000 0000 0001 0011
0000 0000 0000 0000
0000 0000 0000 0000
After second two bytes
are sent
0000 0000 0001 1110
0000 0000 0001 0011
0000 0000 0000 0000
After third two bytes are
sent
0000 0000 0000 0001
0000 0000 0001 1110
0000 0000 0001 0011
The data in the register of
LMP8358 #1 is shifted
into the register of
LMP8358 #2, the data in
the register of LMP8358
#2 is shifted into the
register of LMP8358 #3
LMP8358 SETTINGS
Gain (Serial, Parallel)
When the LMP8358 is in Parallel Mode the gain can be set by applying a high or low level to pins 12 (G2), 13
(G1), and 14 (G0), as shown in Table 2. The Frequency Compensation bits are automatically set as shown in
Table 2 to optimize the bandwidth. In Serial Mode the gain is determined by setting G[2:0] as shown in Table 7
and the bandwidth can be changed using the Frequency Compensation bits in the register.
Table 7. Gain Setting (Register bits 2:0)
G2
G1
G0
Gain Setting
0
0
0
10x (power-up default)
0
0
1
20x
0
1
0
50x
0
1
1
100x
1
0
0
200x
1
0
1
500x
1
1
0
1000x
1
1
1
User Defined
When G[2:0] = 000b to 110b switch S1 is closed and switch S2 is open as shown in the Block Diagram.
When G[2:0] = 111b in either serial or parallel mode switch S1 is open and S2 is closed and the LMP8358 gain
is set by external resistors as shown in Figure 53. The gain is:
GAIN = 1 + (Z1/Z2)
(1)
When the gain is set by external resistors and COMP[2:0] = 1xxb, a capacitor can be used to implement a noise
reduction low pass filter. See the Filter and External Filter Capacitor (Serial) section. R1and CFILTER are placed
between the OUT and FB pins. R2 is placed between the FB and REFS pins.
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VOUT
OUT
CFILTER
R1
Z1
R2
Z2
FB
REFS
VREF
REFF
Figure 53. External Gain Set Resistors and Filter Capacitor
Frequency Compensation (Serial)
The gain-bandwidth compensation is set to one of five levels under program control. The amount of
compensation can be decreased to maximize the available bandwidth as the gain of the amplifier is increased.
The compensation level is selected by setting bits COMP[2:0] of the control register with 000b, 001b, 010b, 011b,
or 1xxb. Table 8 shows the bandwidths achieved at the selectable gain and compensation settings. Note that for
gains 10X and 20X, the recommended compensation setting is 000b. For the gain setting 50X, compensation
settings may be 000b and 001b. Gain settings 100X and 200X may use the three bandwidth compensation
settings 000b, 001b, and 010b. At gains of 500X and 1000X, all bandwidth compensation ranges may be used.
Note that for lower gains, it is possible to under compensate the amplifier into instability.
Table 8. Frequency Compensation (Register bits 5:3)
Bandwidth
Gain\COMP [2:0]
000
001
010
011
1xx
10
930 kHz
n/a
n/a
n/a
74 kHz
20
385 kHz
n/a
n/a
n/a
37 kHz
50
160 kHz
460 kHz
n/a
n/a
16 kHz
100
80 kHz
225 kHz
640 kHz
n/a
8 kHz
200
38 kHz
95 kHz
195 kHz
n/a
4 kHz
500
16 kHz
40 kHz
85 kHz
130 kHz
1.5 kHz
1000
8 kHz
22 kHz
50 kHz
89 kHz
0.8 kHz
User Defined Gain
GBW Product
> 10x
8 MHz
> 30x
24 MHz
> 100x
80 MHz
> 300x
240 MHz
> 1x
0.8 MHz
(For external filter cap)
Input Multiplexer and Polarity Switch (Serial)
The Input Multiplexer Selection bits MUX[1:0] and Polarity bit POL can be used to set the inputs of the LMP8358
to the states shown in Table 9.
Table 9. Input Multiplexer and Polarity (Register bits 8:6)
MUX1
MUX0
0
0
Diff Input for POL = 0
1
Diff Input for POL = 1
1
+
+IN
+IN
6
2
6
OUT
2
±
-IN
+
-IN
VOUT = Gain((+IN) ± (±IN))
OUT
±
VOUT = Gain((±IN) ± (+IN))
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Table 9. Input Multiplexer and Polarity (Register bits 8:6) (continued)
MUX1
MUX0
0
1
Diff Input for POL = 0
Diff Input for POL = 1
1
1
+
+IN
2
6
OUT
2
±
-IN
+
+IN
6
±
-IN
VOUT = VREF
1
OUT
VOUT = VREF
0
-
1
+IN
+IN
6
2
-IN
-
V
1
+
1/50
+
1/50
6
OUT
2
±
OUT
±
-IN
V
VOUT = Gain(+IN)/50
1
VOUT = ±Gain(+IN)/50
1
-
1
-IN
1/50
+
+IN
6
2
V
1
+
+IN
6
OUT
2
±
-IN
1/50
OUT
±
-
V
VOUT = Gain(±IN)/50
VOUT = ±Gain(±IN)/50
Polarity Reversal
When MUX[1:0] = 00b and POL = 0b the LMP8358 has the input of a normal instrumentation amplifier. The input
for the LMP8358 is defined as Gain × (V+IN − V−IN). When POL = 1b, the input for the LMP8358 is defined as
Gain × (V−IN – V+IN). Polarity reversal can be used to do system level calibration, for example, to compensate for
thermocouple voltages, residual offset of the LMP8358, or offsets of the sensor or ADC.
Short Inputs
When MUX[1:0] = 01b and POL = 0b both inputs are connected to the +IN pin of the LMP8358. The –IN pin is
left floating. When MUX[1:0] = 01b and POL = 1b both inputs are connected to the -IN pin of the LMP8358. The
+IN pin is left floating.
Compare Input to VWhen MUX[1:0] = 10b or 11b one external input of the LMP8358 is floating. The other external input is divided by
50 as shown in Table 9. The internal instrumentation amplifier input that is not connected to the external pin is
connected to V−. With a scale factor of 1/50 this gives an overall gain of 0.2x, 0.4x, 1x, 2x, 4x, 10x, or 20x
depending on what the gain is set to with G[2:0] bits as shown in Table 10.
Table 10. Overall Gain using G[2:0], MUX[1:0] and POL
G[2:0]
MUX[1:0]
POL = 0b
POL = 1b
000b
10b or 11b
0.2
−0.2
001b
10b or 11b
0.4
−0.4
010b
10b or 11b
1
−1
011b
10b or 11b
2
−2
100b
10b or 11b
4
−4
101b
10b or 11b
10
−10
110b
10b or 11b
20
−20
26
Overall System Gain
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Shutdown Enable (Serial, Parallel)
When the SHDN bit of the LMP8358 register is set to 1b the part is put into shutdown mode. It will use less than
1μA in this state.
Table 11. Shutdown (Register bit 9)
SHDN
Mode
0
Active mode
1
Shutdown mode
Filter and External Filter Capacitor (Serial)
The FILT bit controls the state of switch S2 shown in the Block Diagram. When G[2:0] = 000b to 110b, switch S2
will be open if FILT = 0b and S2 will be closed if FILT = 1b. When G[2:0] = 111b switch S2 is always closed and
does not depend on the value in the FILT bit.
When FILT = 1b and COMP[2:0] = 1xxb the LMP8358 is unity-gain stable and an external filter cap can be
applied as shown in Figure 53. The corner filter of the filter is:
F-3dB = 1/(2πRFILTERCFILTER)
(2)
RFILTER depends on the gain of the part and is shown inTable 13.
Table 12. Filter (Register bit 10)
FILT
Mode
0
No external filter cap used
1
External filter cap used
Table 13. RFILTER Value
Gain
RFILTER Value
10
18.5 kΩ
20
112 kΩ
50
168 kΩ
100
187 kΩ
200
1.12 MΩ
500
1.68 MΩ
1000
1.87 MΩ
User-Defined Gain
External Resistor R1
The tolerance of the RFILTER value for the pre-defined gains is about ±3%. If an external filter cap is not used
FILT should be set to 0b to prevent errors related to leakage currents on the FB pin.
Fault Detection Pin and Current Setting (Serial)
The LMP8358 has an internal current source that can be used to detect faults in the overall system. See the
FAULT DETECTION METHODS Section. When PIN = 0b this current source is connected to the +IN pin. When
PIN = 1b the current source is connected to the −IN pin.
Table 14. Pin Current Source (Register bit 11)
PIN
Current source is connected to
0
+IN pin
1
−IN pin
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The Fault Detection Current bit, CUR[2:0] controls the amount of current that sent to the input pin as shown in
Table 15.
Table 15. Fault Detection Current Source (Register bits 14:12)
CUR2
CUR1
CUR0
0
0
0
disconnected and powered down *
0
0
1
10 nA
0
1
0
100 nA
0
1
1
1 μA
1
0
0
10 µA
1
0
1
100 µA
1
1
0
disconnected, but powered *
1
1
1
Do Not Use
* Leaving the fault detection current source powered allows it to switch between current levels faster, particularly
when supplying currents less than 1 µA.
FAULT DETECTION METHODS
Using the Multiplexer, Polarity, and Current features the end user can detect faults in the system between the
sensor and the LMP8358. These examples will use the set up shown in Figure 54 which shows a bridge sensor
connected through some cabling to a supply and the LMP8358. The fault detection methods are described
below.
+5V
1k
+5V
1k
-
+
2.5V
1k
+IN
V
+
OUT
1k
-IN
2.5V
Figure 54. Bridge Connected to the LMP8358 With No Problems
Common Mode Out of Range
Figure 55 shows an example of a degraded connection between the bottom of the bridge and ground. This fault
is shown by the 1.5 kΩ resistor placed between the bridge and ground. This will raise the common mode at the
inputs of the LMP8358 to 4V, which is out of the CMVR. To determine the common mode voltage at the input
pins, use the 1/50 feature by setting MUX[1:0] to 10b to test the +IN pin or to 11b to test the −IN pin, POL to 0b,
and G[2:0] to 010b for a gain of 50 (0082x or 00C2x). This will give an overall gain of 1 and the output will read
4V for either MUX setting.
+5V
1k
+5V
1k
-
+
4V
1k
4V
1.5k
+IN
+
V
1k
OUT
-IN
3V
Figure 55. Degraded Connection Between the Bottom of the Bridge and Ground
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Open Input
Figure 56 shows an example of an open input fault. To sense this type of fault use the 1/50 feature by setting
MUX[1:0] to 10b to test the +IN pin or to 11b to test the −IN pin, POL to 0b, PIN to 1b to test the −IN pin, and
G[2:0] to 010b for a gain of 50, and inject 100µA current by setting CUR[2:0] = 101b (5082x or 58C2x). Since the
input is open the input pin will be pulled to V+. With an overall gain of 1 the output will read 5V for open input.
+5V
+5V
100 PA
1k
1k
-
+
5V
1k
+IN
+
V
OUT
1k
-IN
Figure 56. Open Input
Input Shorted to V+ or V−
Figure 57 shows an example of an input pin shorted to V+ or V−. To sense this fault, use the 1/50 feature by
setting MUX[1:0] to 10b to test the +IN pin or to 11b to test the −IN pin, POL to 0b, and G[2:0] to 010b for a gain
of 50 (0082x or 00C2x). This will give an overall gain of 1 and the output will read either V+ or V− depending on
whether the input pin is shorted to V+ or V−.
+5V
+5V
+5V
1k
1k
-
+
5V or GND
1k
+IN
+
V
1k
GND
OUT
-IN
Figure 57. Input Shorted to V+ or V−
Shorted Inputs
Figure 58 shows the inputs of the LMP8358 shorted. To detect this fault set CUR[2:0] = 101b to inject a 100µA
current and set the gain to 10× (5000x). The LMP8358 is set up with normal differential inputs. The output will
read about 0.07V because of the voltage drop across the internal ESD resistor, which has a value between 60Ω
to 90Ω. If the gain is set to 100× with an injected current of 100µA the output will be about 0.7V.
+5V
+5V
100 PA
1k
-
1k
+
+IN
+
V
1k
1k
OUT
-IN
Figure 58. Shorted Inputs
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Degraded Input Line
Figure 59 shows an example of a degraded connection between the bridge and the +IN pin of the LMP8358.
This fault is shown by the 1 kΩ resistor placed between the bridge and the LMP8358. To detect this fault use the
1/50 feature by setting MUX[1:0] to 10b to test the +IN pin, POL to 0b, and G[2:0] to 010b for a gain of 50. This
will give an overall gain of 1. Set CUR[2:0] = 101b to inject a 100µA current and read the output voltage (5082x).
Next set MUX[1:0] to 11b and PIN to 1b to test the −IN pin as shown in Figure 60 and read the output (58C2x). If
the voltages of these two measurements are different a degraded input fault exists.
+5V
+5V
100 PA
1k
1k
-
1k
+
2.65V
2.55V
1k
+IN
+
V
OUT
1k
2.5V
-IN
Figure 59. Degraded Input Line, Step 1
+5V
1k
-
+5V
1k
1k
+
2.5V
1k
+IN
2.5V
+
V
1k
2.55V
OUT
-IN
100 PA
Figure 60. Degraded Input Line, Step 2
Fault Detection Example
Using the fault detection features of the LMP8358 an end product, such as a scale, can periodically test that no
damage has occurred to the system. A routine can be written that could, for example, run on start up, that will
step through the fault detection features shown above and compare the output voltage to a table like that shown
in Table 16. If the circuit shown in Figure 54 is used the values shown in column 2 of Table 16 would show that
the system is working correctly, the values in the columns under the Possible Faults heading would show that
there is a potential problem and that operator attention is needed.
Table 16. Fault Detection Matrix
No Faults
Possible Faults
LMP8358
Register
VOUT
VOUT
Possible Cause
VOUT
Possible Cause
VOUT
Possible Cause
00 82x
2.5V
VOUT < CMVR or
VOUT > CMVR
Input is out of
CMVR
V+
+IN shorted to V+
0V
+IN shorted to
GND
00 C2x
2.5V
VOUT < CMVR or
VOUT > CMVR
Input is out of
CMVR
V+
−IN shorted to V+
0V
−IN shorted to
GND
50 00x
0.61V
V+
+IN Open
0.07V
Inputs shorted
50 03x
4.97V
+
V
−IN
0.7V
Inputs shorted
50 82x
2.55V
2.65V*
Degraded +IN line
58 C2x
2.55V
2.55V*
Degraded +IN line
50 82x
2.55V
2.55V*
Degraded −IN line
30
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Table 16. Fault Detection Matrix (continued)
58 C2x
2.55V
2.65V*
Degraded −IN line
* The values shown for a degraded input line will vary depending on the resistance in the line. This table uses
the value in Figure 59 and Figure 60, 1kΩ.
START UP AND POWER ON RESET
During power on, 50µs after V+ − V− > 1V the LMP8358 resets the internal register to 0000x. If the digital
supplies and inputs are undefined after the Power On Reset transients could occur which can cause erroneous
data to be written over the default values in the register. The following should be done to prevent this from
happening:
• Bring all supplies up at the same time. All power supplies, analog and digital, should be brought up together
within 40µs so that the supplies are not undefined after the Power On Reset at 50µs. This is easiest done by
tying the VHSER/VLPAR and VLSER/VHPAR pins to the analog supplies. — Parallel Mode
• Immediately after power on, write to the register the value needed for the application. (This is always
recommended.) — Serial Mode
LAYOUT
The LMP8358 is a precision device that contains both analog and digital sections as shown in the Block
Diagram. The PCB should be carefully designed to minimize the interaction between the analog and digital
sections and to maximize the performance of the part. This should include the following:
0.1µF ceramic capacitors should be placed as close as possible to each supply pin. If a digital supply pin is tied
to an analog pin only one 0.1µF capacitor is needed for both pins. A larger 1µF or 10µF capacitor should be
located near the part for each supply.
Digital and analog traces should be kept away from each other. Analog and digital traces should not run next to
each other, if they do the digital signal can couple onto the analog line. The LMP8358 pinout is set up to simplify
layout by not having analog, power, and digital pins mixed together. Pins 1 — 6 are the analog signals, pins 7 —
10 are the power pins, and pins 11 — 14 are the digital signals.
Be aware of the signal and power return paths. The return paths of the analog, digital, and power sections should
not cross each other and the return path should be underneath the respective signal or power path. The best
PCB layout is if the bottom plane of the PCB is a solid plane.
The REFF and REFS pins are connected to the bottom side of the gain resistors of the LMP8358 as shown in
the Block Diagram. Any impedance on these pins will change the specified gain. If the REFF and REFS pins are
to be connected to ground they should be tied directly to the ground plane and not through thin traces that can
add impedance. If the REFF and REFS pins are to be connected to a voltage, the voltage source must be low
impedance. This can be done by adding an op amp, such as the LMP7701, set up in a buffer configuration with
the LMP7701 output connected to REFF, the negative input of the op amp connected to REFS, and the desired
reference voltage connected to the positive input of the op amp as shown in Figure 61.
DIFFERENTIAL BRIDGE SENSOR
Non-amplified differential bridge sensors, which are used in a variety of applications, typically have a very small
differential output signal. This small signal needs to be accurately amplified before it can be used by an ADC.
The high DC performance of the LMP8358 makes it a good choice for use with a differential bridge sensor. This
performance includes low input offset voltage, low input offset voltage drift, and high CMRR. The on chip EMI
rejection filters available on the LMP8358 help remove the EMI interference introduced to the signal as shown in
Figure 61 and improves the overall system performance.
The circuit in Figure 61 shows a signal path solution for a typical bridge sensor using the LMP8358. The typical
output voltage of a resistive load cell is 2mV/V. If the bridge sensor is using a 5V supply the maximum output
voltage will be 2mV/V × 5V = 10mV. The bridge voltage in this example is the same as the LMP8358 and
ADC161S626 supply voltage of +5V. This 10mV signal must be accurately amplified by the LMP8358 to best
match the dynamic range of the ADC. This is done by setting the gain of the LMP8358 to 200 which will give an
output from the LMP8358 of 2V. To use the complete range of the ADC161S626 the VREF of the ADC should be
set to half of the input or 1V. This is done by the resistor divider on the VREF pin of the ADC161S626. The
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LMP8358
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negative input of the ADC and the REFF and REFS pins of the LMP8358 can be set to +2.5V to set the signal at
the center of the supply. A resistor divider supplies +2.5V to the positive input of an LMP7701 set up in a buffer
configuration. The LMP7701 acts as a low impedance source for the REFF pin. The VIOand VHSER/VLPAR pins
should all be set to the same voltage as the microcontroller, +3.3V in this example. The VLSER/VHPAR pin
should be connected to ground. The resistor and capacitor between the LMP8358 and the ADC161S626 serve a
dual purpose. The capacitor is a charge reservoir for the sampling capacitor of the ADC. The resistor provides
isolation for the LMP8358 from the capacitive load. The values listed in the ADC161S626 datasheet are 180Ω for
the resistor and the 470pF for the capacitor. These two components also form a low pass filter of about 1.9MHz.
If a filter is needed to attenuate disturbance from the internal auto−zeroing at 12kHz and the ping−pong
frequency at 50kHz of the LMP8358 these values could be changed to 7870Ω and 0.01µF which will make a filter
with a corner of about 2kHz.
+5V
+5V
0.1 PF
10 PF
0.1 PF
+
EMI
R1
+3.3V
0.1 PF
+
10 PF
+
+
V
+IN
R4
1
C
7
OUT
6
-IN
R2
10 PF
2
R3
5
VHSER/VLPAR
+3.3V
8
4
10
3
VLSER/VHPAR
VBRIDGE
SCLK
+ VA VIO
R
DOUT
ADC161S626
-
FB
CSB
VREF
+5V
REFF
100pF
REFS
8k
+5V
0.1 PF
LMP8358
CSB/SHDN
14
13
12
-
SCK/G2
10k
SDO/G0
LMP7701
11
2k
+
SDI/G1
MICRO
CONTROLLER
MICRO
CONTROLLER
10k
0.1 PF
9
-
V
Figure 61. Differential Bridge Sensor
32
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SNOSB09B – APRIL 2010 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMP8358MA/NOPB
ACTIVE
SOIC
D
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP8358
MA
LMP8358MAX/NOPB
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP8358
MA
LMP8358MT/NOPB
ACTIVE
TSSOP
PW
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP835
8MT
LMP8358MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP835
8MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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