LMP90080QMHX/NOPB

LMP90080-Q1 www.ti.com SNIS186A – MAY 2013 – REVISED JANUARY 2014 LMP90080-Q1 Multi-Channel 16-Bit Sensor AFE with Background Calibration Check for Samples: LMP90080-Q1 FEATURES APPLICATIONS • • • • • 1 23 • • • • • • • • • • • • • • 16-Bit Low-Power Sigma Delta ADC True Continuous Background Calibration at All Gains In-Place System Calibration Using Expected Value Programming Low-Noise Programmable Gain (1x - 128x) Continuous Background Open/Short and Out of Range Sensor Diagnostics 8 Output Data Rates (ODR) with Single-Cycle Settling 2 Matched Excitation Current Sources from 100 µA to 1000 µA 4-DIFF / 7-SE Inputs 2-DIFF / 4-SE Inputs 7 General Purpose Input/Output Pins Chopper-Stabilized Buffer for Low Offset SPI 4/3-Wire with CRC Data Link Error Detection 50 Hz to 60 Hz Line Rejection at ODR ≤13.42 SPS Independent Gain and ODR Selection per Channel Supported by WEBENCH® Sensor AFE Designer Automatic Channel Sequencer KEY SPECIFICATIONS • • • • • • • • • ENOB/NFR: Up to 16/16 Bits Offset Error (typ): 8.4 nV Gain Error (typ): 7 ppm Total Noise: 1.2*VREF/GAIN) 0x3: The modulator was over-ranged (VIN < -1.2*VREF/GAIN) [2:0] SAMPLED_CH Channel Number – the sampled channel for ADC_DOUT and SENDIAG_FLAGS. SPI Registers Table 26. SPI_HANDSHAKECN SPI Handshake Control (Address 0x01) Bit Bit Symbol [7:4] Reserved Bit Description SDO/DRDYB Driver – sets who is driving the SDO/DRYB pin [3:1] SDO_DRDYB_ DRIVER 0 SW_OFF_TRG Whenever CSB is Asserted and the Device is Reading ADC_DOUT Whenever CSB is Asserted and the Device is Not Reading ADC_DOUT CSB is Deasserted 0x0 (default) SDO is driving DRDYB is driving High-Z 0x3 SDO is driving DRDYB is driving DRDYB is driving 0x4 SDO is driving High-Z High-Z Others Forbidden Switch-off trigger - refers to the switching of the output drive from the slave to the master. 0 (default): SDO will be high-Z after the last (16th, 24th, 32nd, etc) rising edge of SCLK. This option allows time for the slave to transfer control back to the master at the end of the frame. 1: SDO’s high-Z is postponed to the subsequent falling edge following the last (16th, 24th, 32nd, etc) rising edge of SCLK. This option provides additional hold time for the last bit, DB0, in nonstreaming read transfers. Table 27. SPI_STREAMCN SPI Streaming Control (Address 0x03) Bit 7 Bit Symbol Bit Description STRM_TYPE Stream type 0 (default): Normal Streaming mode 1: Controlled Streaming mode [6:0] STRM_ RANGE 54 Stream range – selects Range for Controlled Streaming mode Default: 0x00 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LMP90080-Q1 LMP90080-Q1 www.ti.com SNIS186A – MAY 2013 – REVISED JANUARY 2014 Table 28. DATA_ONLY_1 Data Only Read Control 1 (Address 0x09) Bit Bit Symbol Bit Description 7 Reserved - [6:0] DATA_ONLY_ADR Start address for the Data Only Read Transaction Default: 0x1A Please refer to the description of DT_ONLY_SZ in Table 29 register. Table 29. DATA_ONLY_2 Data Only Read Control 2 (Address 0x0A) Bit [7:3] Bit Symbol Bit Description Reserved - DATA_ONLY_SZ Number of bytes to be read out in Data Only mode. A value of 0x0 means read one byte and 0x7 means read 8 bytes. Default: 0x2 [2:0] Table 30. SPI_DRDYBCN SPI Data Ready Bar Control (Address 0x11) Bit Bit Symbol Bit Description 7 SPI_DRDYB_D6 Enable DRDYB on D6 0 (default): D6 is a GPIO 1: D6 = drdyb signal 6 Reserved - 5 CRC_RST CRC Reset 0 (default): Enable CRC reset on DRDYB deassertion 1: Disbale CRC reset on DRDYB deassertion 4 Reserved - FGA_BGCAL Gain background calibration 0 (default): Correct FGA gain error. This is useful only if the device is operating in BgcalMode2 and ScanMode2 or ScanMode3. 1: Correct FGA gain error using the last known coefficients. 3 [2:0] Reserved Default - 0x3 (do not change this value) Table 31. SPI_CRC_CN CRC Control (Address 0x13) Bit Bit Symbol [7:5] Reserved Bit Description - 4 EN_CRC Enable CRC 0 (default): Disable CRC 1: Enable CRC 3 Reserved Default - 0x0 (do not change this value) 2 DRDYB_AFT_CRC DRDYB After CRC 0 (default): DRDYB is deasserted (active high) after ADC_DOUTL is read. 1: DRDYB is deasserted after SPI_CRC_DAT (which follows ADC_DOUTL), is read. [1:0] Reserved - Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LMP90080-Q1 55 LMP90080-Q1 SNIS186A – MAY 2013 – REVISED JANUARY 2014 www.ti.com Table 32. SPI_CRC_DAT CRC Data (Address 0x1D) Bit Bit Symbol [7:0] CRC_DAT Bit Description CRC Data When written, this register reset CRC: Any Value: Reset CRC When read, this register indicates the CRC data. GPIO Registers Table 33. GPIO_DIRCN GPIO Direction (Address 0x0E) Bit 7 x (1) Bit Symbol Bit Description Reserved - GPIO_DIRCNx GPIO direction control – these bits are used to control the direction of each General Purpose Input/Outputs (GPIO) pins D0 - D6. 0 (default): Dx is an Input 1: Dx is an Output where 0 ≤ x ≤ 6 For example, writing a 1 to bit 6 means D6 is an Output. (1) If D6 is used for DRDYB, then it cannot be used for GPIO. Table 34. GPIO_DAT GPIO Data (Address 0x0F) Bit 7 x Bit Symbol Bit Description Reserved - Dx Write Only - when GPIO_DIRCNx = 0 0: Dx is LO 1: Dx is HI Read Only - when GPIO_DIRCNx = 1 0: Dx driven LO 1: Dx driven HI where 0 ≤ x ≤ 6 For example, writing a 0 to bit 4 means D4 is LO. It is okay to Read the GPIOs that are configured as outputs and write to GPIOs that are configured as inputs. Reading the GPIOs that are outputs would return the current value on those GPIOs, and writing to the GPIOs that are inputs are neglected. 56 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LMP90080-Q1 LMP90080-Q1 www.ti.com SNIS186A – MAY 2013 – REVISED JANUARY 2014 REVISION HISTORY Changes from Revision (May 2013) to Revision A Page • Deleted CH_STS and ADC_DOUTM from the sentence: Compute the CRC externally... ................................................ 37 • Added sentence to the end of the RESET and RESTART section .................................................................................... 38 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LMP90080-Q1 57 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) LMP90080QMH/NOPB ACTIVE HTSSOP PWP 28 48 RoHS & Green SN Level-3-260C-168 HR -40 to 150 LMP90080Q MH LMP90080QMHE/NOPB ACTIVE HTSSOP PWP 28 250 RoHS & Green SN Level-3-260C-168 HR -40 to 150 LMP90080Q MH LMP90080QMHX/NOPB ACTIVE HTSSOP PWP 28 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 150 LMP90080Q MH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of