LMP91051
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SNAS581B – MARCH 2012 – REVISED MAY 2013
LMP91051 Configurable AFE for Nondispersive Infrared (NDIR) Sensing Applications
Check for Samples: LMP91051
FEATURES
1
•
•
•
•
•
•
2
Dual Channel Input
Programmable Gain Amplifier
“Dark Signal” Offset Cancellation
Supports External Filtering
Common Mode Generator and 8 Bit DAC
Package 14 Pin TSSOP
APPLICATIONS
•
•
•
•
•
•
•
NDIR Sensing
Demand Control Ventilation
Building Monitoring
CO2 Cabin Control — Automotive
Alcohol Detection — Automotive
Industrial Safety and Security
GHG & Freons Detection Platforms
KEY SPECIFICATIONS
•
•
•
•
•
Programmable Gain … 167V/V to 7986V/V
Low Noise (0.1 to 10 Hz) … 0.1µVRMS
Gain Drift … 20 ppm/°C (typ)
Phase Delay Drift … 300 ns (typ)
Power supply voltage range … 2.7V to 5.5V
DESCRIPTION
The LMP91051 is a dual channel programmable
integrated Sensor Analog Front End (AFE) optimized
for thermopile sensors, as typically used in NDIR
applications. It provides a complete signal path
solution between a sensor and microcontroller that
generates an output voltage proportional to the
thermopile voltage. The LMP91051’s programmability
enables it to support multiple thermopile sensors with
a single design as opposed to the multiple discrete
solutions.
The LMP91051 features a programmable gain
amplifier (PGA), “dark phase” offset cancellation, and
an adjustable common mode generator (1.15V or
2.59V) which increases output dynamic range. The
PGA offers a low gain range of 167V/V to 1335V/V
plus a high gain range of 1002V/V to 7986V/V which
enables the user to utilize thermopiles with different
sensitivities. The PGA is highlighted by low gain drift
(20 ppm/°C), output offset drift (230 mV/°C at
G = 1002 V/V), phase delay drift (300 ns) and noise
specifications (0.1 µVRMS 0.1 to 10Hz) . The offset
cancellation circuitry compensates for the “dark
signal” by adding an equal and opposite offset to the
input of the second stage, thus removing the original
offset from the output signal. This offset cancellation
circuitry allows optimized usage of the ADC full scale
and relaxes ADC resolution requirements.
The LMP91051 allows extra signal filtering (high
pass, low pass or band pass) through dedicated pins
A0 and A1, in order to remove out of band noise. The
user can program through the on board SPI interface.
Available in a small form factor 14 pin TSSOP
package, the LMP91051 operates from –40 to
+105°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
LMP91051
SNAS581B – MARCH 2012 – REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM
Optional
External
Filter
CMOUT
VDD
A0
A1
LMP91051
G1=250,42
IN1
G2=4,8,16,32
IN2
+
PGA2
-
+
PGA1
-
OUT
VIO
SPI
DAC
CMOUT
CSB
SPI
SCLK
SDIO
CM GEN
VREF
GND
Configurable AFE for NDIR
TYPICAL APPLICATION
VDD
VDD
A0
A1
VDD
VIO
AVCC
DVCC
IN1
Active
Thermopile
A/D
OUT
Reference
Thermopile
IN2
VIO
LMP91051
MSP430
VIO
CMOUT
CSB
GPIO
SCLK
CLK
SDIO
MOSI
AVSS/DVSS
GND
Typical NDIR Sensing Application Circuit
2
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CONNECTION DIAGRAM
SVA-30180650
PIN DESCRIPTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
IN1
1
Analog Input
Signal Input
IN2
2
Analog Input
Signal Input
CMOUT
3
Analog Output
Common Mode Voltage Output
A0
4
Analog Output
First Stage Output
A1
5
Analog Input
GND
6
Power
NC
7
—
No Connect
NC
8
—
No Connect
OUT
9
Analog Output
CSB
10
Digital Input
Chip Select, active low
SCLK
11
Digital Input
Interface Clock
SDIO
12
Digital Input / Output
Serial Data Input / Output
VIO
13
Power
Digital Input/Output Supply
VDD
14
Power
Positive Supply
Second Stage Input
Ground
Signal Output, reference to the same potential as CMOUT
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ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Human Body Model
ESD Tolerance (3)
1000
Charged Device Model
250
UNIT
V
VDD
Supply Voltage
–0.3
6.0
V
VIO
Digital I/O supply
–0.3
6.0
V
––0.3
VDD + 0.3
Voltage at Any Pin
Input Current at Any Pin
Storage Temperature Range
Junction Temperature
65
(4)
V
5
mA
150
°C
150
°C
For soldering specifications: see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
(1)
(2)
(3)
(4)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the
device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field- Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board.
OPERATING CHARACTERISTICS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
θJA
(1)
(2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltage
2.7
5.5
V
Junction Temperature Range (2)
–40
105
°C
140
°C/W
Package Thermal Resitance
Package 14 pin TSSOP
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the
device is functional and the device should not be operated beyond such conditions.
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board.
ELECTRICAL CHARACTERISTICS (1)
The following specifications apply for VDD = 3.3V, VIO = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
UNIT
Power Supply
VDD
Supply Voltage
2.7
3.3
5.5
VIO
Digital I/O supply
2.7
3.3
5.5
V
IDD
Supply Current
All analog block ON
3.1
3.6
4.2
mA
Power Down Supply Current
All analog block OFF
45
75
121
µA
Digital Supply Current
(1)
(2)
(3)
4
8
V
µA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
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ELECTRICAL CHARACTERISTICS(1) (continued)
The following specifications apply for VDD = 3.3V, VIO = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
UNIT
Offset Cancellation (Offset DAC)
Resolution
LSB
256
All gains
DNL
–1
Error
Output referred offset error, all gains
Offset adjust Range
Output referred, all gains
steps
33.8
mV
+2
±100
DAC settling time
mV
VDD –
0.2
0.2
LSB
480
V
µs
Programmable Gain Amplifier (PGA) 1st Stage, RL = 10 kΩ, CL = 15 pF
IBIAS
Bias Current
VINMAX
_HGM
Max input signal High gain mode
VINMAX
_LGM
Max input signal Low gain mode
VOS
5
Referenced to CMOUT voltage, it refers
to the maximum voltage at the IN pin
before clipping; It includes dark voltage
of the thermopile and signal voltage.
200
pA
±2
mV
±12
mV
Input Offset Voltage
–165
µV
G _HGM
Gain High gain mode
250
V/V
G_LGM
Gain Low gain mode
42
V/V
GE
Gain Error
2.5
%
VOUT
Output Voltage Range
PhDly
Phase Delay
1mV input step signal, HGM, Vout
measured at Vdd/2
6
µs
TCPhDly
Phase Delay variation with
Temperature
1mV input step signal, HGM, Vout
measured at Vdd/2,
416
ns
SSBW
Small Signal Bandwidth
Vin = 1mVpp, Gain = 250 V/V
Cin
Input Capacitance
Both HGM and LGM
VDD –
0.5
0.5
V
18
kHz
100
pF
1.65
V
0.82
V
Programmable Gain Amplifier (PGA) 2nd Stage, RS = 1kΩ, CL = 1µF
VINMAX
Max input signal
VINMIN
Min input signal
GAIN = 4 V/V
G
Gain
Programmable in 4 steps
GE
Gain Error
Any gain
4
32
2.5
%
VDD –
0.2
0.2
V/V
VOUT
Output Voltage Range
PhDly
Phase Delay
100mV input sine 35kHz signal, Gain =
8, VOUT measureed at 1.65V, RL = 10
kΩ
1
µs
TCPhDly
Phase Delay variation with
Temperature
250mV input step signal, Gain = 8, Vout
measured at Vdd/2
84
ns
SSBW
Small Signal Bandwidth
Gain = 32 V/V
360
kHz
Cin
Input Capacitance
5
pF
CLOAD,
OUT
OUT Pin Load Capacitance
Series RC
1
µF
RLOAD,
OUT
OUT Pin Load Resistance
Series RC
1
kΩ
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ELECTRICAL CHARACTERISTICS(1) (continued)
The following specifications apply for VDD = 3.3V, VIO = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
PARAMETER
MIN (2)
TEST CONDITIONS
TYP (3)
MAX (2)
UNIT
Combined Amplifier Chain Specification
en
G
Input-Referred Noise Density
Combination of both current and voltage
noise, with a 86kΩ source impedance at
5Hz, Gain = 7986
30
Input-Referred Integrated Noise
Combination of both current and voltage
noise, with a 86kΩ source impedance
0.1Hz to 10Hz, Gain = 7986
0.1
PGA1 GAIN = 42, PGA2 GAIN = 4
167
PGA1 GAIN = 42, PGA2 GAIN = 8
335
Gain
GE
Gain Error
TCCGE
PSRR
Gain Temp Coefficient (5)
PGA1 GAIN = 42, PGA2 GAIN = 16
669
PGA1 GAIN = 42, PGA2 GAIN = 3
1335
2 PGA1 GAIN = 250, PGA2 GAIN = 4
1002
PGA1 GAIN = 250, PGA2 GAIN = 8
2004
PGA1 GAIN = 250, PGA2 GAIN = 16
4003
PGA1 GAIN = 250, PGA2 GAIN = 32
7986
Any gain
5
Gain = 167 V/V, 335 V/V, 669 V/V, 1335
V/V
6
DC, 3.0V to 3.6V supply, gain = 1002V/V
PhDly
Phase Delay
1mV input step signal, Gain = 1002,
Vout measured at Vdd/2
TCPhDly
Phase Delay variation with
Temperature (6)
1mV input step signal, Gain=1002, Vout
measured at Vdd/2
TCVOS
Output Offset Voltage Temperature
Drift (5)
0.12 (4)
µVrms
V/V
%
ppm/°C
Gain = 1002 V/V, 2004 V/V, 4003 V/V,
7986V/V
Power Supply Rejection Ratio
nV√Hz
20
90
110
dB
9
µs
300
ns
Gain = 167 V/V
70
Gain = 335 V/V
100
Gain = 669 V/V
160
Gain = 1335 V/V
290
Gain = 1002 V/V
230
Gain = 2004 V/V
420
Gain = 4003 V/V
800
Gain = 7986V/V
1550
VDD = 3.3V
1.15
VDD = 5V
2.59
µV/°C
Common Mode Generator
VCM
Common Mode Voltage
VCM accuracy
CLOAD
(4)
(5)
(6)
6
CMOut Load Capacitance
V
2
%
10
nF
Guaranteed by design and characterization. Not tested on shipped production material.
TCCGE and TCVOS are calculated by taking the largest slope between –40°C and 25°C linear interpolation and 25°C and 85°C linear
interpolation.
TCPhDly is largest change in phase delay between –40°C and 25°C measurements and 25°C and 85°C measurements.
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SPI INTERFACE (1)
The following specifications apply for VDD = 3.3V, VIO = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = –40°C to
+85°C unless otherwise specified. All other limits apply to TA = TJ = +25°C.
PARAMETER
VIH
Logic Input High
VIL
Logic Input Low
VOH
Logic Output High
VOL
Logic Output Low
IIH/IIL
(1)
(2)
(3)
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
UNIT
0.7 × VDD
V
0.8
V
2.6
V
–100
–200
Input Digital Leakage Current
0.4
V
100
200
nA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
TIMING CHARACTERISTICS (1)
The following specifications apply for VDD = 3.3V, VIO = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = –40°C to
+85°C unless otherwise specified. All other limits apply to TA = TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
UNIT
10
MHz
tWU
Wake up time
fSCLK
Serial Clock Frequency
tPH
SCLK Pulse Width High
0.4/fSCLK
ns
tPL
SCLK Pulse Width Low
0.4/fSCLK
ns
tCSS
CSB Setup Time
10
ns
tCSH
CSB Hold Time
10
ns
tSU
SDI Setup Time prior to rise edge of
SCLK
10
tSH
SDI Hold Time prior to rise edge of
SCLK
10
tDOD1
SDO Disable Time after rise edge of
CSB
45
ns
tDOD2
SDO Disable Time after 16th rise
edge of SCLK
45
ns
tDOE
SDO Enable Time from the fall edge
of 8th SCLK
35
ns
tDOA
SDO Access Time after the fall edge
of SCLK
35
ns
tDOH
SDO hold time after the fall edge of
SCLK
tDOR
SDO Rise time
5
ns
tDOF
SDO Fall time
5
ns
(1)
(2)
(3)
1
ms
ns
ns
5
ns
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
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Timing Diagrams
SVA-30180612
Figure 1. SPI Timing Diagram
tPL
tPH
16th clock
SCLK
tH
tSU
SDI
Valid Data
Valid Data
SVA-30180613
Figure 2. SPI Set-up Hold Time
SCLK
tDOD2
SDIO
DB0
SVA-30180617
Figure 3. SDO Disable Time After 16th Rise Edge of SCLK
SCLK
tDOH
tDOA
SDIO
DB
DB
SVA-30180616
Figure 4. SDO Access Time (tDOA) and SDO Hold Time (tDOH) After the Fall Edge of SCLK
8
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SCLK
8
9
tDOE
SDIO
DB7
SVA-30180618
Figure 5. SDO Enable Time From the Fall Edge of 8th SCLK
CSB
tDOD1
SDIO
SVA-30180619
Figure 6. SDO Disable Time After Rise Edge of CSB
SDO
tDOR
tDOF
SVA-30180620
Figure 7. SDO Rise and Fall Times
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TYPICAL PERFORMANCE CHARACTERISTICS
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Gain = 335 V/V
vs
Temperature
336.0
168.3
335.9
168.2
335.8
GAIN (V/V)
GAIN (V/V)
168.4
Gain = 167 V/V
vs
Temperature
168.1
168.0
335.6
167.9
335.5
167.8
-50
335.7
-25
0
25
50
75
TEMPERATURE (°C)
335.4
-50
100
-25
0
25
50
75
TEMPERATURE (°C)
SVA-30180625
100
SVA-30180624
Gain = 669 V/V
vs
Temperature
Gain = 1002 V/V
vs
Temperature
672.5
1011
672.4
GAIN (V/V)
GAIN (V/V)
672.3
672.2
672.1
672.0
1010
1009
671.9
671.8
671.7
-50
1008
-25
0
25
50
75
TEMPERATURE (°C)
100
-50
-25
0
25
50
75
TEMPERATURE (°C)
SVA-30180623
SVA-30180627
Phase Delay
vs
Temperature
2014
9.3
2013
9.2
PHASE DELAY ( s)
GAIN (V/V)
Gain = 2004 V/V
vs
Temperature
2012
2011
2010
2009
9.1
9.0
8.9
8.8
8.7
2008
-50
8.6
-25
0
25
50
75
TEMPERATURE (°C)
100
-50
SVA-30180626
10
100
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-25
0
25
50
TEMPERATURE (°C)
75
100
SVA-30180622
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Output Offset
vs
Temperature
Common Mode Voltage
vs
Temperature
1.160
100
COMMON MODE VOLTAGE (V)
OUTPUT OFFSET (mV)
90
80
70
60
50
40
30
G = 1002 V/V
20
10
0
-50
-25
0
25
50
TEMPERATURE (°C)
75
1.158
1.156
1.154
1.152
1.150
-50
100
-25
0
25
50
75
TEMPERATURE (°C)
SVA-301806100
SVA-30180628
Input Bias Current
vs
Temperature
Supply Current
vs
Temperature
0
5
-1
4
IDD (mA)
IBIAS (pA)
100
-2
-3
3
2
G = 1002 V/V
1
-4
0
-5
-50
-25
0
25
50
TEMPERATURE (°C)
75
-50
100
-25
0
25
50
TEMPERATURE (°C)
75
SVA-30180643
100
SVA-30180642
Supply Current
vs
Supply Voltage
Power Down Supply Current
vs
Supply Voltage
120
4.5
4.0
110
3.5
100
IDD ( A)
IDD (mA)
3.0
2.5
2.0
80
1.5
PGA ALL ON
PGA2 ON
PGA1 ON
1.0
0.5
70
60
0.0
2.5
90
3.0
3.5
4.0
4.5
VDD (V)
5.0
2.5
5.5
SVA-30180631
3.0
3.5
4.0
4.5
VDD (V)
5.0
5.5
SVA-30180630
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Output Offset
vs
Supply Voltage
PGA1 Small Signal Bandwidth
60
65
G = 250 V/V
G = 42 V/V
50
G = 1002 V/V
40
GAIN (dB)
OUTPUT OFFSET (mV)
70
60
30
20
55
10
50
0
2.5
3.0
3.5
4.0
4.5
VDD (V)
5.0
5.5
1k
10k
100k
FREQUENCY (Hz)
1M
SVA-30180633
SVA-30180629
Power Supply Rejection Ratio
vs
Frequency
PGA2 Small Signal Bandwidth
40
120
G = 32 V/V
G = 16 V/V
G = 8 V/V
G = 4 V/V
PSRR (dB)
GAIN (dB)
30
G = 7986 V/V
G = 4003 V/V
G = 2004 V/V
G = 1002 V/V
110
20
100
90
80
10
70
0
60
10k
100k
1M
FREQUENCY (Hz)
10M
10
100
FREQUENCY (Hz)
1k
SVA-30180632
SVA-30180634
DAC DC Sweep
DAC DC Sweep
3.5
5.50
G = 1002 V/V
G = 2004 V/V
G = 4003 V/V
G = 7986 V/V
2.5
2.0
1.5
VDD = 3.3V
1.0
0.5
0.0
4.00
3.25
2.50
VDD = 5V
1.75
1.00
0.25
-0.5
-0.50
0
50
100 150 200
DAC CODE
250
300
0
SVA-30180639
12
G = 1002 V/V
G = 2004 V/V
G = 4003 V/V
G = 7986 V/V
4.75
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.0
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50
100 150 200
DAC CODE
250
300
SVA-30180640
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FUNCTIONAL DESCRIPTION
PROGRAMMABLE GAIN AMPLIFIER
The LMP91051 offers two programmable gain modes (low/high) with four programmable gain settings each. The
purpose of the gain mode is to enable thermopiles with larger dark voltage levels. All gain settings are accessible
through bits GAIN1 and GAIN2 [1:0]. The low gain mode has a range of 167 V/V to 1335 V/V while the high gain
mode has a range of 1002 V/V to 7986 V/V. The PGA is referenced to the internally generated VCM. Input
signal, referenced to this VCM voltage, should be within +/-2mV (see VINMAX_HGM specification) in high gain
mode. In the low gain mode the first stage will provide a gain of 42 V/V instead of 250 V/V, thus allowing a larger
maximum input signal up to +/-12mV (VINMAX_LGM).
Table 1. Gain Modes
BIT SYMBOL
GAIN
GAIN1
0: 250 (default)
1: 42
GAIN2 [1:0]
00: 4 (default)
01: 8
10: 16
11: 32
EXTERNAL FILTER
The LMP91051 offers two different measurement modes selectable through EXT_FILT bit. EXT_FILT bit is
present in the Device configuration register and is programmable through SPI.
Table 2. Measurement Modes
BIT SYMBOL
EXT_FILT
MEASUREMENT MODE
0: The signal from the thermopile is being processed by the internal PGAs,
without additional external decoupling or filtering (default).
1: The signal from the thermopile is being processed by the first internal PGA and
fed to the A0 pin. An external low pass, high pass or band pass filter can be
connected through pins A0, A1.
An external filter can be applied when EXT_FILT = 1. A typical band pass filter is shown in the picture below.
Resistor and capacitor can be connected to the CMOUT pin of the LMP91051 as shown. Discrete component
values have been added for reference.
10 PF
160 k:
A1
A0
6.8 nF
160 k:
CMOUT
SVA-30180607
Figure 8. Typical Bandpass Filter
OFFSET ADJUST
Procedure of the offset adjust is to first measure the “dark signal”, program the DAC to adjust, and then measure
in a second cycle the residual of the dark signal for further signal manipulation within the µC. The signal source
is expected to have an offset component (dark signal) larger than the actual signal. During the “dark phase”, the
time when no light is detected by the sensor, the µC can program LMP91051 internal DAC to compensate for a
measured offset. A low output offset voltage temperature drift (TCVOS) ensures system accuracy over
temperature.
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COMMON MODE GENERATION
As the sensor’s offset is bipolar, there is a need to supply a VCM to the sensor. This can be programmed as
1.15V or 2.59V (approximately mid rail of 3.3V or 5V supply). It is not recommended to use 2.59V VCM with 3.3V
supply.
SPI INTERFACE
An SPI interface is available in order to program the device parameters like PGA gain of two stages, enabling
external filter, enabling power for PGAs, offset adjust and common mode (VCM) voltage.
Interface Pins
The Serial Interface consists of SDIO (Serial Data Input / Output), SCLK (Serial Interface Clock) and CSB (Chip
Select Bar). The serial interface is write-only by default. Read operations are supported after enabling the SDIO
mode by programming the SDIO_MODE_EN register. This is discussed in detail later in the document.
CSB
Chip Select is a active-low signal. CSB needs to be asserted throughout a transaction. That is, CSB should not
pulse between the Instruction Byte and the Data Byte of a single transaction.
Note that CSB de-assertion always terminates an on-going transaction, if it is not already complete. Likewise,
CSB assertion will always bring the device into a state, ready for next transaction, regardless of the termination
status of a previous transaction.
CSB may be permanently tied low for a 2-wire SPI communication protocol.
SCLK
SCLK can idle High or Low for a write transaction. However, for a READ transaction, SCLK should idle high.
SCLK features a Schmitt-triggered input and although it has hysterisis, it is recommened to keep SCLK as clean
as possible to prevent glitches from inadvertently spoiling the SPI frame.
Communication Protocol
Communication on the SPI normally involves Write and Read transactions. Write transaction consists of single
Write Command Byte, followed by single Data byte. The following figure shows the SPI Interface Protocol for
write transaction.
CSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
COMMAND FIELD
DATA FIELD
MSB
c7
Wb=0
c6
c5
c4
Reserved to 0
c3
c2
c1
c0
d7
LSB
d6
d5
d4
Address (4 bits)
d3
d2
d1
d0
Write Data (8-bits)
SVA-30180609
Figure 9. SPI Interface Protocol
14
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For Read transactions, user first needs to write into a SDIO mode enable register for enabling the SPI read
mode. Once the device is enabled for Reading, the data is driven out on the SDIO pin during the Data field of the
Read Transaction. SDIO pin is designed as a bidirectional pin for this purpose. Figure 6 shows the Read
transaction. The sequence of commands that need to be issued by the SPI Master to enable SPI read mode is
illustrated in Figure 11.
SVA-30180601
Figure 10. Read Transaction
Sequence of transactions for unlocking SDIO_MODE
CSB
SDI
Write cmd
(sdio_mod
e_en reg)
Write data Write cmd Write
(0xFE first (sdio_mode data
byte of
_en reg) (0xED)
sdio_mode
_en reg)
Read cmd (to
read contents of
any register
specified by the
address bits)
SDO
Read data
Bus turnaround time = half cycle
Note:
1. Once the SDIO_mode is unlocked. The user can read as many registers as long as nothing
else is written to sdio_mode_en register to disturb the state of SDIO_mode
2. The separate signals SDI and SDO are given in the figure for the sake of understanding.
However, only one signal SDIO exists in the design
SVA-30180615
Figure 11. Enable SDIO Mode for reading SPI registers
Registers Organization
Configuring the device is achieved using ‘Write’ of the designated registers in the device. All the registers are
organized into individually addressable byte-long registers that have a unique address. The format of the Write/
Read instruction is as shown below.
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Table 3. Write / Read Instruction Format
BIT[6:4] (1)
BIT[7]
0 : Write Instruction
1 : Read Instruction
(1)
BIT[3:0]
Reserved to 0
Address
Specifying any value other than zero in Bit[6:4] is prohibited.
REGISTERS
This section describes the programmable registers and the associated programming sequence, if any, for the
device. The following table shows the summary listing of all the registers that are available to the user and their
power-up values.
ADDRESS (HEX) (1)
TYPE
POWER-UP/RESET
VALUE (HEX)
Device
Configuration
0x0
Read-Write
(Read allowed in SDIO Mode)
0x0
DAC
Configuration
0x1
Read-Write
(Read allowed in SDIO Mode)
0x80
SDIO Mode
Enable
0xF
Write-only
0x0
TITLE
(1)
Recommended values must be programmed where they are indicated in order to avoid unexpected results. Avoid writing to addresses
not mentioned in the document; this could cause unexpected results.
Device Configuration – Device Configuration Register (Address 0x0)
BIT
BIT SYMBOL
DESCRIPTION
0: IN1 (default)
1: IN2
7
INP_SEL
[6:5]
EN
4
EXT_FILT
3
CMN_MODE
[2:1]
GAIN2
00: 4 (default)
01: 8
10: 16
11: 32
0
GAIN1
0: 250 (default)
1: 42
00: PGA1 OFF PGA2 OFF (default)
01: PGA1 OFF, PGA2 ON
10: PGA1 ON, PGA2 OFF
11: PGA1 ON, PGA2 ON
0: PGA1 to PGA2 direct (default)
1: PGA1 to PGA2 via external filter
0 : 1.15V (default)
1 : 2.59V
DAC Configuration – DAC Configuration Register (Address 0x1)
The output DC level will shift according to the formula Vout_shift = –33.8mV * (NDAC – 128).
BIT
BIT SYMBOL
[7:0]
NDAC
DESCRIPTION
128 (0×80): Vout_shift = –33.8mV * (128 – 128) = 0mV (default)
SDIO Mode – SDIO Mode Enable Register (Address 0xf)
Write-only
BIT
[7:0]
16
BIT SYMBOL
SDIO_MODE_EN
DESCRIPTION
To enter SDIO Mode, write the successive sequence 0×FE and 0×ED. Write
anything other than this sequence to get out of mode.
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APPLICATION INFORMATION
NDIR Gas Sensing Principle
NDIR technology, a type of IR spectroscopy, is based on the principle that gas molecules absorb IR light and
absorption of a certain gas occurs at a specific wavelength. Typically, a thermopile with a built-in filter is used to
detect the amount of a specific gas. For instance, since CO2 has a strong absorbance at a wavelength of 4.26
µm, a band-pass filter is used to remove all light outside of this wavelength. Figure below shows the basic NDIR
gas sensor working principle.
Figure 12. NDIR Gas Sensor Principle
Gas molecules will absorb radiation energy from the lamp emission. Absorption follows the Lambert-Beer law:
I = I0 * e-kcl
Where I is the transmitted IR intensity at the thermopile detector side, I0 is the initial intensity at the IR source, k
is the gas specific absorption coefficient of the target gas, c is the gas concentration, and l is the length of the
absorption path from light source to thermopile detector.
The thermopile is used to detect the light intensity change. Its output voltage will follow:
V = n * Δα * (Tbody - Tamb)
Where Δα is the difference of the Seebeck coefficients of the thermopile materials and n is the number of
thermocouples in thermopile detector. Tbody is the blackbody temperature that is emitting thermal radiation (i.e.
the IR lamp), and Tamb is the temperature of the surrounding ambient.
Inside the gas chamber, the IR lamp radiation energy could be regarded as ideal black body radiation. The
radiation emitted by a blackbody as a result of the temperature difference between the blackbody and ambient is
known as thermal radiation. According to Stefan-Boltzmann law, thermal radiation per unit area is expressed with
the following equation:
RT = σ * (Tbody4 - Tamb4)
where σ = 5.67 * 10-8 W/(m2 *K4) is the Stefan-Boltzmann constant.
Assuming no loss in light intensity while traveling through the chamber, then RT = I. After rearranging the
equations above the equation for thermopile output voltage becomes:
V = n * Δα * [ I0 * e-kcl ] / [σ * (Tbody2 + Tamb2) * (Tbody + Tamb) ]
If we examine this equation it makes sense that the thermopile output voltage will be affected by the ambient
temperature and the IR lamp intensity uncertainty with a complex relationship. In order to maintain better
accuracy of the system, special consideration should be taken in the design implementation. We can see that
temperature compensation is an effective way to maintain system accuracy. To accomplish this thermistors are
commonly integrated into the thermopile sensor and their resistance changes depending on the surrounding
ambient temperature. For better measurement accuracy, having a stable constant voltage to excite the thermistor
is a good choice.
Traditional Discrete Op Amp Signal Conditioning
Traditionally discrete op amps have been employed for the gain stage of NDIR systems. AC coupling is required
in order to eliminate the signal chain offset. To handle a two channel system one could use a quad op amp
configured in a dual channel 2 stage front end. Active filtering is built into the signal path.
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C2
C4
R3
VREF
R2
R6
VR EF
R5
U1C
U1D
C3
V+
V-
Thermopile Active
Active Signal
V+
V-
R1
R4
C1
VREF
VR EF
C6
C8
R9
VREF
R8
R12
VR EF
R11
VDD
U1B
U1A
V+
V-
C7
V+
V-
Thermopile Reference
R7
Reference Si gnal
R10
C5
GND
VREF
VR EF
Figure 13. Discrete Op Amp Based System
LMP91051 Sensor AFE for NDIR Gas Sensing
An integrated analog front-end (AFE) can save design time and complexity by incorporating the features of a
discrete op amp solution into one chip. The LMP91051 AFE contains a two channel PGA which allows easy
interface to a two channel NDIR sensor. By cancelling out errors due to light source deviation optimum accuracy
is obtained in a two channel system. This deviation results in long-term drift, which occurs over large periods of
time. Hence, the requirement to simultaneously sample both the reference and active channel simultaneously is
not required. You can use the input multiplexer (MUX) to switch between the two channels, reducing system cost
and complexity, while maintaining accuracy.
The LMP91051 also has fully programmable gain and offset adjustment. This helps ensure that the small
thermopile output (100’s µV) is matched to the dynamic range of the sampling Analog to Digital converter (A/D)
and improves system resolution. The LMP91051 also provides a common mode bias which level-shifts the
thermopile sensor signal away from the negative rail, allowing for accurate sensing in the presence of sensor
offset voltages.
18
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VDD
A0
A1
LMP91051
G1=250,42
IN1
G2=4,8,16,32
IN2
+
PGA2
-
+
PGA1
-
OUT
VIO
DAC
SPI
CMOUT
CSB
SPI
SCLK
SDIO
CM GEN
VREF
GND
Figure 14. LMP91051 Sensor AFE for NDIR Sensing
LMP91051 Gas Detection System
VDD
VDD
R4
U3
R2
V+
TEMPERATURE
V-
C2
VDD
GND
VDD
U4
Lamp +
Lamp -
Q1
NC
GND
1
Det ec tor
2
Referenc e
GND
LAMP DRIVE
U1
Thermi s tor
C4
4
5
GND
6
7
C3
14
U2
VIO
3
R3
VDD
IN2
C5
IRC-AT NDIR S ens or
COMMON
IN1
CMOUT
SDIO
A0
SCLK
A1
CSB
GND
OUT
NC
NC
13
AVCC
12
11
CLK
10
9
GPIO1
R1
ADC1
TEM PER ATURE
8
C1
COMMON
GND
LMP91051
LAMP DRIVE
GND
GND
DV CC
MOS I
ADC2
A DC3
GPIO2
GND
MSP430
GND
Figure 15. LMP91051 CO2 Gas Detection System
The NDIR sensor used in the proposed system is a Alphasense IRC-AT. The sensor is composed of an IR lamp,
two thermopile channels, and a thermistor which is used for temperature calibration. To save power and to avoid
overheating the device the lamp source is modulated typically with a 50% duty cycle with a frequency of 1 to
3Hz. The Detector (Active) and Reference channel output are connected directly to the inputs of the LMP91051.
Filter capacitors are connected from each input to the common mode reference, CMOUT, to provide low pass
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filtering. LMP91051 external filtering option is disabled and pins A0 and A1 are shorted internally in the chip. No
high pass filtering (AC coupling) is required because the internal offset DAC is used to cancel offset error in the
signal chain. This facilitates faster measurements over the traditional AC coupled system which will be discussed
further later in this application note. The NDIR sensor has an internal thermistor which is connected to a resistor
bridge then buffered by an amplifier.
The MSP430 microcontroller programs the LMP91051 via SPI. The microcontroller utilizes an internal 12 bit
muxed A/D to sample the LMP91051 output, buffered thermistor output, and system common mode. The entire
system can be powered off of a single supply of 3V.
Gas Detection Method and Settings
In a 2 channel NDIR system the integrated IR lamp is pulsed (typical 1 to 3Hz) with a 50% duty cycle resulting in
small 100’s uV RC waveforms seen on both the output of the active and reference channel. To improve
measurement accuracy these signals are amplified and the peak to peak waveform voltage of both the active
channel and reference channel are compared. In a DC coupled single supply system, active DC offset
adjustment is required in order to ensure the output of the gain stage doesn’t saturate and to remove signal chain
offset errors.
In a Muxed 2 channel system toggling between channels is done at an increased rate (i.e 100Hz) in order to
reliably reconstruct both channels. To ensure accurate sampling, multiple samples should be taken on each
channel prior to switching channels. Preferably sampling is synced to the lamp pulses to ensure data is being
capture at the expected time relative to the lamp switching and the same sample within one lamp cycle can be
looked at over many lamp cycles to determine noise performance. Figure below provides a visual explanation of
the proposed gas detection method.
Lamp Frequency 2Hz
Active
Active
+
PGA2
Gain
-
Reference
100Hz
Reference
Figure 16. Example Gas Detection Method
A system was constructed with the following settings. Image below shows actual system RC waveform.
Lamp Pulse Frequency: 2 Hz
System Gain: 2000 V/V
System Offset: Apx. -700mV
Input Channel Mux Toggle Frequency: 100Hz
Number of Ch. Samples per Ch. Toggle: 10
ADC Sampling Rate: 1ksps
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Figure 17. System Waveform
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMP91051MT/NOPB
ACTIVE
TSSOP
PW
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
LMP910
51MT
LMP91051MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
LMP910
51MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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