LMP92066PWPR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 LMP92066 Dual Temperature-Controlled DAC with Integrated EEPROM and Output ON/OFF Control 1 Features 3 Description • The LMP92066 is a highly integrated temperaturecontrolled dual DAC. Both DACs can be programmed by two independent, user-defined, temperature-tovoltage transfer functions stored in the internal EEPROM, allowing any temperature effects to be corrected without additional external circuitry. Once powered up, the device operates autonomously, without intervention from the system controller, to provide a complete solution for setting and compensating bias voltages and currents in control applications. 1 • • • • • • • • Internal 12-Bit Temperature Sensor – Accuracy (–40°C to 120°C), ±3.2°C (maximum) Two Independent Transfer Functions Stored in EEPROM Dual-Analog Output – Two 12-Bit DACs – Output Range 0 V to 5 V or 0 V to –5 V – High-Capacitive Load Tolerant, up to 10 µF – Post-Calibration Accuracy ±2.4 mV (typical) Output On/Off Control Switching Time 50 ns (typical) – Switching Time 50 ns (typical) – RDSON 5 Ω (maximum) I2C Interface: Standard and Fast – Nine Selectable Slave Addresses – TIMEOUT Function VDD Supply Range 4.75 V to 5.25 V VIO Range 1.65 V to 3.6 V Specified Temperature Range –25°C to 120°C Operating Temperature Range –40°C to 125°C 2 Applications • • • GaN or LDMOS PA Bias Controller Sensor Temperature Compensation Timing Circuit Temperature Compensation The LMP92066 has two analog outputs that support two output ranges: zero to plus five volts and zero to minus five volts. Each output can be switched to the load individually through the use of the dedicated control pin. The output switching is designed for rapid response, making the device suitable for the RF Power Amplifier biasing applications. The EEPROM is verified for 100 write operations, enabling repeated field updates. The EEPROM programming is completed upon the user-issued I2C command. The LMP92066’s digital ports interface to a variety of system controllers, as the dedicated VIO pin sets the digital I/O levels. The device is available in the thermally enhanced PowerPAD™ package, enabling precise PCB temperature measurement. Device Information PART NUMBER LMP92066 PACKAGE BODY SIZE HTSSOP (16) 5.00 mm x 4.40 mm 4 Simplified Schematic 3.3V 5V Residual Error After One Point Calibration VIO 35 VDD VDDB FETDRV1 Gate Bias 1 MEAN = 0.72 mV STDEV = 1.71 mV PA: LDMOS 30 10µ SCL LMP92066 DRVEN1 DRVEN0 FETDRV0 PA: LDMOS 15 10 DAC0 10 8 6 4 2 0 0 5 ±2 10µ ±4 GNDD GNDA VSSB ±6 A0 20 ±8 A1 Gate Bias 0 25 ±10 µC Occurrences (%) DAC1 SDA REAOPC (mV) C009 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 1 2 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics........................................... 6 Timing Requirements ................................................ 8 Output Switching Characteristics .............................. 8 Typical Characteristics ............................................ 10 Detailed Description ............................................ 14 8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Features Description ............................................... Device Functional Modes........................................ 14 14 15 28 8.5 Programming........................................................... 32 8.6 Register Map........................................................... 39 9 Application and Implementation ........................ 43 9.1 9.2 9.3 9.4 Application Information............................................ Typical Applications ................................................ Do's and Don'ts ....................................................... Initialization Setup ................................................... 43 43 51 52 10 Power Supply Recommendations ..................... 54 10.1 VDD Supply Sourcing ........................................... 54 10.2 IVDD During EEPROM BURN ................................ 54 10.3 IVDD During EEPROM TRANSFER....................... 54 11 Layout................................................................... 55 11.1 Layout Guidelines ................................................. 55 11.2 Layout Example .................................................... 56 12 Device and Documentation Support ................. 57 12.1 12.2 12.3 12.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 57 57 57 57 13 Mechanical, Packaging, and Orderable Information ........................................................... 57 5 Revision History Changes from Revision A (April 2015) to Revision B Page • Added new footnote. .............................................................................................................................................................. 7 • Added VDD Supply Sourcing section. ................................................................................................................................. 54 Changes from Original (March 2014) to Revision A Page • Changed header row of Device Information table; revised "terminal" to "pin" throughout document, changed Handling Ratings to ESD Ratings table; took out "+" from positive values; italicize section cross references; add titles for tables 3, 4, 5, and 6 .................................................................................................................................................. 1 • Added "Ω" after "k" in EC table ............................................................................................................................................. 6 • Added "Ω" after "k" in Output Switching table ....................................................................................................................... 8 • Added "NOTE" to beginning of Applications and Implementations ...................................................................................... 43 • Changed title from Application Performance Plots to Application Curves; deleted reference to Figure 43 in first sentence of first Application Curves section......................................................................................................................... 47 • Added change "5 mA" to "50 mA" ........................................................................................................................................ 54 2 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 6 Pin Configuration and Functions PWP Package 16-Pin HTSSOP Top View GNDD 1 16 VDD DRVEN1 2 15 VDDB DRVEN0 3 14 DAC1 VIO 4 13 FETDRV1 DAP SDA 5 12 GNDA SCL 6 11 FETDRV0 A1 7 10 DAC0 A0 8 9 VSSB Pin Functions PIN NUMBER NAME TYPE (1) DESCRIPTION ESD STRUCTURES VIO 1 GNDD G Lower power rail of the digital I/O 2:3 DRVEN[1:0] I Asynchronous control of the Changeover Switches Digital I/O power supply rail GNDA 4 VIO I 5 SDA I/O 6 SCL I I2C bi-directional data line I2C clock input GNDA VIO 7:8 A[1:0] I I2C slave address selector GNDA GNDA 9 VSSB P Output drive lower supply rail 10, 14 DAC0 DAC1 O DAC0 output 11, 13 FETDRV0 FETDRV1 O Gate drive of the external FET device VDDB VSSB (1) G = Ground; I = Input; O = Output; P = Power Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 3 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Pin Functions (continued) PIN NUMBER NAME TYPE (1) DESCRIPTION ESD STRUCTURES VDD 12 GNDA G Analog block lower rail Merril Clamp GNDA VDD 15 VDDB P Output drive upper supply rail GNDA VDD 16 VDD P Analog block upper rail Merril Clamp GNDA --- 4 DAP G Die Attach Pad. For best thermal, and noise performance it should be soldered to the local system ground pad. Submit Documentation Feedback GNDA Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX –0.3 5.5 –0.3 5.5 –0.3 5.5 VSSB –5.5 0.3 GNDD –0.3 0.3 VDDB to VSSB –0.3 5.5 Any other pins to GNDA –0.3 5.5 VDD VDDB VIO Supply voltage with respect to GNDA DAC output current 10 Current at all other pins 5 Storage temperature, Tstg (1) –65 UNIT V V mA 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX Operational temperature –40 125 Specification temperature –25 120 8 12 DAC output load capacitance VDD Supply voltage range (VDD) 4.75 5.25 VIO Digital I/O supply voltage 1.65 3.3 VDDB–VSSB LDMOS mode VSSB = GNDA 5 GaN mode VSSB = –5 V 5 UNIT °C µF V 7.4 Thermal Information THERMAL METRIC (1) PWP (HTSSOP) 16 PINS RθJA Junction-to-ambient thermal resistance 38.2 RθJC(top) Junction-to-case (top) thermal resistance 21.3 RθJB Junction-to-board thermal resistance 15.1 ψJT Junction-to-top characterization parameter 0.5 ψJB Junction-to-board characterization parameter 14.9 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 5 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 7.5 Electrical Characteristics Unless otherwise noted: VDD = 5 V ±5%, VIO = 1.8 V to 3.3 V, TA = 25°C. VDDB = 5 V ±5%, VSSB = GNDA, VDACx output range 0 V to 5 V; or VDDB = GNDA, VSSB = –5 V ±5%, VDACx output range 0 V to –5V. DAC input code range 48 to 4047. VDACX load CL = 10 µF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG SIGNAL PATH CHARACTERISTICS (DAC, Buffer Amplifier, Internal Reference) Resolution 12 –25°C < TA < 120°C Monotonic 12 12 DNL Differential non-linearity RL = 100 kΩ, –25°C < TA < 120°C –0.99 1 INL Integral non-linearity RL = 100 kΩ, –25°C < TA < 120°C −1.93 2.78 –14 14 LDMOS mode, RL = 100 kΩ, –25°C < TA < 120°C OE Offset error (1) LDMOS mode, RL = 100 kΩ ±1 GaN mode, RL = 100 kΩ, –25°C < TA < 120°C OETC Offset error temperature coefficient (1) (2) RL = 100 kΩ, –25°C < TA < 120°C GE Gain error (1) RL = 100 kΩ, –25°C < TA < 120°C GETC Gain error temperature coefficient (1) (2) Residual error after one point calibration (1) (2) (3) (4) Zero code output (VDACx – VSSB) FSO Full-scale output at code 4095 (VDDB – VDACx) IO Continuous output current per channel allowed (5) CL Load capacitance (5) mV 16.5 43 μV/°C –0.72 0.74 %FS 20 ppm/°C –13.3 BASEx = 1638 (VDACX = 2 V at 24°C) BASEx = 819 (VDACX = 1 V at 24°C) –25°C < TA < 120°C 13.3 ±2.4 –11.3 BASEx = 819 (VDACX = 1 V at 24°C) ZCO mV 11.3 ±2.1 LDMOS mode, RL = 100 kΩ 0 LDMOS mode, IOUT = 10 mA mV 200 LDMOS mode, RL = 100 kΩ 10 LDMOS mode, IOUT = –10 mA mV 150 TA = 125°C 10 RL = 2 kΩ or ∞, –25°C < TA < 120°C 12 RL = 2 kΩ or ∞ DAC output resistance DACCODEx = 2048 DAC settling time CL = 10 µF LSB –16.5 RL = 100 kΩ, –25°C < TA < 120°C BASEx = 1638 (VDACX = 2 V at 24°C) –25°C < TA < 120°C REAOPC Bits 10 mA µF 3 Ω 250 µs OUTPUT SWITCH DC CHARACTERISTICS RDRV On Resistance of the switch between DACx and FETDRVx RG On Resistance of the switch between FETDRVx and VSSB –25°C < TA < 120°C 6 Ω 11 TEMPERATURE SENSOR CHARACTERISTICS Resolution TE Temperature sensor error (2) 0.0625 TA = –40°C to 120°C Conversion time (1) (2) (3) (4) (5) 6 –3.2 °C/lsb 3.2 25 °C ms The package mechanical stress-induced parameter shift may cause the parts to manifest behavior beyond the specified limits. Mechanical stresses may also arise as a result of the PCB manufacturing process. Device specification is verified by characterization and is not tested in production. The specification is a calculated worst-case value based on the OE, OETC, GE, and GETC limits. The outcome of the REAOPC characterization of the PCB mounted devices is shown in Figure 4, Figure 5, and Figure 6 of the Typical Characteristics. The 97, randomly selected, devices from 3 diffusion lots were installed on the 4-layer RO4003 Laminate using Convection Reflow. The Look-Up-Table was set for maximum gain; for example, all DELx = 0xFF. While powered up, the devices were subjected to 3 thermal cycles, from –40°C to 125°C, during which their REAOPC was recorded. Parameter based on the process data and circuit simulation. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Electrical Characteristics (continued) Unless otherwise noted: VDD = 5 V ±5%, VIO = 1.8 V to 3.3 V, TA = 25°C. VDDB = 5 V ±5%, VSSB = GNDA, VDACx output range 0 V to 5 V; or VDDB = GNDA, VSSB = –5 V ±5%, VDACx output range 0 V to –5V. DAC input code range 48 to 4047. VDACX load CL = 10 µF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EEPROM Maximum EEPROM write cycles 100 DIGITAL INPUT CHARACTERISTICS (DRVEN0, DRVEN1, SDA, and SCL) VIH Input high voltage –25°C < TA < 120°C VIL Input low voltage –25°C < TA < 120°C 0.7 × VIO 0.3 × VIO 0.2 × VIO Hysteresis CiND V Input capacitance 5 pF DIGITAL INPUT CHARACTERISTICS (A0, A1) 0.7 × VIO VIH Input high voltage –25°C < TA < 120°C VIL Input low voltage –25°C < TA < 120°C RUP Internal pullup resistance 17 RDN Internal pulldown resistance 17 0.3 × VIO Max external capacitance (5) V kΩ 30 pF DIGITAL OUTPUT CHARACTERISTICS (SDA) VOL Output low voltage ILEAK Open-drain output leakage current with output high (5) COUT Output capacitance IOUT = 4 mA, –25°C < TA < 120°C 0.4 IOUT = 4 mA 0.16 Current from the supply rail through the pullup resistor into the drain of the opendrain output device, –25°C < TA < 120°C ±1 4 V μA pF SUPPLY CURRENT SPECIFICATIONS Normal operation (6), (7) –25°C < TA < 120°C IDD 2.6 While executing EEPROM BURN (8) 4 While transferring EEPROM content to operating memory (9) 9 I2C inactive, –25°C < TA < 120°C IVIO mA 3 I2C in fast mode, –25°C < TA < 120°C 3.1 IVDDB LDMOS mode, RL = ∞, –25°C < TA < 120°C 1.5 IVSSB GaN mode, RL = ∞, –25°C < TA < 120°C PWR (Conv) (6) (7) (8) (9) Power consumption, conversion mode All output pins RL = ∞ –1.4 20 µA mA mW The normal operation current through the VDD excludes the current supplied to the external load, and excludes the current required by the EPPROM BURNS and TRANSFERS. The power supply must be capable of sourcing a minimum of 50mA in order to avoid the continuous activation of the LMP92066’s power-on-reset (POR) circuit. During the EEPROM BURN command execution the device activates internal systems that are not active during the Normal operation. This causes a momentary increase in supply current through the VDD pin. The duration of this temporary surge in supply current is typically 125 ms. During the data transfer from the EEPROM to the Operating memory there will be a momentary surge in supply current through the VDD pin. The duration of this surge is typically 200 µs. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 7 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 7.6 Timing Requirements Unless otherwise noted: VDD = 5 V ±5%, VIO = 1.8 V to 3.3 V. VDDB = 5 V ±5%, VSSB = GNDA; or VDDB = GNDA, VSSB = –5V ±5%. PARAMETER TEST CONDITIONS MIN I2C clock frequency 10 tLOW Clock low time 1.3 tHIGH Clock high time MAX UNIT 400 kHz 0.6 After this period, the first clock pulse is generated tHD-STA Hold time repeated START condition tSU;STA Setup time for a repeated START condition tHD;DAT Data hold time (Note x and y) tSU;DAT Data setup time tf SDA fall time tSU;STO Setup time for STOP condition 0.6 tBUF Bus free time between a STOP and START condition 1.3 Cb SDA capacitive load tSP Pulse width of spikes that must be suppressed by the input filter µs 0.6 0.6 0 900 100 ns IL ≤ 3 mA and CL ≤ 400 pF 250 SCL and SDA timeout µs 25 400 pF 50 ns 35 ms 7.7 Output Switching Characteristics Unless otherwise noted: VDD = 5 V ±5%, VIO = 1.8 V to 3.3 V. VDDB = 5 V ±5%, VSSB = GNDA; or VDDB = GNDA, VSSB = –5V ±5%. PARAMETER TEST CONDITIONS MIN TYP tON On time tOFF Off time tBBM Break-before-make time 15 CFETDRV FETDRV output capacitance 10 MAX UNIT 50 DACCODEx = 4095, RL = 100 kΩ 50 ns pF tVD;DAT, tVD;ACK SDA 70% tLOW tf tr SCL tBUF tHD;STA tf 30% tSP 70% 30% tSU;STA tHD;STA tHD;DAT START tHIGH tSU;STO tSU;DAT REPEATED START STOP START Figure 1. I2C Timing 8 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 VIO DRVENx 50% 50% GNDD VDACx FETDRVx 90% HiZ 90% HiZ VSSB tBBM tON tBBM tOFF Figure 2. Switching Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 9 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 7.8 Typical Characteristics Unless otherwise stated the plot data was collected under these conditions: VDD = 5 V, VDDB = 5 V, VSSB = GNDA, VIO = 3.3 V, Temperature = 24°C, RL = 100 kΩ. 2.1 35 MEAN = 0.76 mV STDEV = 1.43 mV 1.8 30 1.5 Occurrences (%) 1.2 0.9 TE (ƒC) 0.6 0.3 0.0 ±0.3 25 20 15 10 ±0.6 ±40 ±20 0 20 40 60 80 100 120 Temperature (ƒC) C008 PCB Mounted 3 Cycles: –40°C to 125°C Figure 3. Temperature Sensor Error Figure 4. REAOPC 35 REAOPC (mV) REAOPC (mV) C009 BASE = 1638 97 devices C010 PCB Mounted 3 Cycles: –40°C to 125°C BASE = 3277 97 devices Figure 5. REAOPC PCB Mounted 3 Cycles: –40°C to 125°C Figure 6. REAOPC 0.5 1.0 0.4 0.8 0.3 0.6 0.2 0.4 0.1 0.2 INL (lsb) DNL (lsb) 10 8 2 0 10 8 6 4 2 0 ±2 0 ±4 0 ±6 5 ±8 5 ±2 10 ±4 10 15 ±6 15 20 ±8 20 25 ±10 Occurrences (%) 25 ±10 MEAN = 0.66 mV STDEV = 2.42 mV 30 6 MEAN = 0.72 mV STDEV = 1.71 mV 30 4 35 0.0 ±0.1 0.0 ±0.2 ±0.2 ±0.4 ±0.3 ±0.6 ±0.4 ±0.8 ±0.5 ±1.0 0 512 1024 1536 2048 2560 Input Code (dec) 3072 3584 4096 0 C003 Figure 7. DAC DNL 10 10 8 6 4 2 0 REAOPC (mV) C001 BASE = 819 97 devices Occurrences (%) ±2 ±4 0 ±6 ±1.5 ±10 ±1.2 ±8 5 Mean Error 1 ± 1 ±0.9 512 1024 1536 2048 2560 Input Code (dec) 3072 3584 4096 C003 Figure 8. DAC INL Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Typical Characteristics (continued) 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (lsb) 0.0 ±0.2 ±0.4 0.0 ±0.2 ±0.4 ±0.6 ±0.6 MAX MIN 100 120 140 ±60 25 60 Occurrences (%) 70 20 15 10 10 8 6 4 2 0 80 100 120 140 C005 20 0 ±2 60 30 0 ±4 40 40 10 ±6 20 50 5 ±8 0 Figure 10. DAC MIN/MAX INL vs Temperature 30 ±10 ±20 Temperature (ƒC) Figure 9. DAC MIN/MAX DNL vs Temperature Occurrences (%) ±40 C004 OE (mV) GE (%) C006 C007 TEMP = –40°C to 120°C TEMP = –40°C to 120°C Figure 11. DAC Offset Error Figure 12. DAC Gain Error VDACx VDACx VSCL VSCL Time (100 µs/DIV) Time (100 µs/DIV) C012 C011 DAC OVERRIDE MODE CL = 10 µF 1.0 80 0.8 60 0.6 40 0.4 20 Temperature (ƒC) 0.2 0 ±0.4 ±20 ±0.6 ±40 ±1.0 ±0.8 ±60 MAX MIN ±0.8 0.0 ±1.0 ±0.2 ±0.8 ±1.0 DNL (lsb) Unless otherwise stated the plot data was collected under these conditions: VDD = 5 V, VDDB = 5 V, VSSB = GNDA, VIO = 3.3 V, Temperature = 24°C, RL = 100 kΩ. I2C command triggers DAC step Step size: 1/4 to 3/4 FS DAC OVERRIDE MODE CL = 10 pF Figure 13. DAC Step Response I2C command triggers DAC step Step size: 1/4 to 3/4 FS Figure 14. DAC Step Response Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 11 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) Unless otherwise stated the plot data was collected under these conditions: VDD = 5 V, VDDB = 5 V, VSSB = GNDA, VIO = 3.3 V, Temperature = 24°C, RL = 100 kΩ. VDACx VDACx VSCL VSCL Time (100 µs/DIV) Time (100 µs/DIV) C013 I2C command triggers DAC step Step size: 3/4 to 1/4 FS DAC OVERRIDE MODE CL = 10 µF C014 Figure 15. DAC Step Response Figure 16. DAC Step Response 5 5 4 4 3 3 RDRV ( ) RDRV ( ) I2C command triggers DAC step Step size: 3/4 to 1/4 FS DAC OVERRIDE MODE CL = 10 pF 2 2 1 1 Vdacx= VDACx 1.38 V VDACx 3.23 V Vdacx= VDACx 4.46 V Vdacx= 0 0 0 1 2 3 4 5 VDACx (V) ±40 ±20 0 20 40 60 80 100 120 Temperature (ƒC) C015 Figure 17. RDRV Resistance vs DAC Output Level C016 Figure 18. RDRV vs Temperature 90 60 80 50 Occurrences (%) 70 tON (ns) 40 30 20 60 50 40 30 20 10 Temperature (ƒC) C017 45 0 44 120 43 100 42 80 41 60 40 40 39 20 38 0 37 ±20 36 ±40 35 10 0 tON (ns) C018 Figure 19. Output Switch ON Time vs Temperature 12 Submit Documentation Feedback Figure 20. Output Switch ON Time Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Typical Characteristics (continued) Unless otherwise stated the plot data was collected under these conditions: VDD = 5 V, VDDB = 5 V, VSSB = GNDA, VIO = 3.3 V, Temperature = 24°C, RL = 100 kΩ. 70 Occurrences (%) 60 50 40 30 20 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 0 9.0 10 RG ( ) C019 Figure 21. Ground Switch Resistance When Closed Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 13 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 8 Detailed Description 8.1 Overview The LMP92066 is a dual temperature-dependent bias generator whose temperature-to-voltage transfer functions are user defined. The device contains a digital temperature sensor that addresses two independently programmable Look-Up-Tables (LUTs). The outputs of LUTs are sent on to their respective 12-bit DACs to produce two independent output voltages. For added flexibility the device can be configured to provide bias potential above or below GNDA. In applications requiring rapid ON/OFF switching of the bias voltage, the LMP92066 provides asynchronous control over its outputs. Dedicated digital input pins control analog output switching. All aspects of the device functionality are controlled through internal registers. These registers, and the LUTs, are accessible through the I2C-compatible interface. The LMP92066 can operate autonomously of the system controller, once LUT coefficients have been committed to its non-volatile memory, EEPROM. Upon power up the EEPROM content is automatically transferred to the operating memory, and the device begins to produce required bias voltage. 8.2 Functional Block Diagram VIO A[1:0] SCL SDA VDD VDDB I2C Interface & Controller DAC1 LUT1 Temp. Sensor FETDRV1 DAC1 DRVEN1 EPROM VSSB DAC0 LUT0 FETDRV0 DAC0 DRVEN[1:0] DRVEN0 VSSB GNDD 14 GNDA VSSB Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 8.3 Features Description 8.3.1 Temperature Sensor The onboard digital temperature sensor produces 12-bit, twos complement output, where the LSB represents +0.0625°C, and MSB represents –128°C. The output of the temperature sensor is stored in the TEMPM and TEMPL registers. These registers are updated automatically once the temperature sensor completes a new conversion, approximately every 25 ms. The temperature sensor begins operation immediately after the supply voltage at VDD has reached its minimum operating level. Initially, right after power up, TEMPM and TEMPL registers contain 0s. The first measurement result is loaded into TEMPM and TEMPL registers 25 ms after power up. Table 1. Temperature Sensor Output TEMPERATURE SENSOR OUTPUT {TEMPM[3:0], TEMPL[7:0]} TEMPERATURE (°C) 100000000000 –128.0000 111001000000 –28.0000 111111111111 –0.0625 000000000001 0.0625 000110000000 24.0000 011111111111 127.9375 NOTE The maximum output of the temperature sensor stored in the TEMPM and TEMPL registers is 127.9375°C. 8.3.2 Look-Up-Table (LUT) and Arithmetic-Logic Unit (ALU) The LUT is used to create an arbitrary transfer function which maps the temperature to the analog output of the device. In concept, the temperature readout is used as a pointer to a table of discrete values that are representative of the samples of the desired temperature-dependent function. In order to minimize the storage requirements, the LMP92066 LUTs are indexed in 4°C increments. Also, the stored values are only the increments, or first derivatives (Δs) of the modeled transfer function. The internal ALU reconstructs the original transfer function by integrating the coefficients stored in the LUTs. The errors due to the coarseness of the temperature quantization are significantly reduced through the use of linear interpolation, which is also implemented in the ALU. Consider the example shown in Figure 22. The target output vs temperature is shown in the top graph. VDACx is a smooth, monotonic function with, ideally, infinite precision. The LUT stores only the increments, or the rise, within each 4°C interval. In order to recreate the original transfer function, the series of increments must be summed together and added to the constant BASE value. BASE represents the constant offset which is lost due to the differentiation - storage of the increments only. This process must also be referenced to the common temperature point. This reference temperature is called BASELINE in this document, and is fixed at 24°C. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 15 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com VDACx û4 BASE 24°C Temperature 4°C 4°C û VDACx û4 1 2 3 4 LUT Index BASELINE Figure 22. Original Transfer Function The LUT and ALU Organization, LUT Coefficient to Register Mapping, and The LUT Input and Output Ranges sections below detail the operation of the LUTs and the ALUs. 8.3.2.1 LUT and ALU Organization In Figure 23 TEMP represents the 12-bit input value to the LUT. This value is produced by the local temperature sensor, or it can be provided by the user through the use of the OVERRIDE registers. The OVERRIDE modes are described in the later sections. TEMP is truncated, and TEMP[11:6] is used to index the LUT. The truncation is equivalent to reducing the TEMP resolution from 0.0625°C/LSB to 4°C/LSB. The overall transfer function is stored in the LUT as a set of unsigned 4-bit increments from the BASE value, that is, LUT location (+1) stores the value of the increment Δ1. This is shown in Figure 23. The BASELINE is 24°C temperature reference point, and BASE is the numeric representation of the required output at 24°C TEMP INDEX VALUE K+1 û(K+1) K ûK 36°C +3 û3 32°C +2 û2 28°C +1 û1 24°C BASELINE BASE 20°C -1 û-1 -(M-1) û-(M-1) -M û-M 128°C Temp. Sensor -28°C Figure 23. LUT Organization When TEMP is above 24°C, the LUT is addressed above the BASELINE address, all increments are added to the BASE value to produce numeric equivalent of the analog output. When TEMP is below 24°C, LUT is addressed below the BASELINE, all increments are subtracted from the BASE value to produce DACIN. 16 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Interpolation function is implemented in the ALU that follows the LUT. The truncated lower bits of the TEMP value, REM = TEMP[5:0], are used to interpolate between data points stored in the LUT. A portion of increment, αΔi, is added to form the final numeric output - the input data to the DAC. The factor α is a fraction of 4°C temperature span, or equivalently it is a fraction of the 64-code temperature span. D REM 64 (1) The process of calculating the DACIN, including the interpolation, is depicted in Figure 24. The DACIN is the final 12-bit value produced by the ALU and the LUT, and forwarded to the DAC for conversion to analog domain. K DACIN = BASE + ™ ûi + . û(K+1) i=1 DACIN .û(K+1) ûK+1 ûK REM û3 û2 û1 M ™û-i + . û-M i=1 DACIN = BASE ± BASE û-1 REM û-(M-1) û-M ) +K +(K +1 +3 +2 +1 -1 SE (24 o LIN C) E LUT INDEX (TEMP) Truncated Full Accuracy Truncated Full Accuracy BA -(M -1) -M .û-M Figure 24. DACIN Calculation Up to this point the algorithm description concerned only the generation of the monotonically increasing transfer function. The device can also produce monotonically decreasing transfer function by setting the DACx_BASEM.POL bit. The effect of polarity reversal (POL = 1) on the overall transfer function is shown in Figure 25. The LUT content is unchanged from the original example above. Note that now the LUT values stored at locations above BASELINE address are subtracted from BASE value, and the LUT values stored at locations below BASELINE address are added to the BASE value. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 17 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com DACIN û-M û-(M-1) û-1 BASE û1 û2 û3 ûK +(K +1 ) +K +3 +2 SE (24 o LIN C) E LUT INDEX (TEMP) BA +1 -1 -1) -(M -M ûK+1 Figure 25. Monotonically Decreasing Transfer Function The expressions used in the calculation of the transfer function are summarized below: LUT index > BASELINE: DACIN POL BASE ( 1) § ¨ ¨ ¨ © ¦ § ¨ ¨ ¨ © M K 'i D'(K · ¸ 1) ¸ i 1 ¸ ¹ (2) LUT index < BASELINE: DACIN 18 POL BASE ( 1) ¦ ' i i 1 · ¸ D' M ¸ ¸ ¹ (3) Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 8.3.2.2 LUT Coefficient to Register Mapping For the sake of convenience the preceding sections referred to LUT coefficients as ΔK. These are stored in the operating memory in the registers DELx. This is reflected in the Register Map section of this document. The example of the ΔK to DELx register mapping is shown in Table 2 section below. Table 2. ΔK to DELx Register Mapping TEMPERATURE FUNCTION INCREMENT REGISTER ASSIGNMENT –28°C Δ–13 DEL0 ↓ ↓ ↓ 20°C Δ–1 DEL12 28°C Δ+1 DEL13 ↓ ↓ ↓ Δ+26 DEL38 124°C 128°C 8.3.2.3 The LUT Input and Output Ranges The programmable LUT input range spans temperatures –28°C to 128°C. For the temperatures below –28°C the LUT output is linearly extrapolated; that is, the increment Δ–13 (register DEL0) stored at the location corresponding to –28°C is used as the slope down to –40°C. Computed DAC input data Extrapolated LUT output LUT Range DEL0 -40° C -28°C -24°C +124°C +128°C Temperature Sensor Output Figure 26. Temperature Sensor Output Although the maximum output of the temperature sensor is 127.9375°C, the LUT index corresponding to 128°C (DEL38) is required for proper interpolation when the temperature is above 124°C. The increments stored in the LUT are 4-bit unsigned values. This limits the maximum slope of the transfer function stored in the LUT to: = SLOPEMAX = 16LSB 4 qC 4LSB qC (4) Given this slope limit imposed by the LUT structure, and the fact that the LUT input range is 156°C (from –28°C to 128°C ), the maximum output range of the LUT due to the temperature sensor input is 624 LSBs, for the given BASE value. NOTE The maximum span of 624 codes can reside anywhere within the 0 to 4095 code space of the 12-bit DAC input. The total input code to the DAC is the sum of the increments (Δs) and the 12-bit BASE value. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 19 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 8.3.3 Analog Signal Path The simplified schematic of one analog channel of the device is shown in Figure 27. The LMP92066 contains 2 such channels. The following sub-sections describe each of the individual blocks within a channel. DACxM.DAC DACxL.DAC DACxM_OVRD.DAC DACxL_OVRD.DAC VDD VDDB DAC BUFFER 0 1 S 1 2 DACx OVRD_CTL.DAC GNDA VSSB FETDRVx DRVENx VSSB Figure 27. One Analog Channel Simplified Schematic 8.3.3.1 DAC The DAC produces unipolar output voltage proportional to the 12-bit input code. The input code format is offset binary, where 0x000 represents minimum and the 0xFFF full-scale input. The input code is produced by the LUT/ALU and stored in the DACxM and DACxL read-only registers. The user can also insert the DAC input code via the DACxM_OVRD and DACxL_OVRD registers, and by setting the OVRD_CTL.DAC bit. The DAC is referenced to the internally generated 5 V. The DAC transfer functions: DACIN VDACx 5A (V) 4096 (5) Where A is the Buffer Amplifier gain (see Buffer Amplifier) and DACIN is the 12-bit input code stored in either: { DACxM[3:0], DACxL[7:0] } or { DACxM_OVRD[3:0], DACxL_OVRD[7:0] } The LUT Input and Output Ranges describes the maximum output code span of the LUT, for the given base value. This also implies that when DACxM and DACxL registers are selected as the DAC inputs, the maximum VDACx output excursion over temperature is: 4LSB 5V dVDACx SLOPEMAX x TRANGE x VLSB x156qC x 762mV qC 4096 (6) However, this limitation is lifted when using DACxM_OVRD and DACxL_OVRD registers as the DAC inputs. In this case the DAC input range is full 4096 codes, and the output spans 0 V to 5 V. 8.3.3.2 Buffer Amplifier The buffer amplifier provides the low impedance drive for the potential generated by the DAC. The output of the amplifier is always available at the DACx output pin of the device. The buffer is designed to drive large capacitive loads, as high as 10 µF. The structure of the Buffer is such that it can produce output voltages above or below GNDA potential. Both Buffer Amplifiers are biased from dedicated supply rails: VDDB and VSSB. The difference between the VDDB and VSSB is nominally 5 V, but the span can be above or below GNDA. The gain A of the Buffer Amplifier depends on the state of supply rails VDDB and VSSB. 20 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 When the span is above GNDA, or VDDB = 5 V and VSSB = 0 V, then the output buffer gain is A = 1. The net effect on the output of the analog processing chain is shown in Figure 28. The DAC input codes in the range of 0x000 to 0xFFF are mapped to the output voltage in the range of 0 V to 5 V. VDDB VDACx 5V A=1 0V VSSB DACx Input Code 0x000 0xFFF Figure 28. Output of Analog Processing Chain: Net Effect If the span is below GNDA, or VDDB = 0 V and VSSB = –5 V, then the output buffer gain is A = –1. This configuration is depicted Figure 29. This results in effective mapping of the DAC input codes in the range of 0x000 to 0xFFF, to the output voltage range of 0 V to –5 V. 0x000 0xFFF DACx Input Code VDDB VDACx 0V A=-1 -5V VSSB Figure 29. Common Mode Voltage Below GNDA, or VDDB = 0 V and VSSB = –5 V NOTE Both Buffer Amplifiers share the VDDB and VSSB rails. Therefore, both Buffers produce gain of A = 1, or both produce gain of A = –1. The state of the VDDB and VSSB supplies, whether their span is above or below GNDA is indicated by the state of the DRV_STATUS.GAN bit, and can be read by the controller via the I2C interface. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 21 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 8.3.3.3 Output On and Off Control The LMP92066 facilitates rapid turnon and shutdown of the downstream devices. The FETDRVx outputs can be switched ON or OFF by the DRVENx input, independently of the I2C bus transactions. The FETDRVx pin is driven by the Buffer amplifier when the corresponding DRVENx input pin is asserted HIGH. Otherwise, the FETDRVx pin is connected to VSSB. The control and switch design was optimized for minimum delay between the DRVENx input and the FETDRVx switching. The design also ensures that during the state transition there exists an instance when both switches at FETDRVx are open; that is, no possibility for the crow-bar current to flow from the Buffer output to VSSB. The switches are assured to default to the state where FETDRVx output is connected to VSSB at power up, as long as logic 0 is present at the DRVENx input. 8.3.4 Memory The internal memory of the device consists of 2 distinct areas: the user register set or operating memory and the EEPROM (non-volatile storage). The operating memory registers provide the control over device functionality, report internal status of the device, and store the signal path data (LUT, temperature sensor output, etc). A section of operating memory, designated as a SCRATCH PAD, is available for arbitrary data storage. All operating memory locations are directly accessible to the user via the I2C bus. The EEPROM is not directly accessible via the I2C bus. The EEPROM acquires its data via the transfer from the operating memory, upon user issued command. Sections READ and WRITE Access, Access Control, LUT, NOTEPAD Storage, and EEPROM, and Figure 30 detail the internal memory functionality. 8.3.4.1 READ and WRITE Access The operating memory consists of individually addressable bytes whose content can be accessed via a single I2C transaction. For 8-bit data, as soon as the I2C transfer is complete the transferred value takes effect. The device also uses values longer that 8 bits — for example, with Temperature Sensor output, Temperature Sensor Override input, and the DAC input and Override registers are 12-bit values which require storage in 2 adjacent registers. For these values any access should start with the register containing the upper 4 bits, immediately followed by the access to the lower byte. NOTE It is the WRITE of the lower byte that results in the update of the 12-bit value. See Table 3. Table 3. Block Writing 2 I C OPERATION WRITE 22 REGISTER BLK_CNTL DATA DESCRIPTION 0x8F Enable the BLOCK access and set the block length to 15. This transfer results in the immediate update of the BLK_CNTL register and immediate change of behavior of the I2C interface. WRITE TEMPM_OVRD 0x08 Write the upper nibble of the Temperature Sensor override value. This transaction does not result in the update of the TEMPM_OVRD register. The transferred value is placed on a queue awaiting the transfer of the lower byte. The output of the device is not affected. WRITE TEMPL_OVRD 0x00 Write the lower byte of the Temperature Sensor override value. This transaction results in the update of both the TEMPM_OVRD and TEMPL_OVRD registers. The output of the device changes accordingly with the new setting. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 8.3.4.2 Access Control By default, all operating memory locations are open to READ access. The WRITE access is controlled by the Access Level setting. Increasing the Access Level, broadens the scope of the WRITE access. There are 3 access levels available to the user; see Access Control. User can change the current Access Level by writing a “password” sequence to the ACC_CNTL register. The “password” sequences are 2 consecutive I2C byte transfers to the ACC_CNTL register. The data content of each 2 byte transfer is unique for each access level. For example, to enter access level L2 perform the following 2 transfers: Table 4. Memory Access Control 2 I C OPERATION REGISTER DATA WRITE ACC_CNTL 0xCD First byte of the “password”. WRITE ACC_CNTL 0xF0 Second byte of the “password”. After this transfer is completed the access level is changed to L2. 0x03 Optional: Reading the ACC_CNTL serves as status report. The possible returned values are: 0x00 – access level L0 0x01 – access level L1 is activated 0x03 – access level L2 is activated (and due to nesting, L1 is also indicated) READ ACC_CNTL DESCRIPTION Table 5. EEPROM Access Levels ACCESS LEVEL SCOPE L0 Default. User has READ access only to all locations in the operating memory. L1 User has READ access to all locations, and WRITE access to ADR_LK and BLK_CNTL registers. L2 User has READ and WRITE access to all operating memory locations. NOTE The access levels are nested. This means that L1 access level also gives all L0 level functionality. L2 access level provides L1 and L0 functionality. 8.3.4.3 LUT, NOTEPAD Storage, and EEPROM The LUT (its coefficients, BASE value, ALU control bits) and the NOTEPAD are stored in the operating memory block spanning addresses 0x40 through 0x7F. This space is directly accessible (READ and WIRITE) via the I2C bus. There is an option to store the LUT and the NOTEPAD in the non-volatile memory, EEPROM. The move of data from the operating memory to the EEPROM (BURN) is initiated by WRITING a command byte to the EEPROM_CNTL register. Upon power up the device automatically executes the TRANSFER of the EEPROM data to the operating memory. The user can also issue a command via the I2C bus to force the TRANSFER of data from the EEPROM to the operating memory. Table 6. EEPROM Control TRANSFER/BURN 2 I C OPERATION REGISTER DATA COMMENT TRANSFER WRITE EEPROM_CNTL 0x4E Transfer of data from the EEPROM to the operating memory. BURN WRITE EEPROM_CNTL 0xE4 Transfer of data from the operating memory to the EEPROM. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 23 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com The READ of the EEPROM_CNTL register returns the status of the BURN or TRANSFER. Table 7. Status of BURN or TRANSFER EEPROM_CNTL BIT FIELD DESCRIPTION RDYB 0 - The TRANSFER or BURN has completed 1 – The TRANSFER or BURN is in progress COR 1 – A bit error was detected during the transfer from EEPROM to the operating memory. The error has been corrected and the data is valid. UCOR 1 – A bit error was detected during the transfer from EEPROM to operating memory. The error was not corrected. LUT data is compromised. 0x00 0x05 Temp Sensor and DAC Data RESERVED 0x07 Temp Sensor Status, Override Control, EEPROM Control RESET, Access Level Control 0x11 RESERVED 0x16 Block Access Control RESERVED 0x18 Address Lock I 2C OPERATING MEMORY RESERVED 0x1E Output Drive Status, Device Version 0x1F RESERVED 0x40 Burn Counter, LUT Coefficients, LUT Control BURN COMMAND EEPROM TRANSFER COMMAND 0x6B 0x6C Note Pad 0x7F Figure 30. Memory-to-EEPROM Mapping 24 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 8.3.5 I2C Interface I2C bus is used for communication between the Master (the digital supervisor; for example, the microcontroller) and the Slave (LMP92066). This interface provides the user full access to all Data, Status, and Control registers of the device. LMP92066 supports Standard-mode and Fast-mode, 100 kbit/s and 400 kbit/s, respectively. All • • • • • • • • • transactions follow the format: Master begins all transactions by generating START condition. All transfers comprise 8-bit bytes. First byte following START must contain 7-bit Slave address. First byte is followed by a READ/WRITE bit. All subsequent bytes contain 8-bit data. By default, the device assumes 1-byte data transfers. Block access can be enabled via BLK_CNTL register, resulting in multi-byte transfers. Bit order within a byte is always MSB first ACK/NAK condition follows every byte transfer – this can be generated by either Master or the Slave depending on direction of data transfer. STOP condition generated by the MASTER terminates all transactions, and resets the I2C bus. LMP92066 resets its internal address pointer to 0x00. 8.3.5.1 Supported Data Transfer Formats Table 8 lists all conditions defined by the I2C specification and supported by this device. All following bus descriptions refer to the symbols listed in Table 8. Table 8. I2C Symbol Set CONDITION SYMBOL SOURCE DESCRIPTION START S Master Begins all bus transactions STOP P Master Terminates all transations and resets bus ACK (Acknowledge) A Master/Slave Handshaking bit (LOW) NAK (Not Acknowledge) A Master/Slave Handshaking bit (HIGH) Master Active HIGH bit that follows immediately after the slave address sequence. Indicates that the master is initiating the slave-to-master data transfer. READ R WRITE W Master Active LOW bit that follows immediately after the slave address sequence. Indicates that the master is initiating the master-to-slave data transfer. REPEATED START Sr Master Generated by master, same function as the START condition (highlights the fact that STOP condition is not strictly necessary.) Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 25 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com The single data byte transfers are shown in Figure 31 and Figure 32: S Slave Address W A RegAddr[7:0] A Data[7:0] A P From MASTER to SLAVE From SLAVE to MASTER Figure 31. Single-Byte WRITE Access Protocol S Slave Address W A RegAddr[7:0] A Sr Slave Address R A Data[7:0] A P From MASTER to SLAVE From SLAVE to MASTER Figure 32. Single-Byte READ Access Protocol Block Access functionality is provided to minimize the transfer overhead of large data sets. By default the LMP92066 is ready to accept multi-byte transfers. Until the transaction is terminated by the STOP condition, the device will READ (WRITE) the subsequent memory locations. The size of the contiguous block can be limited by the user. This functionality can be enabled by setting BLK_CNTL.EN bit. The 7-bit value of BLK_CNTL.SIZE=N sets the size of the contiguous memory block that can be accessed via the block transfer. If the Master generates a block transfer that is larger than (BLK_CNTL.SIZE + 1), the internal register pointer wraps around to the First Register address and the access continue to subsequent memory locations. The examples of the block WRITE and READ transactions are shown below in Figure 33 and Figure 34: Address of the First Register of the contiguous memory block S Slave Address W A RegAddr[7:0] A From MASTER to SLAVE Data[7:0] A Data[7:0] A Data[7:0] A P Data to First Register N bytes of data to contiguous memory locations following First Register From SLAVE to MASTER Figure 33. Block WRITE Access — BLK_CNTL.EN = 1, BLK_CNTL.SIZE = N Address of the First Register of the contiguous memory block S Slave Address W A RegAddr[7:0] A Sr Data[7:0] Slave Address A R A Data[7:0] A Data[7:0] A P Data to First Register From MASTER to SLAVE From SLAVE to MASTER N bytes of data to contiguous memory locations following First Register Figure 34. Block READ Access — BLK_CNTL.EN = 1, BLK_CNTL.SIZE = N 26 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 8.3.5.2 Slave Address Selection The I2C bus slave address is selected by installing shunts from A0 and A1 pins of the device to the VIO or GNDD rails. The device discerns between 3 possible options for each pin: shunt to VIO, shunt to GNDD, or left not connected (floating), for the total of 9 possible slave addresses. The state of the A0 and A1 pins is tested after every occurrence of START condition on the I2C bus. However, the user has an option to LOCK the acquired address by setting the ADR_LK.EN bit. Once the address is locked, the device stores its Slave address internally and does not attempt to decode the address during subsequent I2C transactions. The address lock can be disabled by resetting ADR_LK.EN bit. The device resets the ADR_LK.EN upon power up. Figure 35 and Figure 36 illustrate the operation of the address decoder circuit. The device internally attempts to pull up, and then pull down, the Ax pin while monitoring the voltage at that pin. If the shunts are installed, the weak pull-ups or pull-downs does not affect the voltage at the Ax pin; that is. the state is fixed by the shunt. If the Ax pin floats, then pull-up and pull-down change the voltage at that pin. VIO VIO Device Terminal LMP92066 UPx SHUNT RUP Ax OUTx RDN ENx SHUNT GNDD DNx GNDD 2 Figure 35. I C Address Decoder - Simplified Diagram The address decoder operates during 2nd through 4th cycles of the SCL. The decoding of the state of Ax pins is performed serially; that is, A0 is decoded first then A1. The functional diagram of the address decoder is shown in Figure 36. SCL EN0 UP0 DN0 EN1 UP1 DN1 Figure 36. I2C Address Decoder - Functional Diagram Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 27 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com The interpretation of the OUTx values produced from the test phases is summarized in the following table. For example: if a shunt is present between Ax and VIO (first case in the table), both UPx phase and DNx phase result in OUTx being decoded as logical 1, unambiguously indicating the presence of the shunt to VIO, or HI state of Ax. Table 9. Address Decoder Output TEST PHASE DECODED Ax ↓ UPx DNx SHUNT to VIO: OUTx → 1 1 SHUNT to GNDD: OUTx → 0 0 LO NO SHUNT: OUTx → 1 0 N.C. HI The mapping from the decoded Ax states to the I2C Slave address is shown in Table 10. Table 10. Slave Address Space I2C SLAVE ADDRESS DEVICE PINS A1 A0 [A6:A0] LO LO 0111111 LO N.C. 1000000 LO HI 1000001 N.C. LO 1000010 N.C. N.C. 1000011 N.C. HI 1000100 HI LO 1000101 HI N.C. 1000110 HI HI 1000111 The Slave Address alignment within the first byte following the START condition is shown in Figure 37: S A6 A5 A4 A3 A2 A1 A0 R/W W A From MASTER to SLAVE From SLAVE to MASTER Figure 37. Slave Address Alignment 8.4 Device Functional Modes The numeric signal path is shown in Figure 38. The signal flow is generally from left to right: the system input is the temperature sensor, signal processing is done by the LUT/ALU, and the output is driven by the DACs - DAC detail is omitted as DACs provide a conversion from numeric domain to voltage domain only, and they do not affect the signal flow. There are a number of multiplexers in the signal path which alter the data flow when their respective control bits are set. The multiplexer states, and thus modes of device operation, are described in further detail below. 28 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Device Functional Modes (continued) DAC1_BASEM.POL DAC1_BASEM.BYP LUT1 0 ALU [11:6] S DAC1M.DAC 12 DAC1L.DAC 1 0 DAC1 DAC1M_OVRD.DAC DAC1L_OVRD.DAC 12 1 S [5:0] DAC1_BASEM DAC1_BASEL 12 OVRD_CTL.TEMP TEMPM.TEMP Temp. Sensor TEMPL.TEMP 12 0 S 12 TEMPM_OVRD.TEMP OVRD_CTL.DAC 1 TEMPL_OVRD.TEMP 12 DAC0_BASEM.POL LUT0 DAC0_BASM.BYP 0 ALU [11:6] 12 S DAC0M.DAC DAC0L.DAC 0 S 1 DAC0 DAC0M_OVRD.DAC DAC0L_OVRD.DAC 12 1 [5:0] DAC0_BASEM.BASE DAC0_BASEL.BASE 12 Figure 38. Modes of Operation 8.4.1 Default Operating Mode This mode of operation is active upon power up. By default the OVRD_CTL.TEMP and OVRD_CTL.DAC are cleared. The temperature sensor continuously updates readings every 25 ms (registers: TEMPM, TEMPL). Each temperature sensor update triggers the ALU to re-calculate its output using the user defined coefficients stored in the LUT. The ALU output is passed on to the DACs (registers: DACxM, DACxL) which ultimately drive the VDACx outputs. All of the functionality described here occurs automatically, without intervention from the system controller, as long as the power is applied to the device supply pins: VDD, VIO, and VDDB. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 29 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Device Functional Modes (continued) 8.4.2 Temperature Sensor Override The temperature sensor output can be overridden by the externally supplied data. This capability may be used to verify the validity of the function stored in the LUT. The externally supplied data can act as the temperature sweep input and the output response due to temperature may be readily observed, without actually altering the temperature of the test setup. This functionality is facilitated by the multiplexer that follows the temperature sensor, and user writable data registers TEMPM_OVRD and TEMPL_OVRD. TEMPM_OVRD[3:0] is the upper nibble of the temperature data. TEMPL_OVRD[7:0] is the lower byte of the temperature data. The multiplexer control signal is the OVRD_CTL.TEMP bit. Table 11 shows an example of the I2C bus transfer sequence which results in externally supplied data indexing the LUT. Table 11. I2C Bus Transfer Sequence: Externally Supplied Data Indexing LUT I2C OPERATION REGISTER DATA DESCRIPTION WRITE ACC_CNTL 0xCD First byte of the “password” WRITE ACC_CNTL 0xF0 Second byte of the “password”. After this transfer is completed the access level is changed to L2 READ ACC_CNTL 0x03 Optional: Reading the ACC_CNTL serves as status report. 0x03 – access level L2 is activated (and due to nesting, L1 is also indicated) WRITE TEMPM_OVRD 0x01 Writes 0x1 as the value of the top nibble of the 12-bit, twos complement, temperature value. After this transaction the TEMPM_OVRD register is not updated, yet. The update takes place only after the TEMPL_OVRD register is written. WRITE TEMPL_OVRD 0x01 Writes 0x01 into the lower byte of temperature value. After this transaction completes both TEMPM_OVRD and TEMPL_OVRD registers are updated. The 12-bit value in this example is 0x101 which corresponds to 16.0625°C WRITE OVRD_CTL 0x01 Sets the OVRD_CTL.TEMP bit. This causes the temperature stored in the TEMPM_OVRD and TEMPL_OVRD to index the LUT. READ TEMPM 0x** Optional: READ TEMPL 0x** Read the actual temperature reported by the temperature sensor. The temperature sensor override is cancelled by clearing the OVRD_CTL.TEMP bit. NOTE TEMPM_OVRD, TEMPL_OVRD and OVRD_CTL registers are in the volatile section of memory and are not backed by EEPROM. Upon power up these registers are cleared. 8.4.3 ALU Bypass It may be desirable that the device produces a predetermined constant output level as soon as it is powered up. The ALU bypass mode does that. This mode is enabled by setting DACx_BASEM.BYP bit. Since DACx_BASEM.BYP is stored in the EEPROM, its value is automatically loaded into the operating memory at power up. If the stored value for DACx_BASEM.BYP is 1, upon power up the corresponding DAC output immediately produces an analog output equivalent of the BASE. In this mode of operation the ALU is bypassed, and the BASE value of the LUT is presented at the input of the DAC. This is the result of DACx_BASEM.BYP, which controls the mux that follows the ALU in the signal path, being set. Therefore, the output of the device is constant over the operating temperature range of the device. 30 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 NOTE Each channel has its own BYP bit, and its own BASE value. 8.4.4 DAC Input Override The DAC inputs words can be directly written via the I2C interface. In this mode the LMP92066 is a dual 12-bit DAC. This functionality is facilitated by the multiplexers that precede the DACs, and user writable data registers DACxM_OVRD and DACxL_OVRD. DACxM_OVRD[3:0] is the upper nibble of the DAC input word. DACxL_OVRD[7:0] is the lower byte of the DAC input data. The multiplexer control signal is the OVRD_CTL.DAC bit. This bit is shared by both channels; that is, both channels are either in the DAC input override mode, or both are in the default mode. Table 12 shows the example of the I2C bus transfer sequence which results in externally supplied data being the source of input to the DACs. Table 12. I2C Bus Transfer Sequence: Externally Supplied Data Sourcing Input to DACs I2C OPERATION REGISTER DATA DESCRIPTION WRITE ACC_CNTL 0xCD First byte of the “password” WRITE ACC_CNTL 0xF0 Second byte of the “password”. After this transfer is completed the access level is changed to L2 READ ACC_CNTL 0x03 Optional: Reading the ACC_CNTL serves as status report. 0x03 – access level L2 is activated (and due to nesting, L1 is also indicated) WRITE DAC0M_OVRD 0x08 Writes 0x8 as the value of the top nibble of the 12-bit, offset binary, DAC0 input value. After this transaction the DAC0M_OVRD register is not updated, yet. The update takes place only after the DAC0L_OVRD register is written. WRITE DAC0L_OVRD 0x00 Writes 0x00 into the lower byte of the DAC0 input value. After this transaction completes both DAC0M_OVRD and DAC0L_OVRD registers are updated. The 12-bit value in this example is 0x800. WRITE DAC1M_OVRD 0x04 Writes 0x4 as the value of the top nibble of the 12-bit, offset binary, DAC1 input value. After this transaction the DAC1M_OVRD register is not updated, yet. The update takes place only after the DAC1L_OVRD register is written. WRITE DAC1L_OVRD 0x00 Writes 0x00 into the lower byte of the DAC1 input value. After this transaction completes both DAC1M_OVRD and DAC1L_OVRD registers are updated. The 12-bit value in this example is 0x400. WRITE OVRD_CTL 0x02 Sets the OVRD_CTL.TEMP bit. This causes both multiplexers that precede the DACs to start routing the DACx_OVRD values to the inputs of their respective DACs. As a result the outputs of the device are: VDAC0 = 2.5 V, and VDAC1 = 1.25 V READ DAC0M 0x** Optional: READ DAC0L 0x** Read the values computed by the ALU. NOTE The DAC Input Override and Temperature Sensor Override modes are mutually exclusive. The allowed values for OVRD_CTRL register are 0x00, 0x01 or 0x02. NOTE DACxM_OVRD, DACxL_OVRD and OVRD_CTL registers are in the volatile section of memory and are not backed by EEPROM. Upon power up these registers are cleared. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 31 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 8.4.5 LDMOS and GaN Drives The LDMOS mode and the GaN mode result from 2 possible biasing methods of the DAC output buffers – these were described in earlier sections of this data sheet. The LDMOS mode is in effect when the VDDB and VSSB common mode is above GNDA. This mode is suitable for biasing of the LDMOS Power Amplifiers, since the output produced by the LMP92066 is in the 0 V to 5 V range. The GaN mode is in effect when the VDDB and VSSB common mode is below GNDA. This mode is suitable for biasing of the GaN type Power Amplifiers, as the output produced by the LMP92066 is in the 0V to –5V range. 8.5 Programming 8.5.1 Temperature Sensor Output Data Access Registers The temperature sensor produces a 12-bit output value, TEMP[11:0], which is stored in 2 adjacent registers: TEMPM and TEMPL. The temperature sensor updates its output every 25 ms, nominally, but the exact instance of the update is unknown to the user. It is possible that the temperature sensor produces a new value between READ operations of TEMPM and TEMPL. Therefore, a synchronization mechanism was implemented, to assure that TEMPM and TEMPL values correspond to the same temperature sample. The coherence of the temperature sensor data is maintained if the READ sequence is: read TEMPM first, then TEMPL. ADDRESS 0x00 NAME TEMPM ACCESS TYPE R ACCESS LEVEL BIT FUNCTION 7 RES 6:5 * 4 RES 3:0 TEMP[11:8] L0 ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x01 TEMPL R L0 7:0 TEMP[7:0] DESCRIPTION Reserved bit. The value may be reported as 0 or 1 Reserved bit. Always reported as 0. Reserved bit. The value may be reported as 0 or 1. 4-bit MSB nibble of the 12-bit Temperature Sensor output word. DESCRIPTION 8-bit LSB byte of the 12-bit Temperature Sensor output word. 8.5.2 DAC Input Data Registers The 12-bit data produced by the LUT and ALU is stored in the DAC0M and DAC0L, and DAC1M and DAC1L pairs of registers. Unless overridden (see Override Control Register), the contents of these registers are presented at each DAC inputs. In cases where the user wants to read the temperature sensor output and resulting DACxM or DACxL data, the following read order has to be maintained to assure the coherency of data: TEMPM, TEMPL, DAC0M, DAC0L, DAC1M, DAC1L. Coherency of the TEMPM is still maintained, and TEMPL read is omitted in the sequence above. ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x02 DAC0M R L0 7:4 * 3:0 DAC[11:8] ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x03 DAC0L R L0 7:0 DAC[7:0] 32 Submit Documentation Feedback DESCRIPTION Reserved bit. Always report as 0. 4-bit MSB nibble of the 12-bit DAC0 input word. DESCRIPTION 8-bit LSB byte of the 12-bit Temperature Sensor output word. Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x04 DAC1M R L0 7:4 * 3:0 DAC[11:8] ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x05 DAC1L R L0 7:0 TEMP[7:0] DESCRIPTION Reserved bit. Always report as 0. 4-bit MSB nibble of the 12-bit DAC1 input word. DESCRIPTION 8-bit LSB byte of the 12-bit DAC1 input word. 8.5.3 Temperature Sensor Status Register This register may contain non-zero values immediately after the device power up. Within 100 ms of the power up the TEMP_STATUS register clears, indicating the temperature sensor’s output is valid. ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION DESCRIPTION 0x07 TEMP_STATUS R L0 7:0 RBYB If RDYB=0x00, the Temperature Sensor is initialized and producing valid output. 8.5.4 Override Control Register Override functionality allows the user to insert external data into the signal path of the device. When TEMP override is enabled, the temperature sensor’s data is ignored, and the user-supplied data is used to index the LUT (TEMPM_OVRD and TEMPL_OVRD, below). When DAC override is enabled the LUT and ALU produced output is ignored, and both DAC0 and DAC1 use external data as their inputs (DAC0M_OVRD, DAC0L_OVRD and DAC1M_OVRD and DAC1L_OVRD described below). NOTE Only 3 OVRD_CNTL[2:0] settings are allowed: 0x0, 0x1, 0x2; simultaneous DAC and TEMP override is not allowed. ADDRESS 0x08 NAME OVRD_CNTL ACCESS TYPE ACCESS LEVEL R/W L2 BIT FUNCTION DESCRIPTION 7:4 * Reserved bit. Always WRITE 0 3 RES Reserved bit. Always WRITE 0 2 RES Reserved bit. Always WRITE 0 1 DAC DAC override enable bit: 0: DAC input generated by LUT 1: DAC input is supplied from user accessible registers DACxy_OVRD. 0 TEMP DAC override enable bit: 0: DAC input generated by LUT 1: DAC input is supplied from user accesible registers TEMPy_OVRD. 8.5.5 Override Data Registers These registers hold the externally supplied data to be inserted into the signal path of the device (see OVRD_CNTL). NOTE Since override data are 12-bit words stored in 2 adjacent registers, it is the writing of the lower byte that makes the new value take effect. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 33 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com ADDRESS NAME ACCESS TYPE ACCESS LEVEL 0x09 TEMPM_OVRD R/W L2 ADDRESS NAME ACCESS TYPE 0x0A TEMPL_OVRD ADDRESS BIT FUNCTION 7:4 * 3:0 TEMP[11:8] ACCESS LEVEL BIT FUNCTION R/W L2 7:0 TEMP[7:0] NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 7:4 * 0x0B DAC0M_OVRD R/W L2 3:0 DAC[11:8] ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x0C DAC0L_OVRD R/W L2 7:0 DAC[7:0] ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 7:4 * 0x0D DAC1M_OVRD R/W L2 3:0 DAC[11:8] ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x0E DAC1L_OVRD R/W L2 7:0 DAC[7:0] DESCRIPTION Reserved bit. Always report as 0. 4-bit MSB nibble of the 12-bit Temperature Sensor override input word. DESCRIPTION 8-bit LSB byte of the 12-bit Temperature Sensor output word. DESCRIPTION Reserved bit. Always report as 0. 4-bit MSB nibble of the 12-bit DAC0 input override word. DESCRIPTION 8-bit LSB byte of the 12-bit DAC0 input override word. DESCRIPTION Reserved bit. Always report as 0. 4-bit MSB nibble of the 12-bit DAC1 input override word. DESCRIPTION 8-bit LSB byte of the 12-bit DAC1 input override word. 8.5.6 EEPROM Control Register Writing a command byte results in either the EEPROM BURN (the commitment of a section of operating memory to non-volatile storage), or the TRANSFER (recall of the data in the non-volatile storage to the operating memory. Reading this register yields status information. NOTE UCOR and COR bits are updated only by the TRANSFER command. 34 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com ADDRESS SNAS634B – MARCH 2014 – REVISED JANUARY 2016 NAME ACCESS TYPE ACCESS LEVEL W 0x0F L2 EEPROM_CNTL R BIT FUNCTION DESCRIPTION 7:0 * Instruction to BURN EEPROM or TRANSFER EEPROM content to operating memory: 0xE4: BURN EEPROM. 0x4E: TRANSFER data from EEPROM to operating memory. 7:3 * Reserved bit. 2 UCOR 1 COR 1: A bit error was detected and corrected during the TRANSFER. 0: No errors detected during the TRANSFER. 0 RDYB 1: BURN or TRANSFER in progress. 0: BURN or TRANSFER completed. L0 1: More than one bit error was detected during the TRANSFER, and correction was not possible. 0: No uncorrected errors were detected during the TRANSFER. 8.5.7 Software RESET Register Has the same effect as the power-on reset. ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x10 RESET W L2 7:0 DAC[7:0] DESCRIPTION WRITE 0xC3 to reset the deice to the power-up default state. 8.5.8 Access Control Register Changing the Access Level requires writing the 2-byte password sequence. Reading this register yields status information. ADDRESS 0x11 NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION W L0 7:0 PSWD 7:2 * * 1 * 1: Access Level L2 is enabled. 0: L2 not enabled. 0 RES 1: Access Level L1 is enabled. 0: L1 not enabled. ACC_CNTL R L0 DESCRIPTION WRITE 2-byte password to change access level: 0xCD, 0xEF: Access Level L1. 0xCD, 0xF0: Access Level L2. 8.5.9 Block I2C Access Control Register The I2C master may request a continuous transfer of data from or to the slave. By default, the slave continues advancing its internal register pointer to the end of the internal register space, and then wrap back to address 0x00 and continue on. BLK_CNTL allows to limit the size of the contiguous memory accessed continuously. ADDRESS 0x16 NAME BLK_CNTL ACCESS TYPE ACCESS LEVEL R/W BIT FUNCTION 7 EN 6:0 * L1 DESCRIPTION Enable the control of the I2C access block size: 1: Enabled. 0: Block size control is disabled. 7-bit SIZE of the I2C access block. The continuous I2C transaction accesses SIZE+1 memory locations, and then wrap back to the starting address. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 35 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 8.5.10 I2C Address LOCK Register Allows the device to LOCK its own I2C slave address. Once the slave address is locked, the device does not attempt to decode the state of A0 and A1 address setting pins on subsequent transactions. ADDRESS 0x18 NAME ADR_LK ACCESS TYPE R/W ACCESS LEVEL L1 BIT FUNCTION DESCRIPTION 7:3 * 2 RES Always set to 0 Reserved bit. Always write 0. 1 RES Reserved bit. Always write 0. 0 EN 1: Lock the slave address 0: Slave address is not locked. Device decodes state of A1 and A0 after every START condition of the I2C bus. NOTE The locked address is the one present at the A[1:0] pins during the I2C transaction that follows the ADR_LK command. 8.5.11 Output Drive Supply Status Register The device output stage can operate in either LDMOS or GaN modes. The mode is determined by the potential applied to the VDDB and VSSB supply pins. The device monitors the VDDB and VSSB supplies, and reports the mode of operation via the GaN status bit. ADDRESS 0x1E NAME DRV-STATUS ACCESS TYPE R ACCESS LEVEL L0 BIT FUNCTION 7:1 * DESCRIPTION Reserved. Always reports 0 0 GAN 1: GaN mode supply rails detected; that is, VDDB = GNDA, VSSB = –5V. 0: LDMOS mode supply rails detected; that is, VDDB = +5V, VSSB = GNDA. DESCRIPTION 8.5.12 Device Version Register Factory set value. ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x1F VERSION R L0 7:0 VERSION 8-bit device revision number. 8.5.13 EEPROM Burn Counter The value is incremented automatically at the start of BURN sequence. This data is transferred automatically from the EEPROM to operating memory upon power up. ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x40 BURN_CT R L0 7:0 COUNT DESCRIPTION 8-bit EEPROM BURN counter. 8.5.14 LUT Coefficient Registers This data is transferred to the EEPROM when a BURN command sequence is issued. This data is transferred automatically from the EEPROM to operating memory upon power up or after a software reset. 36 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 NOTE The LUT values are stored at locations corresponding to 4°C increments from –28°C to 128°C. There is no increment corresponding to 24°C because this temperature is a BASELINE, and the corresponding LUT value is 12-bit BASE (see Look-Up-Table (LUT) and Arithmetic-Logic Unit (ALU) ). ADDRESS NAME 0x41 DEL0 ↓ ↓ 0x4D DEL12 (20°C) 0x4E DEL13 (28°C) ↓ ↓ 0x67 DEL38 (128°C) ACCESS TYPE ACCESS LEVEL R/W BIT FUNCTION DESCRIPTION 7:4 DAC1[3:0] 4-bit LUT1 entry 3:0 DAC0[3:0] 4-bit LUT0 entry L2 8.5.15 LUT Control Registers This data is transferred to the EEPROM when a BURN command sequence is issued. This data is transferred automatically from the EEPROM to operating memory upon power up. ADDRESS 0x68 NAME DAC0_BASEM ACCESS TYPE ACCESS LEVEL R/W BIT FUNCTION 7 RES Reserved bit. Always write 0. 6 RES Reserved bit. Always reported as 0. 5 BYP ALU bypass control: 1: Bypass ALU. Send BASE value to DAC0. 0: ALU output sent to DAC0. 4 POL LUT increment polarity control: 1: All LUT values are treated as negatives. This realizes a monotonically decreasing LUT0 transfer function. 0: All LUT values are treated as positive numbers. This realizes a monotonically increasing LUT0 transfer function. 3:0 BASE[11:8] L2 DESCRIPTION 4-bit MSB nibble of the 12-bit LUT0 BASE value (LUT0 output at +24°C). ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x69 DAC0_BASEL R L2 7:0 BASE[7:0] ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 7 RES Reserved bit. Always write 0. 6 RES Reserved bit. Always reported as 0. 5 BYP ALU bypass control: 1: Bypass ALU. Send BASE value to DAC1. 0: ALU output sent to DAC1. 4 POL LUT increment polarity control: 1: All LUT values are treated as negatives. This realizes a monotonically decreasing LUT1 transfer function. 0: All LUT values are treated as positive numbers. This realizes a monotonically increasing LUT1 transfer function. 3:0 BASE[11:8] 0x6A DAC1_BASEM R/W L2 DESCRIPTION 8-bit LSB byte of the 12-bit BASE value (LUT0 output at +24°C). DESCRIPTION 4-bit MSB nibble of the 12-bit LUT1 BASE value (LUT0 output at +24°C). Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 37 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com ADDRESS NAME ACCESS TYPE ACCESS LEVEL BIT FUNCTION 0x6B DAC1_BASEL R L2 7:0 BASE[7:0] DESCRIPTION 8-bit LSB byte of the 12-bit BASE value (LUT1 output at +24°C). 8.5.16 Notepad Registers 20 bytes of memory for arbitrary data storage. This data does not affect the operation of the device. This data is transferred to the EEPROM when BURN command sequence is issued. This data is transferred automatically from the EEPROM to operating memory upon power up. ADDRESS NAME 0x6C PAD0 38 ↓ ↓ 0x7F PAD19 ACCESS TYPE R/W ACCESS LEVEL L2 BIT 7:0 FUNCTION DESCRIPTION * 20 bytes of memory for arbitrary data storage. This data does not affect the operation of the device. This data is transferred to the EEPROM when BURN command sequence is issued via I2C transaction. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 8.6 Register Map ADDRESS TYPE ACC. LVL NAME TEMPM 7 6 RES 5 BIT FIELDS 4 3 8'h00 R L0 0 8'h01 R L0 TEMPL 8'h02 R L0 DAC0M 8'h03 R L0 DAC0L 8'h04 R L0 DAC1M 8'h05 R L0 DAC1L DAC[7:0] 8'h06 R L0 RES RES 8'h07 R L0 8'h08 R/W L2 OVRD_CNTL 2 RES 1 0 NOTES TEMP[11:8] TEMP[7:0] 0 DAC[11:8] DAC[7:0] 0 DAC[11:8] TEMP_STATUS RDYB RDYB RDYB RDYB RDYB RDYB RDYB RDYB 8'h09 R/W L2 TEMPM_OVRD 8'h0A R/W L2 TEMPL_OVRD 8'h0B R/W L2 DAC0M_OVRD 8'h0C R/W L2 DAC0L_OVRD 8'h0D R/W L2 DAC1M_OVRD 8'h0E R/W L2 DAC1L_OVRD POR RES RES 0 8'hFF DAC TEMP TEMP[11:8] 8'h01 TEMP[7:0] 8'h80 0 DAC[11:8] 8'h80 DAC[7:0] 8'h00 0 DAC[11:8] 8'h80 DAC[7:0] 8'h00 For BURN write: 8'hE4 For TRANSFER write: 8'h4E 8'h0F W L2 EEPROM_CNTL BURN or TRNASFER command 8'h0F R L0 EEPROM_CNTL 8'h10 W L2 RESET SYSTEM RESET ± EQUIVALENT TO POWER-UP write: 8'hC3 8'h11 W L0 ACC_CNTL ACCESS LEVEL PASSWORD For L1 write: 8'hCD,8'hEF For L2 write: 8'hCD,8'hF0 8'h11 R L0 ACC_CNTL 8'h12 R/W L1 RES 8'h13 W L1 8'h13 R L0 8'h14 R/W L1 RES RES 8'h00 8'h15 R/W L1 RES RES 8'h00 8'h16 R/W L1 BLK_CNTL 8'h17 R/W L1 RES 0 RES RES RES 8'h00 8'h18 R/W L1 ADR_LK 0 RES RES EN 8'h00 8'h19 R/W L1 RES 0 RES RES 8'h00 8'h1A R/W L1 RES 0 RES 8'h00 8'h1E R L0 DRV_STATUS 8'h1F R L0 VERSION UCOR COR RDYB L2 L1 8'h00 0 RES 8'h00 RES 0 RES 8'h00 RES 0 RES 8'h00 EN SIZE 8'h00 RES 0 GAN VERSION=8'hA0 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 39 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Register Map (continued) ADDRESS TYPE 40 ACC. LVL NAME 7 6 5 BIT FIELDS 4 3 2 1 0 NOTES 8'h40 R L0 BURN_CT 8'h41 R/W L2 DEL0 DAC1[3:0] DAC0[3:0] -28°C 8'h42 R/W L2 DEL1 DAC1[3:0] DAC0[3:0] -24°C 8'h43 R/W L2 DEL2 DAC1[3:0] DAC0[3:0] -20°C 8'h44 R/W L2 DEL3 DAC1[3:0] DAC0[3:0] -16°C 8'h45 R/W L2 DEL4 DAC1[3:0] DAC0[3:0] -12°C 8'h46 R/W L2 DEL5 DAC1[3:0] DAC0[3:0] -8°C 8'h47 R/W L2 DEL6 DAC1[3:0] DAC0[3:0] -4°C 8'h48 R/W L2 DEL7 DAC1[3:0] DAC0[3:0] 0°C 8'h49 R/W L2 DEL8 DAC1[3:0] DAC0[3:0] 4°C 8'h4A R/W L2 DEL9 DAC1[3:0] DAC0[3:0] 6°C 8'h4B R/W L2 DEL10 DAC1[3:0] DAC0[3:0] 12°C 8'h4C R/W L2 DEL11 DAC1[3:0] DAC0[3:0] 16°C 8'h4D R/W L2 DEL12 DAC1[3:0] DAC0[3:0] 20°C 8'h4E R/W L2 DEL13 DAC1[3:0] DAC0[3:0] 28°C 8'h4F R/W L2 DEL14 DAC1[3:0] DAC0[3:0] 32°C 8'h50 R/W L2 DEL15 DAC1[3:0] DAC0[3:0] 36°C 8'h51 R/W L2 DEL16 DAC1[3:0] DAC0[3:0] 40°C 8'h52 R/W L2 DEL17 DAC1[3:0] DAC0[3:0] 44°C 8'h53 R/W L2 DEL18 DAC1[3:0] DAC0[3:0] 48°C 8'h54 R/W L2 DEL19 DAC1[3:0] DAC0[3:0] 52°C 8'h55 R/W L2 DEL20 DAC1[3:0] DAC0[3:0] 56°C Submit Documentation Feedback POR Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Register Map (continued) ADDRESS TYPE ACC. LVL NAME 7 6 5 BIT FIELDS 4 3 2 1 0 NOTES 8'h56 R/W L2 DEL21 DAC1[3:0] DAC0[3:0] 60°C 8'h57 R/W L2 DEL22 DAC1[3:0] DAC0[3:0] 64°C 8'h58 R/W L2 DEL23 DAC1[3:0] DAC0[3:0] 68°C 8'h59 R/W L2 DEL24 DAC1[3:0] DAC0[3:0] 72°C 8'h5A R/W L2 DEL25 DAC1[3:0] DAC0[3:0] 76°C 8'h5B R/W L2 DEL26 DAC1[3:0] DAC0[3:0] 80°C 8'h5C R/W L2 DEL27 DAC1[3:0] DAC0[3:0] 84°C 8'h5D R/W L2 DEL28 DAC1[3:0] DAC0[3:0] 88°C 8'h5E R/W L2 DEL29 DAC1[3:0] DAC0[3:0] 92°C 8'h5F R/W L2 DEL30 DAC1[3:0] DAC0[3:0] 96°C 8'h60 R/W L2 DEL31 DAC1[3:0] DAC0[3:0] 100°C 8'h61 R/W L2 DEL32 DAC1[3:0] DAC0[3:0] 104°C 8'h62 R/W L2 DEL33 DAC1[3:0] DAC0[3:0] 108°C 8'h63 R/W L2 DEL34 DAC1[3:0] DAC0[3:0] 112°C 8'h64 R/W L2 DEL35 DAC1[3:0] DAC0[3:0] 116°C 8'h65 R/W L2 DEL36 DAC1[3:0] DAC0[3:0] 120°C 8'h66 R/W L2 DEL37 DAC1[3:0] DAC0[3:0] 124°C 8'h67 R/W L2 DEL38 8'h66 8'h68 R/W L2 DAC0_BASEM DEL37 8'h67 8'h69 R/W L2 DAC0_BASEL DEL38 8'h6A R/W L2 DAC1_BASEM 8'h6B R/W L2 DAC1_BASEL DAC1[3:0] RES RES DAC1[3:0] BYP DAC1[3:0] RES RES BYP POL BASE[7:0] POL DAC0[3:0] 128°C BASE[11:8] DAC0[3:0] 124° 24°CC DAC0[3:0] 128° 24°CC BASE[11:8] 24°C BASE[7:0] POR 24°C Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 41 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Register Map (continued) ADDRESS TYPE 42 ACC. LVL NAME 8'h6C R/W L2 PAD0 8'h6D R/W L2 PAD1 8'h6E R/W L2 PAD2 8'h6F R/W L2 PAD3 8'h70 R/W L2 PAD4 8'h71 R/W L2 PAD5 8'h72 R/W L2 PAD6 8'h73 R/W L2 PAD7 8'h74 R/W L2 PAD8 8'h75 R/W L2 PAD9 8'h76 R/W L2 PAD10 8'h77 R/W L2 PAD11 8'h78 R/W L2 PAD12 8'h79 R/W L2 PAD13 8'h7A R/W L2 PAD14 8'h7B R/W L2 PAD15 8'h7C R/W L2 PAD16 8'h7D R/W L2 PAD17 8'h7E R/W L2 PAD18 8'h7F R/W L2 PAD19 7 6 5 BIT FIELDS 4 3 2 1 Submit Documentation Feedback 0 NOTES POR Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LMP92066 was designed for ease of use. The device requires minimum external components to realize its full functionality. In the typical application the bulk of the design effort is spent on characterization of the target transfer function, and then developing a set of coefficients that the LMP92066 to accurately reproduce the target function. NOTE The LMP92066 can approximate temperature dependent functions, VDAC0,1(T), only if the following requirements are met: 1. Each VDAC0,1(T) must be unipolar. The range of the function must be either wholly positive, or wholly negative. This is dictated by the structure of the Buffer Amplifier that drives the FETDRVx. See the Buffer Amplifier section. 2. Both functions VDAC0,1(T) must be of the same polarity. See the Buffer Amplifier section. 3. Each VDAC0,1(T) must be monotonic. This is dictated by the structure of the LUTs. See the LUT and ALU Organization section. 4. The maximum slope of each VDAC0,1(T) is no greater than 4.88 mV/°C. This also limits the maximum range, the minimum to maximum span, for the VDAC0,1(T) to 761 mV. This is due to the fact that the LUT stores the slope of the VDAC0,1(T) as 4-bit values. See the The LUT Input and Output Ranges section. 9.2 Typical Applications 9.2.1 Temperature Compensated Bias Generator for LDMOS Power Amplifer (PA) The typical application for the LMP92066 is the biasing of the power amplifiers in an RF system. What is required in such applications is for the PA drain current to remain constant over a wide range of operating temperatures. The LMP92066 senses the PA temperature and adjust the bias potential at the gate of the PA in accordance with the known VGS(T), at ID = constant, characteristic of the PA. The typical application circuit for LDMOS applications is shown in Figure 39. A thermal path has to be provided between the LMP92066 and the PA. This is typically accomplished through the close proximity of the 2 devices, and the common metal layer. See also the Layout Example. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 43 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Typical Applications (continued) 3.3V 5V + VIO VDD RFIN 47µ 100n VDDB FETDRV1 10n DAC1 SDA PA: LDMOS /4 10µ SCL LMP92066 µC RFIN DRVEN1 DRVEN0 FETDRV0 A1 /4 A0 DAC0 GNDD GNDA VSSB PA: LDMOS 10n 10µ Figure 39. Temperature-Compensated Bias Generator for LDMOS Power Amplifier (PA) 9.2.1.1 Design Requirements The thermal characteristic of a hypothetical LDMOS PA is plotted in Figure 40. This characteristic was obtained from the temperature sweep of the LDMOS gate-source voltage, VGS, while keeping the drain current, ID = 750 mA. The goal is to have the LMP92066 produce that same VGS vs T characteristic which, when applied to the gate of the PA device ensures constant ID throughout the operating temperature range. In the following sections the curve VGS vs T are referred to as the Target Function, VDAC (T). 2.50 2.45 Target Response (V) 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 ±40 ±20 0 20 40 60 80 100 120 Temperature (ƒC) 140 C023 Figure 40. Target Function to be Reproduced by the LMP92066: VGS vs T Characteristic of an LDMOS PA The target function is approximated by the following polynomial (T unit is °C): VDAC (T) 5.1u 10 10 (T)4 2.63 u 10 8 (T)3 3.58 u 10 6 (T)2 5.14 u 10 4 (T) 2.26 (7) In the Detailed Design Requirements section the above expression is used to obtain the LUT coefficient values. 44 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Typical Applications (continued) 9.2.1.2 Detailed Design Requirements Figure 41 outlines the LUT design procedure. The procedure is for one channel only – repeat for the second available channel, as needed. In principle, the procedure follows the signal path backwards from the output, which is ideally the target function VDAC(T), back to the LUT coefficients, and each block’s processing has to be “reversed”. Additional comments for each design step are listed below Figure 41. Designate the target function VDAC(T) Assign pBUF(T) = -VDAC(T) No VDAC(T) > 0, for all T 1 Yes Assign pBUF(T) = VDAC(T) 2 VDDB = 0V, VSSB = -5V Assign cG(T) = -pBUF(T) VDDB = 5V, VSSB = 0V No dpBUF(T)/dT > 0, for all T Yes Assign cG(T) = pBUF(T) 3 POL=1 POL=0 Sample cG(T) at T= -28, -24..24..128(° C) Store fpBASE = cG(T=24°C) Store as G(k), k=0..39 4 Difference G(k) samples fpDEL(k) = G(k+1)-G(k), for k=0..38 5 Map Voltage to numeric domain, and quantize BASE = round( fpBASE x 4096/5 ) DEL(k) = round( fpDEL(k) x 4096/5 ) 6 BASE (12-bit) DEL(k) (4-bit) 7 Figure 41. Flowchart of the Generalized LUT Design Procedure 1. Before attempting to calculate the LUT coefficients for the given target function VDAC(T), verify the requirements listed in the Application Information section are met. 2. Test if the function is wholly positive, or negative. If necessary “undo” the action of the Buffer Amplifier. (See the Buffer Amplifier section.) From now on consider the pre-buffer signal pBUFF(T). The design variable set in this step is the state of the VDDB and VSSB supplies. VDAC(T) is a strictly positive valued function, therefore: VDDB 5V VSSB GNDA pBUFF(T) VDAC (T) (8) Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 45 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Typical Applications (continued) 3. Check the slope of the pBUF(T). Record the sign of the slope, and from here on consider a positive slope function cG(T). The design variable set in this step is the POL bit. pBUFF(T) is a monotonically increasing function, therefore: POL cG(T) 0 pBUFF(T) (9) 4. Discretize the continuous cG(T) along its temperature domain, thus creating the sequence G(k). Maintain the full precision of the G(k) values. Note the full precision cG(T) at T = 24°C — this is the full precision BASE value, fpBASE, still in voltage domain. G(0) cG( 28qC) 2.2499 G(1) cG( 24qC) 2.2508 G(2) cG( 20qC) 2.2508 p G(13) cG(24qC) 2.2747 fpBASE p G(39) cG(128qC) 2.4667 5. Apply difference operation to the G(k) sequence, and obtain new sequence fpDEL(k). These are now the full precision increments of the target function with each 4°C interval. fpDEL(0) G(1) G(0) 0.9528 u 10 3 fpDEL(1) G(2) G(1) 1.1846 u 10 3 fpDEL(2) G(3) G(2) 1.3891u 10 3 p fpDEL(38) G(39) G(38) 16.9789 u 10 3 6. Convert the full precision voltages of fpDEL(k) and fpBASE to a numeric, quantized domain. This reverses the DAC action. § fpBASE u 4096 · round ¨ ¸ 186310 74716 0111010001112 5 © ¹ fpDEL(0) 4096 u § · DEL(0) round ¨ ¸ 110 116 00012 5 © ¹ BASE p § fpDEL(38) u 4096 · round ¨ ¸ 1410 E16 11102 5 © ¹ 7. Usually BYP bit is reset, BYP=0. However, in cases where it is desirable to bypass the LUT and ALU, and have the DACx output produce voltage equivalent of the BASE value, set BYP = 1. 8. Repeat steps 1 to 6 to obtain POL, BYP, BASE, DELx values for the second channel. 9. Now have BYP, POL, BASE, and DEL(0..38) values ready to be programmed into the LUT. DEL(38) NOTE The device has to be in the L2 Access Level before commencing the WRITE access of BYP, POL, BASE, DELx values. The register WRITE operation immediately affects the operation of the device. However, operating memory is volatile, and BURN operation is required to commit the LUT coefficients to non-volatile memory, EEPROM. 46 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Typical Applications (continued) 9.2.1.3 Application Curves The output of the LMP92066 due to the coefficients calculated in the above procedure is shown in Figure 42. 2.50 10 2.45 8 2.40 6 2.35 4 Error (mV) Measured Response (V) Figure 43 shows the absolute difference between the target function and the measured response of the LMP92066. 2.30 2.25 2.20 2 0 ±2 2.15 ±4 2.10 ±6 2.05 ±8 2.00 ±10 ±40 ±20 0 20 40 60 80 100 120 140 Temperature (ƒC) ±40 Figure 42. Measured Response of the LMP92066 Resulting from the LUT Coefficients (see Detailed Design Requirements) ±20 0 20 40 60 80 100 120 Temperature (ƒC) C024 140 C025 Figure 43. Difference Between the Target Response shown in Figure 40 and Measured Response in Figure 42 9.2.2 Temperature Compensated Bias Generator for GaN Power Amplifer (PA) The typical application for the LMP92066 is the biasing of the power amplifiers in an RF system. What is required in such applications is for the PA drain current to stay constant over a wide range of operating temperatures. The LMP92066 senses the PA temperature and adjust the bias potential at the gate of PA in accordance with the known VGS(T), at ID = constant, characteristic of the PA. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 47 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Typical Applications (continued) 3.3V 5V + 100n VIO VDD RFIN 47µ VDDB FETDRV1 10n DAC1 SDA PA: GaN /4 10µ + SCL LMP92066 µC RFIN DRVEN1 DRVEN0 FETDRV0 A1 10n DAC0 GNDA VSSB + GNDD PA: GaN /4 A0 10µ + 10µ 100n -5V Figure 44. Temperature-Compensated Bias Generator for GaN Power Amplifier (PA) 9.2.2.1 Design Requirements The thermal characteristic of a hypothetical GaN PA is plotted in Figure 45. This characteristic was obtained from the temperature sweep of the GaN gate-source voltage, VGS, while keeping the drain current, ID = 750 mA. The goal is to have the LMP92066 produce that same VGS vs T characteristic which, when applied to the gate of the PA device ensures constant ID throughout the operating temperature range. In the following sections the curve VGS vs T is referred to as the Target Function, VDAC (T). ±1.00 ±1.05 Target Response (V) ±1.10 ±1.15 ±1.20 ±1.25 ±1.30 ±1.35 ±1.40 ±1.45 ±1.50 ±40 ±20 0 20 40 60 80 Temperature (ƒC) 100 120 140 C026 Figure 45. The Target Function to be Reproduced by the LMP92066: VGS vs T Characteristic of an GaN PA 48 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Typical Applications (continued) The target function is approximated by the following polynomial (T unit is °C): VDAC (T) 6.33 u 10 11 (T)4 2.34 u 10 8 (T)3 1.95 u 10 6 (T)2 5.04 u 10 4 (T) 1.26 9.2.2.2 Detailed Design Procedure Figure 46 outlines the LUT design procedure. The procedure is for one channel only – repeat for the second available channel, as needed. In principle, the procedure follows the signal path backwards from the output, which is ideally the target function VDAC(T), back to the LUT coefficients, reversing the processing of each block. Additional comments for each design step are listed below Figure 46. Designate the target function VDAC(T) Assign pBUF(T) = -VDAC(T) No VDAC(T) > 0, for all T 1 Yes Assign pBUF(T) = VDAC(T) 2 VDDB = 0V, VSSB = -5V Assign cG(T) = -pBUF(T) VDDB = 5V, VSSB = 0V No dpBUF(T)/dT > 0, for all T Yes Assign cG(T) = pBUF(T) 3 POL=1 POL=0 Sample cG(T) at T= -28, -24..24..128(° C) Store fpBASE = cG(T=24°C) Store as G(k), k=0..39 4 Difference G(k) samples fpDEL(k) = G(k+1)-G(k), for k=0..38 5 Map Voltage to numeric domain, and quantize BASE = round( fpBASE x 4096/5 ) DEL(k) = round( fpDEL(k) x 4096/5 ) 6 BASE (12-bit) DEL(k) (4-bit) 7 Figure 46. Flowchart of the Generalized LUT Design Procedure 1. Before attempting to calculate the LUT coefficients for the given target function VDAC(T), verify the requirements listed in the Application Information section are met. 2. Test if the function is wholly positive, or negative. If necessary “undo” the action of the Buffer Amplifier. (See the Buffer Amplifier section.) From now on consider the pre-buffer signal pBUFF(T). The design variable set in this step is the state of the VDDB, VSSB supplies. VDAC(T) is a strictly positive valued function, therefore: Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 49 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Typical Applications (continued) VDDB GNDA VSSB 5V pBUFF(T) VDAC (T) (10) 3. Check the slope of the pBUF(T). Record the sign of the slope, and from here on consider a positive slope function cG(T). The design variable set in this step is the POL bit. pBUFF(T) is a monotonically increasing function, therefore: POL 0 cG(T) pBUFF(T) (11) 4. Discretize the continuous cG(T) along its temperature domain, thus creating the sequence G(k). Maintain the full precision of the G(k) values. Note the full precision cG(T) at T = 24°C — this is the full precision BASE value, fpBASE, still in voltage domain. G(0) cG( 28qC) 1.2477 G(1) cG( 24qC) 1.2495 G(2) cG( 20qC) 1.2513 p G(13) cG(24qC) 1.2743 fpBASE p G(39) cG(128qC) 1.3893 (12) 5. Apply difference operation to the G(k) sequence, and obtain new sequence fpDEL(k). These are now the full precision increments of the target function with each 4°C interval. fpDEL(0) G(1) G(0) 1.8174 u 10 3 fpDEL(1) G(2) G(1) 1.8189 u 10 3 fpDEL(2) G(3) G(2) 1.8316 u 10 3 p fpDEL(38) G(39) G(38) 6.4124 u 10 3 6. Convert the full precision voltages of fpDEL(k) and fpBASE to a numeric, quantized domain. This reverses the DAC action. BASE § fpBASE u 4096 · round ¨ ¸ 5 © ¹ 104410 41416 010000010100 2 p DEL(0) § fpDEL(0) u 4096 · round ¨ ¸ 5 © ¹ 110 116 00012 p § fpDEL(38) u 4096 · round ¨ ¸ 510 516 01012 5 © ¹ 7. Usually BYP bit is reset, BYP=0. However, in cases where it is desirable to bypass the LUT and ALU, and have the DACx output produce voltage equivalent of the BASE value, set BYP = 1. 8. Repeat steps 1 to 6 to obtain POL, BYP, BASE, DELx values for the second channel. 9. Now have BYP, POL, BASE, and DEL(0..38) values ready to be programmed into the LUT. DEL(38) 50 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Typical Applications (continued) NOTE The device has to be in the L2 Access Level before commencing the WRITE access of BYP, POL, BASE, DELx values. The register WRITE operation immediately affects the operation of the device. However, operating memory is volatile, and BURN operation is required to commit the LUT coefficients to non-volatile memory, EEPROM. 9.2.2.3 Application Curves The output of the LMP92066 due to the coefficients calculated in the above procedure is shown in Figure 47. ±1.00 10 ±1.05 8 ±1.10 6 ±1.15 4 Error (mV) Measured Response (V) Figure 48 shows the absolute difference between the target function and the measured response of the LMP92066. ±1.20 ±1.25 ±1.30 2 0 ±2 ±1.35 ±4 ±1.40 ±6 ±1.45 ±8 ±1.50 ±10 ±40 ±20 0 20 40 60 80 100 Temperature (ƒC) 120 140 ±40 Figure 47. Measured Response of the LMP92066 Resulting from the LUT Coefficients (see Detailed Design Procedure) ±20 0 20 40 60 80 100 120 Temperature (ƒC) C027 140 C028 Figure 48. Difference Between the Target Response shown in Figure 45 and Measured Response in Figure 47 9.3 Do's and Don'ts 9.3.1 Output Drive Switching Some applications may require that the FETDRVx output reaches the level set by the DACx as fast as possible after the assertion of DRVENx. There are parameters which determine the delay between the assertion of DRVENx, and the FETDRVx output achieving its final level as set by the DACx: • The delay between the DRVENx input the output switch. • The charge up time of the FETDRVx node once the output switch is closed. The delay of the switch response to the DRVENx input, tON, is specified in the Electrical Characteristics table. The charge up time of the FETDRVx node is dependent on the selection of the external components. Rapid rise time of the FETDRVx output, is made possible through the use of the external capacitor C1. C1 is always charged to the potential generated by the DACx, and used to provide instantaneous charge to the load present at the FETDRVx when the output switch closes – the switch between DACx and FETDRVx pin. C1 is chosen to be several orders of magnitude larger than the total capacitance present at the FETDRVx pin, CEXT. In the typical application C1 is 10 µF, and CEXT is limited to 10 nF. See Figure 49. When the output switch closes, a current flows from the C1, acting as a reservoir, to CEXT. This charge-up current is limited only by the resistance of the output switch RDRV, resulting in very rapid slewing at the FETDRVx pin. RDRV is specified in the Electrical Characteristics table. For example, given the following parameters. • tON = 50 ns Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 51 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com Do's and Don'ts (continued) • • RDRV = 5 Ω CEXT = 10 nF The total delay time between activation of DRVENx and FETDRVx achieving 95% of its final value is: TDELAY = tON+ 5τ = tON + 5RDRVCEXT = 300 ns (13) NOTE The charge current flowing into the CEXT at the instant the output switch closes is relatively large and of very short duration, which makes the parasitic inductance in the charge path significant. This parasitic inductance is due to the bond wire and package pin between the device die and the CEXT, and is shown as LP in Figure 49. In some applications it may be beneficial to insert a small resistance in the charge path, see REXT in Figure 49, to dampen the resonance of the LP and CEXT. Choice of REXT is highly application dependent, but 5 Ω is a good initial selection. LMP92066 DACx + C1 FETDRV x DACx RDRV LP REXT CEXT P A DRVENx Figure 49. Flow of Charge Current 9.4 Initialization Setup 9.4.1 Factory Default At the factory the EEPROM is initialized such that all LUT increment values (Δ) are set to 0, BASE value is set to 0x00, and BYP and POL bits are set to 0. This results in the device producing constant output of 0V at DACx pins upon power up, regardless of the temperature or mode or state at the DRVENx inputs. 9.4.2 At Power Up The device is capable of autonomous operation upon power up, without intervention form the system controller. When the power is applied and reaches the minimum level (approximately 4.1 V) the temperature sensor begins operating, and the internal sequencer begins the transfer of LUT values from the EEPROM to the operating memory. Once the transfer is complete, and the Temperature Sensor has completed the first conversion, the ALU computes the DACs input values, and the DACs start producing output voltages representative of the transfer functions implemented in the LUTs. The control signal applied to the DRVENx input determines whether the DAC output voltage is present at the FETDRVx output, or that output is driven to VSSB potential. Figure 50 shows the typical power-up transient behavior at the DACx outputs. While VDD voltage is ramping up from 0 to 5 V the DACx outputs initially follow the VDD. This is due to the fact that initially the device is in the undefined state. When VDD reaches 4.1 V the internal reset occurs and clears the internal data path, resulting in VDACx = 0 V. The Temperature Sensor begins operation at the moment of reset, and 25 ms later produces its first temperature measurement. This, in turn, causes the ALU to update DAC input data, resulting in new VDACx output. 52 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 Initialization Setup (continued) VDD VDAC1 VDAC0 Time (10 ms/DIV) C020 VDD = 2V/div VDAC1 = 1V/div VDAC0 = 1V/div Figure 50. Power-Up Transient Behavior See also the Default Operating Mode section. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 53 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 10 Power Supply Recommendations The device rails VIO, VDD, and VDDB (VSSB in GaN mode) should be supplied from a well-regulated power supply capable of sourcing at least 50 mA. The required supply levels are shown in the Specifications tables of this document. Along with ceramic bypass capacitors, additional bulk capacitance is recommended on the VDD node. The function of this bulk capacitance is to provide the momentary increases in the supply current requirements due to the EEPROM activity. An electrolytic capacitor with a value of 10 μF to 47 μF is a typical choice. 10.1 VDD Supply Sourcing The power supply powering the VDD pin must be capable of sourcing a minimum of 50mA. This is required in order to avoid the continuous activation of the LMP92066’s power-on-reset (POR) circuit. When the VDD supply rail passes through the POR voltage of approximately 4.2V (either rising or falling edge), an increase in supply current occurs. If the power supply is not capable of sourcing the 50mA that is required under worst case conditions, the voltage supplied to VDD will not increase beyond the POR voltage level and the LMP92066’s POR circuitry remains active and continues to draw excess current. This excess current draw is approximately 20mA under nominal conditions. Since the LMP92066’s POR circuitry also responds to the discharge (falling edge) of the supply line, an increase in supply current occurs when the VDD supply is turned off as well. Similar to the condition described above, if the VDD supply is not capable of sourcing a minimum of 50mA, an increase in VDD supply current can be experienced if the VDD supply is immediately ramped back up after being discharged. Under this circumstance, the increase in VDD supply current will persist until the voltage surpasses 4.2V. This is a result of the POR circuitry never turning off. The POR circuit will only turn off once the VDD supply has passed through the POR voltage level of 4.2V. 10.2 IVDD During EEPROM BURN Figure 51 shows the transient behavior of IVDD due to the EEPROM BURN operation. VSDA trace activity is used as the trigger. The triggering event is the BURN command sent via the I2C interface. During the BURN the IVDD increases to almost 4 mA for 125 ms. The 10-mA peaking in IVDD is due to the TRANSFER of newly stored data from EEPROM back to the operating memory – this is part of the internal error detection and correction process. IVDD VSDA Time (20 ms/DIV) C021 IVDD = 2mA/div VSDA = 5V/div Figure 51. IVDD Transient During EEPROM BURN 10.3 IVDD During EEPROM TRANSFER The transfer of data, from the EEPROM to the operating memory, results in the temporary increase in supply current IVDD. The total IVDD increases to about 10 mA for the duration of the TRANFER operation, typically 200 µs. Given the infrequent occurrence, and the short duration, the increased IVDD can be easily supplied by the external bulk capacitors; that is, this does not represent an additional burden to the system power supply. The typical IVDD transient during TRANSFER is shown in Figure 52. The triggering event is the TRANSFER command issued via the I2C interface. 54 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 IVDD During EEPROM TRANSFER (continued) IVDD VSDA Time (200 µs/DIV) C022 IVDD = 2mA/div VSDA = 5V/div Figure 52. IVDD Transient During EEPROM Transfer The TRANSFER operation occurs due to the following: 1. Power-On RESET 2. Software RESET 3. EEPROM TRANSFER command issued via the I2C interface 4. Upon completion of the EEPROM BURN operation, as a data verification step. 11 Layout 11.1 Layout Guidelines The LMP92066 is a device for which the input signal is temperature. The primary path of heat conduction is through the exposed PowerPAD on the underside of the package. The layout should provide direct, high thermal conductivity path between the LMP92066 and the devices controlled by its output: • Use heavy copper layer as the thermal conduction path. This layer must be also a GND node. • If the heavy copper layer is not a top layer, use a dense array of vias to connect to both the LMP92066 and the heat sources to maintain high thermal conductivity. • Place the LMP92066 in the geometric center between the multiple heat sources in order to minimize the “thermal offsets” due to the temperature gradients. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 55 LMP92066 SNAS634B – MARCH 2014 – REVISED JANUARY 2016 www.ti.com 11.2 Layout Example xxxxxx xxxxxx xx xx xx xx xx xx xxxx xx xxxx xx xx xx xx xxxx xx xxxx D xxx xxxxxxxxxx xxxxxxxxxxxxx xxx xxx xxx G /4 1.8V ± 3.3V Supply 5V Supply OPTIONAL GNDD VDD DRVEN1 VDDB DRVEN0 DAC1 5 VIO FETDRV1 SDA GNDA SCL FETDRV0 A1 DAC0 A0 VSSB 10n 10n 5 I2C bus pull-ups. Location dependent on other slave devices present in the system Details of the RF section are beyond the scope of this document D G Copper Pour /4 50 Power Ground Thermal bridge between LMP92066 and the PAs RF_IN Figure 53. LMP92066 Layout 56 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 LMP92066 www.ti.com SNAS634B – MARCH 2014 – REVISED JANUARY 2016 12 Device and Documentation Support 12.1 Device Support 12.1.1 Device Nomenclature REAOPC Residual Error After One Point Calibration is the error acquired in the Analog Signal Path due to the inaccuracies of the constituent signal processing blocks: DAC, Buffer Amplifier, internal Reference. REAOPC is dominated by the Offset and Gain temperature drifts, since the significant portion of the initial error is eliminated through the One Point Calibration process. The small contribution from the DAC linearity error (INL) is omitted, since it is numerically insignificant. REAOPC can be predicted through the following formulation: REAOPC(T) = A[x(T) - x(TO)]GE(T) + A[GE(T) - GE(TO)]x(TO) + û A= 5 (V) 4096 GE(T) = Gain Error at temperature T û = OE(T) - OE(TO) OE(T) = Offset error at temperature T x(T) = DAC input code at temperature T TO = temperature at which One Point Calibration is performed One Point Calibration One Point Calibration is the process where the output of the LMP92066 is adjusted in the target system to achieve the desired response, at temperature T0. Typically this involves measurement of the overall system output variable; for example, ID of the PA, and modification of the BASE value in the LUT to achieve the desired PA bias current. 12.2 Trademarks PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated device(s). This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: LMP92066 57 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMP92066PWP ACTIVE HTSSOP PWP 16 92 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 LMP920 66PWP LMP92066PWPR ACTIVE HTSSOP PWP 16 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 LMP920 66PWP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of