LMQ66410-Q1, LMQ66420-Q1, LMQ66430-Q1
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
LMQ664x0-Q1 具有集成式 VIN 旁路和 CBOOT 电容器的 36V、1A/2A/3A
超小型同步汽车降压转换器
1 特性
3 说明
• 功能安全型
– 可提供用于功能安全系统设计的文档
• 符合面向汽车应用的 AEC-Q100 标准：
– 温度等级 1：–40°C 至 +125°C，TA
• 进行了优化，可满足低 EMI 要求：
– 有助于符合 CISPR 25 5 类标准
– 集成旁路和启动电容器可降低 EMI
– 双随机展频可降低峰值发射
– 增强型 HotRod™ QFN 封装可更大限度地减少开
关节点振铃
• 在 1 mA 时效率高于 85%
• 专为汽车应用而设计：
– 结温范围：–40°C 至 +150°C
– 关键引脚之间的 NC 引脚可提高可靠性
– 出色的引脚 FMEA
– 支持 42V 的汽车负载突降瞬态
– 可提供 3V 的输入电压用于汽车冷启动
• 微型解决方案尺寸和低组件成本：
– 集成输入旁路电容器和自举电容器，可降低 EMI
– 具有可湿性侧面的 2.6mm x 2.6mm 增强型
HotRod™ QFN 封装
– 内部控制环路补偿
LMQ664x0-Q1 是具有集成旁路和自举电容器的业界超
小型 36V、3A（可提供 2A 和 1A 型号）同步直流/直
流降压转换器，采用增强型 HotRod™ QFN 封装。该
易于使用的转换器支持 2.7V 至 36V 的宽输入电压范围
（启动后或运行后），并支持高达 42V 的瞬态电压。
LMQ664x0-Q1 专为满足常开型汽车应用的低待机功耗
要求而设计。自动模式可在轻负载运行时进行频率折
返，实现 1.5µA 的典型空载电流消耗（输入电压为
13.5V）和高轻负载效率。PWM 和 PFM 模式之间的无
缝转换以及超低的 MOSFET 导通电阻可确保在整个负
载范围内实现出色的效率。控制架构（峰值电流模式）
和功能集经过优化，可实现具有超小输出电容的超小解
决方案尺寸。该器件通过使用双随机展频 (DRSS)、低
EMI 增强型 HotRod ™ QFN 封装和经优化的引脚排
列 ， 可 更 大 限 度 地 减 小 输 入 滤 波 器 尺 寸 。 MODE/
SYNC 引脚可用于设置或同步频率，以避开噪声敏感
频带。关键高电压引脚之间有 NC 引脚，可减少潜在故
障（出色的引脚 FMEA）。LMQ664x0-Q1 的丰富功能
旨在简化各种汽车终端设备的实施。
封装信息
封装 (1)
封装尺寸（标称值）
RxB（VQFN，15）
2.60mm × 2.60mm
器件型号
LMQ66430-Q1
2 应用
LMQ66420-Q1
LMQ66410-Q1
• 高级驾驶辅助系统：雷达 ECU
• 信息娱乐系统与仪表组：音响主机、eCall
• 车身电子装置和照明
(1)
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100
器件信息
96
92
Efficiency (%)
88
84
80
(1)
76
器件型号
额定输出电流 (1)
LMQ66430-Q1
3A
LMQ66420-Q1
2A
LMQ66410-Q1
1A
请参阅器件比较表。
72
68
VIN = 12 V
VIN = 18 V
VIN = 24 V
64
60
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
效率：VOUT = 3.3V（固定值）、2.2MHz
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBV1
LMQ66410-Q1, LMQ66420-Q1, LMQ66430-Q1
www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics.............................................6
7.6 System Characteristics............................................... 8
7.7 Typical Characteristics................................................ 9
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................21
9 Application and Implementation.................................. 27
9.1 Application Information............................................. 27
9.2 Typical Application.................................................... 28
9.3 Best Design Practices...............................................42
9.4 Power Supply Recommendations.............................42
9.5 Layout....................................................................... 42
10 Device and Documentation Support..........................45
10.1 Device Support....................................................... 45
10.2 Documentation Support.......................................... 45
10.3 接收文档更新通知................................................... 45
10.4 支持资源..................................................................45
10.5 Trademarks............................................................. 46
10.6 静电放电警告.......................................................... 46
10.7 术语表..................................................................... 46
11 Mechanical, Packaging, and Orderable
Information.................................................................... 47
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2022) to Revision B (May 2023)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Page
将功能安全要点置于特性 部分的顶部.................................................................................................................1
从 1A 和 2A 选项中删除了“预发布”标签删除了对 RT 型号的引用................................................................. 1
Removed 'LMR' orderables from the Device Comparison Table ....................................................................... 3
Added LMQ66420MA3RXBRQ1 to the Device Comparison Table ................................................................... 3
Added note regarding other device orderable options........................................................................................3
Removed references to RT pin and LMQ variants. Included pin 4 and pin 5 must be floating........................... 4
Included 1-A and 2-A current limit information and 400-kHz and 2.2-MHz fixed frequency specifications as
well as IBIAS specification for 3.3-V fixed and 5-V fixed. .................................................................................. 5
Removed RT pin from the functional block diagram and removed note regarding LMR variants.....................11
Corrected the delay time from when EN goes high to when the part begins to switch from 1 ms to 2.5 ms.... 12
Removed references to LMR variants. ............................................................................................................ 17
Included recommended passive component tables for the 1-A and 2-A variants.............................................28
Corrected typo in stated output voltage from 5-V to 3.3-V................................................................................ 30
Corrected recommended inductor K value from 0.3 to 0.2............................................................................... 31
Removed references to LMR variants. ............................................................................................................ 32
Changes from Revision * (February 2022) to Revision A (December 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
2
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: LMQ66410-Q1 LMQ66420-Q1 LMQ66430-Q1
English Data Sheet: SNVSBV1
LMQ66410-Q1, LMQ66420-Q1, LMQ66430-Q1
www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
5 Device Comparison Table
Orderable Part Number (1) (2)
Output
Current
Output Voltage
External Sync
FSW
Internal
Capacitors
Spread
Spectrum
LMQ66430MC3RXBRQ1
3A
3.3-V Fixed /
Adjustable
Yes
(PFM / FPWM
Selectable)
Fixed
2.2 MHz
Yes
Yes
LMQ66430MC5RXBRQ1(3)
3A
5-V Fixed /
Adjustable
Yes
(PFM / FPWM
Selectable)
Fixed
2.2 MHz
Yes
Yes
LMQ66420MC3RXBRQ1(3)
2A
3.3-V Fixed /
Adjustable
Yes
(PFM / FPWM
Selectable)
Fixed
2.2 MHz
Yes
Yes
LMQ66420MC5RXBRQ1(3)
2A
5-V Fixed /
Adjustable
Yes
(PFM / FPWM
Selectable)
Fixed
2.2 MHz
Yes
Yes
LMQ66420MA3RXBRQ1
2A
3.3-V Fixed /
Adjustable
Yes
(PFM / FPWM
Selectable)
Fixed
400 kHz
Yes
Yes
LMQ66410MC3RXBRQ1(3)
1A
3.3-V Fixed /
Adjustable
Yes
(PFM / FPWM
Selectable)
Fixed
2.2 MHz
Yes
Yes
LMQ66410MC5RXBRQ1
1A
5-V Fixed /
Adjustable
Yes
(PFM / FPWM
Selectable)
Fixed
2.2 MHz
Yes
Yes
(1)
(2)
(3)
For more information on device orderable part numbers, see Device Nomenclature.
For other variant options, please contact TI.
Preview.
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: LMQ66410-Q1 LMQ66420-Q1 LMQ66430-Q1
English Data Sheet: SNVSBV1
LMQ66410-Q1, LMQ66420-Q1, LMQ66430-Q1
www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
6 Pin Configuration and Functions
1
EN
NC
2
VIN
3
NC
4
NC
PG MODE/SYNC
13
14
12
GND/DAP
15
11
VOUT/FB
10
VCC
9
5
6
7
PGND
SW
NC
8
NC
BOOT
图 6-1. RXB 15-Pin (2.6-mm × 2.6-mm) Enhanced HotRod™ QFN Package (Top View)
表 6-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN/UVLO
1
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN. Do not float
this pin.
NC
2
—
No internal connection to device
VIN
3
P
Input supply to regulator. Two 22-nF capacitors are connected in series internally from this pin to
the PGND pin. Additional high-quality bypass capacitor or capacitors can be added directly to this
pin and PGND.
NC
4
—
Middle point of the two internal series bypass capacitors. Leave this pin floating.
NC
5
—
Middle point of the two internal series bypass capacitors. Leave this pin floating.
PGND
6
G
Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces.
SW
7
P
Regulator switch node. Connect to the power inductor.
BOOT
8
P
Bootstrap supply voltage for internal high-side driver. A 0.1-µF capacitor is internally connected
from this pin to the SW pin.
NC
9
—
No internal connection to device
VCC
10
A
Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this
pin to GND.
VOUT/FB
11
A
Fixed output options and adjustable output options are available with the VOUT/FB pin variant.
Connect to the output voltage node for fixed VOUT. See VOUT / FB for Adjustable Output for how to
select feedback resistor divider values. See Device Comparison Table for more details. The FB
function can be used to adjust the output voltage. Connect to tap point of feedback voltage divider.
Do not float this pin.
NC
12
—
No internal connection to device
MODE/SYNC
13
A
This pin allows the user to select between PFM/FPWM mode or to synchornize to an external
clock. See MODE/SYNC variant for more details. Do not float this pin.
PG
14
A
Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. This pin goes low when EN = low. This pin can be
open or grounded when not used.
GND/DAP
15
G
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
connected to GND.
A = Analog, P = Power, G = Ground
4
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: LMQ66410-Q1 LMQ66420-Q1 LMQ66430-Q1
English Data Sheet: SNVSBV1
LMQ66410-Q1, LMQ66420-Q1, LMQ66430-Q1
www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range (1)
PARAMETER
MIN
MAX
UNIT
Voltages
VIN to GND
–0.3
42
V
Voltages
SW to GND
–0.3
VIN + 0.3
V
Voltages
BOOT to SW
–0.3
5.5
V
Voltages
VCC to GND
–0.3
5.5
V
Voltages
VOUT/FB to GND
–0.3
16
V
Voltages
SYNC/MODE or RT to GND
–0.3
5.5
V
Voltages
PG to GND
–0.3
20
V
Voltages
EN to GND
–0.3
42
V
Temperature
TJ, Junction temperature
–40
150
°C
Temperature
Tstg, Storage temperature
–65
150
°C
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002,
HBD ESD Classification Level 2 (1)
±2000
V
Charged-device model (CDM), per AEC
Q100-011 CDM ESD clasiffication Level C4B
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 °C to 150 °C (unless otherwise noted)
VIN
MIN
MAX
UNIT
Input Voltage Range for startup
3.6
36
V
Input Voltage Range after startup
3.0
36
V
VOUT
Output Voltage Range with Adjustable Output Voltage Setup
1
18
V
IOUT
LMQ66430-Q1 Continuous DC Output Current Range
0
3
A
IOUT
LMQ66420-Q1 Continuous DC Output Current Range
0
2
A
IOUT
LMQ66410-Q1 Continuous DC Output Current Range
TJ
Operating junction temperature
Copyright © 2023 Texas Instruments Incorporated
0
1
A
-40
150
°C
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Product Folder Links: LMQ66410-Q1 LMQ66420-Q1 LMQ66430-Q1
English Data Sheet: SNVSBV1
LMQ66410-Q1, LMQ66420-Q1, LMQ66430-Q1
www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
7.4 Thermal Information
The value of RθJA in this table is only valid for comparison with other packages. These values were calculated in accordance
with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the performance obtained in an actual
application. For example, a 4-layer PCB can achieve a RθJA= 50℃/W.
LMQ664x0-Q1
THERMAL METRIC (1)
UNIT
VQFN
15 PINS
RθJA
Junction-to-ambient thermal resistance for LMQ66430-2EVM
45
°C/W
RθJA
Junction-to-ambient thermal resistance
66.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.6
°C/W
RθJB
Junction-to-board thermal resistance
26.2
°C/W
ψJT
Junction-to-top characterization parameter
3.3
°C/W
ψJB
Junction-to-board characterization parameter
25.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise noted.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5V, VOUT = 3.3V.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VINMIN
Input voltage rising threshold for startup
Before startup
Input voltage falling threshold
Once operating
ISD(VIN)
Shutdown quiescent current at VIN pin
EN = 0 V
IBIAS
Non-switching input current at VOUT/FB
IBIAS
Non-switching input current at VOUT/FB
IQVIN(nonsw)
IQVIN(nonsw)
3.2 3.35
2.45
3.5
V
2.7
3
V
0.25
1
µA
Fixed 5.0-V Vout, VVOUT/FB = 5.25 V
4.2
6.5
µA
Fixed 3.3-Vout, VVOUT/FB = 3.47 V
4.2
6.5
µA
Non-switching input current; measured at VIN
pin (1)
Fixed 5-V VOUT, VVOUT/FB = 5.25 V
1.6
3
µA
Non-switching input current; measured at VIN
pin (1)
Fixed 3.3-V VOUT, VVOUT/FB = 3.47 V
1.2
2.2
µA
ENABLE (EN PIN)
VEN-WAKE
EN wakeup threshold
VEN-VOUT
Precision enable rising threshold for VOUT
VEN-HYST
Enable hysteresis below VEN-VOUT
ILKG-EN
Enable pin input leakage current
0.7
1
V
1.16 1.23
0.5
1.3
V
0.3 0.35
0.4
VEN = VIN = 13.5 V
V
10
nA
3.1
3.3 3.45
V
3.3-V VOUT, VIN = 3.6 V to 36 V, FPWM Mode
3.27
3.3 3.32
V
INTERNAL LDO (VCC PIN)
VCC
VCC pin output voltage
VFB = 0 V, IVCC = 1 mA
VOLTAGE FEEDBACK (VOUT/FB PIN)
VOUT
Output voltage accuracy for fixed VOUT
5-V VOUT, VIN = 5.5 V to 36 V, FPWM Mode
4.94 5.00 5.06
V
VFB
Internal reference voltage accuracy
VOUT = 1 V, VIN = 3.0 V to 36 V, FPWM Mode
0.99 1.00 1.01
V
IFB(LKG)
FB input current
Adjustable configuration, FB = 1 V
10
nA
CURRENT LIMITS
IPEAKMAX
High-side peak current limit
LMQ66430-Q1
3.9
4.4
5
A
IVALMAX
Low-side valley current limit
LMQ66430-Q1
2.9
3.5
4
A
IPEAKMIN
Minimum peak current limit
LMQ66430-Q1, Auto Mode
0.55 0.69 0.86
A
–
1.3
A
INEGMIN
6
Low-side valley current negative limit
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LMQ66430-Q1, FPWM Mode
–1.5
–1
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: LMQ66410-Q1 LMQ66420-Q1 LMQ66430-Q1
English Data Sheet: SNVSBV1
LMQ66410-Q1, LMQ66420-Q1, LMQ66430-Q1
www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
7.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise noted.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5V, VOUT = 3.3V.
PARAMETER
TEST CONDITIONS
IPEAKMAX
High-side peak current limit
LMQ66420-Q1
IVALMAX
Low-side valley current limit
LMQ66420-Q1
IPEAKMIN
Minimum peak current limit
LMQ66420-Q1, Auto Mode
INEGMIN
Negative current limit
LMQ66420-Q1, FPWM Mode
IPEAKMAX
High-side peak current limit
IVALMAX
Low-side valley current limit
IPEAKMIN
Minimum peak current limit
LMQ66410-Q1, Auto Mode
MIN TYP MAX UNIT
2.8
3.4
3.9
A
1.9
2.2 2.53
A
0.37
0.5 0.65
A
–1
–
0.8
–
0.6
A
LMQ66410-Q1
1.4
1.8
2.1
A
LMQ66410-Q1
0.9
1.1
1.4
A
0.17 0.27 0.35
A
–1
–
0.8
–
0.6
A
30
80
135 mA
108
INEGMIN
Low-side valley current negative limit
LMQ66410-Q1, FPWM Mode
IZC
Zero-cross current limit
Auto Mode
POWER GOOD (PG PIN)
PGOV
PG upper threshold - rising
% of VOUT/FB (Fixed or Adj. output)
104
PGUV
PG upper threshold - falling
% of VOUT/FB (Fixed or Adj. output)
89
PG recovery hysteresis for OV
% of VOUT/FB target regulation voltage
2
2
3.3
PGHYST
111
%
91 94.2
%
2.4
2.8
%
PG recovery hysteresis for UV
% of VOUT/FB target regulation voltage
4.6
%
VPG-VAL
Minimum VIN for PG function
VEN = 0 V, RPG_PU = 10 kΩ
1.5
V
RPG
PG ON resistance
VEN = 3.3 V, 200 µA pull up current
100
Ω
RPG
PG ON resistance
VEN = 0 V, 200 µA pull up current
100
Ω
tRESET_FILTER PG deglitch delay at falling edge
tPG_ACT
Delay time to PG high signal
25
40
75
µs
1.35
2.5
4
ms
2
3.5
4.6
ms
30
50
75
ms
SOFT START
tSS
Time from first SW pulse to VOUT/FB at 90% of
set point
tHICCUP
Time in hiccup before retry soft start
OSCILLATOR (SYNC/MODE PIN)
tPULSE_H
High duration needed to be recognized as a
pulse
100
ns
tPULSE_L
Low duration needed to be recognized as a
pulse
100
ns
tSYNC
High/Low level pulse maximum duration to be
recognized as a valid clock signal
tMODE
Time at one level needed to indicate FPWM or
Auto Mode
FSW(400kHz)
Switching Frequency with fixed 400 kHz
FSW(2.2MHz)
Switching Frequency with fixed 2.2 MHz
fSYNC
Frequency SYNC range
VMODE_L
SYNC/MODE input voltage low level threshold
VMODE_H
SYNC/MODE input voltage high level threshold
6
12.5
340
µs
µs
400
460 kHz
2100 2200 2300 kHz
0.2
2.5 MHz
1
1.6
V
V
SWITCH NODE
tON-MIN
Minimum HS switch on-time
tOFF-MIN
Minimum HS switch off-time
tON-MAX
Maximum HS switch on-time
FPWM mode IOUT = 1 A, 2.2 MHz fixed
HS timeout in dropout
Copyright © 2023 Texas Instruments Incorporated
6
65
75
60
85
ns
9
13
µs
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ns
7
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7.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature range of -40°C to +150°C, unless otherwise noted.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 13.5V, VOUT = 3.3V.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
POWER STAGE
VBOOT_UVLO
Voltage on BOOT pin compared to SW which
will turnoff high-side switch
RDSON-HS
High-side MOSFET on-resistance
Load = 1 A
132
260 mΩ
RDSON-LS
Low-side MOSFET on-resistance
Load = 1 A
75
140 mΩ
(1)
2.1
V
This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
7.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the
case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SUPPLY CURRENT
IQVIN
VIN = 13.5 V, Fixed 3.3-V VOUT, IOUT = 0 A, Auto mode
1.5
µA
2
µA
VOUT = 3.3-V, fixed 2.2 MHz, IOUT = 1 A
0.2
V
VOUT = 5-V, fixed 2.2 MHz, IOUT = 1 A
0.2
V
Input to output voltage differential to
maintain VOUT regulation ≥ 95% and VOUT = 3.3-V, fixed 2.2 MHz, IOUT = 1 A
FSW ≥1.85 MHz
0.7
V
Input to output voltage differential to
maintain VOUT regulation ≥ 95% and VOUT = 5-V, fixed 2.2 MHz trim, IOUT = 1 A
FSW ≥ 1.85 MHz
0.9
V
While in frequency fold-back
98
%
FSW = 1.85 MHz, VOUT = 5.0-V, IOUT = 1 A
87
%
5
KΩ
Input current to VIN
VIN = 13.5 V, Fixed 5-V VOUT, IOUT = 0 A, Auto mode
POWER STAGE
VDROP1
VDROP2
Input to output voltage differential to
maintain VOUT regulation ≥ 95%,
with frequency foldback
DMAX
Maximum switch duty cycle
RFBPARA(min)
Minimum value of parallel FB
resistor : RFBT parallel RFBB
PROTECTION
8
TSD(trip)
Thermal shutdown threshold
TSD(hyst)
Thermal shutdown hysteresis
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Temperature rising
158
168
186
°C
15
20
°C
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7.7 Typical Characteristics
Unless otherwise specified, the following conditions apply: TA = 25°C, VIN = 13.5 V
0.7
2
Non-Switching Input Current (µA)
VIN = 13.5V
VIN = 24V
Shutdown Current (µA)
0.6
0.5
0.4
0.3
0.2
-40
-10
20
50
80
Temperature (°C)
110
1.8
1.6
1.4
1.2
1
-40
140
-10
VOUT = 3.3 V fixed
110
140
图 7-2. Nonswitching Input Current (IQVIN(nonsw))
Versus Temperature
3.3
Voltage Reference Voltage (V)
1
3.298
Output Voltage (V)
50
80
Temperature (°C)
VOUT = 3.3 V fixed
图 7-1. Shutdown Current Versus Temperature
3.296
3.294
3.292
3.29
-40
20
-10
20
50
80
Temperature (°C)
110
VOUT = 3.3 V fixed
图 7-3. Output Voltage Accuracy Versus
Temperature
140
0.9995
0.999
0.9985
0.998
0.9975
-40
-10
20
50
80
Temperature (°C)
110
140
VOUT = adjustable
图 7-4. Feedback Voltage Accuracy Versus
Temperature
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8 Detailed Description
8.1 Overview
The LMQ664x0-Q1 is a wide input, low-quiescent current, high-performance regulator that can operate over a
wide range of duty ratio and the switching frequencies, including sub-AM band at 400 kHz and above AM band
at 2.2 MHz. During wide input transients, if the minimum on time or the minimum off time cannot support the
desired duty ratio at the higher switching frequency settings, the switching frequency is reduced automatically,
allowing the device to maintain the output voltage regulation. With an internally compensated design optimized
for minimal output capacitors, the system design process with the device is simplified significantly compared to
other buck regulators available in the market.
The device is designed to minimize external component cost and solution size while operating in all demanding
automotive environments. To further reduce system cost, the PG output feature with built-in delayed release
allows the elimination of the reset supervisor in many applications.
The LMQ664x0-Q1 family is designed to reduce EMI/EMC emissions by introducing a dual random spread
spectrum (DRSS) switching frequency dithering scheme, using the enhanced HotRod™ QFN package where no
bond wires are used and integrates the high-frequency VIN bypass capacitors including, a CBOOT capacitor,
inside the package. Also, available is the MODE/SYNC feature that allows synchronization to an external clock.
Together, these features reduce the need for any common-mode choke or shielding or any elaborate input filter
design scheme, greatly reducing the complexity and cost of the EMI/EMC mitigation measures.
The device comes in an ultra-small 2.6-mm × 2.6-mm enhanced HotRod™ QFN package with wettable flanks,
allowing for quick optical inspection along with specially designed corner anchor pins for reliable board level
solder connections.
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8.2 Functional Block Diagram
VCC
MODE
/SYNC
CLOCK
VOUT
OSCILLATOR
SLOPE
COMPENSATION
FIXED
OUTPUT
VOLTAGE
LDO
VCC UVLO
VIN
THERMAL
SHUTDOWN
FSW FOLDBACK
TSD
BOOT
SYS ENABLE
ENABLE
EN
VIN
HS
CURRENT
SENSE
ADJ. OUTPUT
VOLTAGE
ERROR
AMPLIFIER
–
VOUT/
FB
+
+
–
COMP
MAX. and
MIN.
LIMITS
+
TSD
CLOCK
+
FIXED OUTPUT
VOLTAGE
HS
CURRENT
LMIT
SYS ENABLE
SOFTSTART
and
BANDGAP
TSD
GND
VREF
VCC UVLO
–
SW
SYS ENABLE
CONTROL
LOGIC and
DRIVER
LS
CURRENT
LMIT
–
+
ADJ. OUTPUT
VOLTAGE
FIXED OUTPUT
VOLTAGE
MIN.
LS CURRENT
LIMIT
VOUT
FB
–
PGND
+
PG
FPWM or AUTO
PGOOD
LOGIC
VOUT UV/OV
VOUT UV/OV
LS
CURRENT
SENSE
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8.3 Feature Description
8.3.1 Enable, Start-Up, and Shutdown
Voltage at the EN pin controls the start-up or remote shutdown of the LMQ664x0-Q1 family of devices. The part
stays shut down as long as the EN pin voltage is less than VEN-WAKE = 0.7 V (typical). During the shutdown, the
input current drawn by the device typically drops down to 0.25 µA (VIN = 13.5 V). With the voltage at the EN pin
greater than VEN-WAKE, the device enters device standby mode and the internal LDO powers up to generate
VCC. As the EN voltage increases further, approaching VEN-VOUT, the device finally starts to switch, entering
start-up mode with a soft start. During the device shutdown process, when the EN input voltage measures less
than (VEN-VOUT – VEN-HYST), the regulator stops switching and re-enters device standby mode. Any further
decrease in the EN pin voltage, below VEN-WAKE, and the device is then firmly shut down. The high-voltage
compliant EN input pin can be connected directly to the VIN input pin if remote precision control is not needed.
The EN input pin must not be allowed to float. The various EN threshold parameters and their values are listed in
the Electrical Characteristics. 图 8-2 shows the precision enable behavior and 图 8-3 shows a typical remote EN
start-up waveform in an application. After EN goes high, after a delay of about 2.5 ms, the output voltage begins
to rise with a soft start and reaches close to the final value in about 3.5 ms (tss). After a delay of about 2.5 ms
(tPG_ACT), the PG flag goes high. During start-up, the device is not allowed to enter FPWM mode until the softstart time has elapsed. This time is measured from the rising edge of EN. Check 节 9.2.1.2.9 for component
selection.
VIN
RENT
EN
RENB
AGND
图 8-1. VIN UVLO Using the EN Pin
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EN
VEN-VOUT
VEN-HYST
VEN-WAKE
VCC
3.3V
0
VOUT
VOUT
0
图 8-2. Precision Enable Behavior
VOUT (2V/DIV)
PGOOD (5V/DIV)
EN (5V/DIV)
IL (1A/DIV)
2 ms/DIV
图 8-3. Enable Start-Up VIN = 24 V, VOUT = 3.3 V, IOUT = 2 A
8.3.2 External CLK SYNC (with MODE/SYNC)
Synchronized operation of multiple regulators in a single system is often desirable for a well-defined system level
performance. The select variants in the device with the MODE/SYNC pin allow the power designer to
synchronize the device to a common external clock. The device implements an in-phase locking scheme, where
the rising edge of the clock signal, provided to the MODE/SYNC pin of the device, corresponds to the turning on
of the high-side device. The external clock synchronization is implemented using a phase locked loop (PLL),
eliminating any large glitches. The external clock fed into the device replaces the internal free-running clock, but
does not affect any frequency foldback operation. Output voltage continues to be well regulated. The device
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remains in FPWM mode and operates in CCM for light loads when synchronization input is provided. The range
of frequencies permitted by the device is given by fSYNC and is provided in the Electrical Characteristics.
14
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The MODE/SYNC input pin in the device can operate in one of three selectable modes:
• Auto mode: Pulse frequency modulation (PFM) operation is enabled during light load and diode emulation
prevents reverse current through the inductor. See 节 8.4.3.2 for more details.
• FPWM mode: In FPWM mode, diode emulation is disabled, allowing current to flow backwards through the
inductor. This allows operation at full frequency even without load current. See 节 8.4.3.3 for more details.
• SYNC mode: The internal clock locks to an external signal applied to the MODE/SYNC pin. As long as output
voltage can be regulated at full frequency and is not limited by minimum off time or minimum on time, clock
frequency is matched to the frequency of the signal applied to the MODE/SYNC pin. While the device is in
SYNC mode, it operates as though in FPWM mode: diode emulation is disabled, allowing the frequency
applied to the MODE/SYNC pin to be matched without a load.
8.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
Most systems that require more than a single mode of operation from the device are controlled by digital circuitry
such as a microprocessor. These systems can generate dynamic signals easily but have difficulty generating
multi-level signals. Pulse-dependent MODE/SYNC pin control is useful with these systems. To initiate pulsedependent MODE/SYNC pin control, a valid sync signal must be applied. 表 8-1 shows a summary of the pulse
dependent mode selection settings.
表 8-1. Pulse-Dependent Mode Selection Settings
Mode/Sync Input
Mode
> VMODE_H
FPWM with spread spectrum factory setting
< VMODE_L
Auto mode with spread spectrum factory setting
Synchronization Clock
SYNC mode
图 8-4 shows the transition between auto mode and FPWM mode while in pulse-dependent MODE/SYNC
control. The device transitions to a new mode of operation after the time, tMODE. 图 8-4 and 图 8-5 show the
details.
Transition to new mode of operation
starts, spread spectrum turns on
> tMODE
FPWM Mode
VMODE_H
VMODE_L
Auto Mode
图 8-4. Transition from Auto Mode and FPWM Mode
If MODE/SYNC voltage remains constant longer than tMODE, the device enters either auto mode or FPWM mode
with spread spectrum turned on (if factory setting is enabled) and MODE/SYNC continues to operate in pulsedependent scheme.
tMODE
Now Auto Mode, Spread Spectrum on
VMODE_H
VMODE_L
> tPULSE_L
> tPULSE_H
< tSYNC
图 8-5. Transition from SYNC Mode to Auto Mode
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tMODE
< tSYNC
Now FPWM Mode, Spread Spectrum on
VMODE_H
VMODE_L
> tPULSE_L
> tPULSE_H
> tPULSE_L
< tSYNC
图 8-6. Transition from SYNC Mode to FPWM Mode
8.3.3 Power-Good Output Operation
The power-good feature using the PG pin of the device can be used to reset a system microprocessor whenever
the output voltage is out of regulation. This open-drain output remains low under device fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for any short duration excursions in the output voltage, such as during line and load transients. Output voltage
excursions lasting less than tRESET_FILTER do not trip the power-good flag. Power-good operation can best be
understood in reference to 图 8-7. 表 8-2 gives a more detailed breakdown of the PG operation. Here, VPGUV is
defined as the PGUV scaled version of VOUT (target regulated output voltage) and VPGHYST as the PGHYST scaled
version of VOUT, where both PGUV and PGHYST are listed in the Electrical Characteristics. During the initial power
up, a total delay of 8.5 ms (typical) is encountered from the time VEN-VOUT is triggered to the time that the power
good is flagged high. This delay only occurs during the device start-up and is not encountered during any other
normal operation of the power-good function. When EN is pulled low, the power-good flag output is also forced
low. With EN low, power good remains valid as long as the input voltage, VPG-VAL, is greater 1.5 V (maximum).
The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup
resistor connected to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an
appropriate resistor, as desired. If this function is not needed, the PG pin can be open or grounded. Limit the
current into this pin to ≤ 4 mA.
Input
Voltage
Output
Voltage
tRESET_FILTER
tPG_ACT
tPG_ACT
VPG-HYST
Input Voltage
tRESET_FILTER
tRESET_FILTER
tRESET_FILTER
VPG-UV (falling)
VINMIN (rising)
VINMIN (falling)
VPG_VAL
GND
VOUT
PG
PG may not
be valid if
input is below
VPG-VAL
Small glitches
do not cause
reset to signal
a fault
Small glitches do not
reset tPG_ACT timer
Startup
delay
PG may not be
valid if input is
below VPG-VAL
图 8-7. Power-Good Operation (OV Events Not Included)
表 8-2. Fault Conditions for PG (Pull Low)
16
Fault Condition Initiated
Fault Condition Ends (After Which tPG_ACT Must Pass Before PG
Output Is Released)
VOUT < VPGUV AND t > tRESET_FILTER
Output voltage in regulation:
VPGUV + VPGHYST < VOUT < VPGOV - VPGHYST
VOUT > VPGOV AND t > tRESET_FILTER
Output voltage in regulation
TJ > TSD(trip)
TJ < TSD(trip) - TSD(hyst) AND output voltage in regulation
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表 8-2. Fault Conditions for PG (Pull Low) (continued)
Fault Condition Initiated
Fault Condition Ends (After Which tPG_ACT Must Pass Before PG
Output Is Released)
EN < VEN-VOUT – VEN-HYST
EN > VEN-VOUT AND output voltage in regulation
8.3.4 Internal LDO, VCC, and VOUT/FB Input
The device uses the internal LDO output and the VCC pin for all internal power supply. The VCC pin draws
power either from the VIN (in adjustable output variants) or VOUT/FB (in fixed-output variants). In the fixedoutput variants, after the device is active but has yet to regulate, the VCC rail continues to draw power from the
input voltage, VIN, until the VOUT/FB voltage reaches > 3.15 V (or when the device has reached steady-state
regulation post the soft start). The VCC rail typically measures 3.3 V in both adjustable and fixed output variants.
During start-up, VCC momentarily exceeds the normal operating voltage and then drops to the normal operating
voltage.
8.3.5 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
The high-side switch driver circuit requires a bias voltage higher than VIN to make sure the HS switch is turned
on. The internal 0.1-μF capacitor that is connected between BOOT and SW works as a charge pump to boost
voltage on the BOOT terminal to (SW + VCC). The boot diode is integrated on the device die to minimize
physical solution size. The CBOOT rail has a UVLO setting. This UVLO has a threshold of VBOOT-UVLO and is
typically set at 2.1 V. If the BOOT capacitor is not charged above this voltage with respect to the SW pin, then
the part initiates a charging sequence, turning on the low-side switch before attempting to turn on the high-side
device.
8.3.6 Output Voltage Selection
In the device family, an adjustable output or fixed output voltage option is configurable for every device variant
(see 节 5). For an adjustable output, the user needs an external resistor divider connection between the output
voltage node, the device FB pin, and the system GND, as shown in 图 8-8. The adjustable output voltage
operation uses a 1-V internal reference voltage. Refer to 节 9.2.1.2.2.1 for more details on how to adjust the
output voltage.
When using the fixed-output configuration from the device family, simply connect the FB pin (identified as
VOUT/FB pin for fixed-output variants in the rest of the data sheet) to the system output voltage node. See 节 5
for more details.
VOUT
RFBT
FB
RFBB
AGND
图 8-8. Setting Output Voltage for Adjustable Output Variant
In adjustable output voltage variants, an additional feedforward capacitor, CFF, in parallel with the RFBT, can be
used to optimize the phase margin and transient response. See 节 9.2.1.2.8 for more details. No additional
resistor divider or feedforward capacitor is needed in fixed-output variants.
8.3.7 Spread Spectrum
In the LMQ664x0-Q1 family of devices, spread spectrum is a factory option. To find which parts have spread
spectrum enabled, see 节 5.
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Spread spectrum reduces peak emissions at specific frequencies by spreading these peaks across a wider
range of frequencies than a part with fixed-frequency operation. The LMQ664x0-Q1 implements a modulation
pattern designed to reduce low frequency-conducted emissions from the first few harmonics of the switching
frequency. The pattern can also help reduce the higher harmonics that are more difficult to filter, which can fall in
the FM band. These harmonics often couple to the environment through electric fields around the switch node
and inductor. The LMQ664x0-Q1 uses a spread of frequencies, which can spread energy smoothly across the
FM and TV bands. The device implements dual random spread spectrum (DRSS). DRSS is a combination of a
triangular frequency spreading pattern and pseudorandom frequency hopping. The combination allows the
spread spectrum to be very effective at spreading the energy at the following:
• Fundamental switching harmonic with slow triangular pattern
• High frequency harmonics with additional pseudo-random jumps at the switching frequency
The advantage of DRSS is its equivalent harmonic attenuation in the upper frequencies with a smaller
fundamental frequency deviation. This reduces the amount of input current and output voltage ripple that is
introduced at the modulating frequency. Additionally, the LMQ664x0-Q1 also allows the user to further reduce
the output voltage ripple caused by the spread spectrum modulating pattern.
The spread spectrum is only available while the clock of the device is free running at its natural frequency. Any of
the following conditions overrides spread spectrum, turning it off:
• The clock is slowed due to operation at low-input voltage – this is operation in dropout.
• The clock is slowed under light load in auto mode. Note that if you are operating in FPWM mode, spread
spectrum can be active, even if there is no load.
• The clock is slowed due to high input to output voltage ratio. This mode of operation is expected if on time
reaches minimum on time. See the Electrical Characteristics.
• The clock is synchronized with an external clock.
8.3.8 Soft Start and Recovery from Dropout
When designing with the LMQ664x0-Q1, slow rise in output voltage due to recovery from dropout and soft start
must be considered as two separate operating conditions, as shown in 图 8-9 and 图 8-10. Soft start is triggered
by any of the following conditions:
• Power is applied to the VIN pin of the device, releasing undervoltage lockout.
• EN is used to turn on the device.
• Recovery from shutdown due to overtemperature protection
After soft start is triggered, the IC takes the following actions:
• The reference used by the IC to regulate output voltage is slowly ramped up. The net result is that output
voltage, if previously 0 V, takes tSS to reach 90% of the desired value.
• Operating mode is set to auto mode of operation, activating the diode emulation mode for the low-side
MOSFET. This allows start-up without pulling the output low. This is true even when there is a voltage already
present at the output during a pre-bias start-up.
EN and Output Voltages
tEN
V
tSS
VOUT Set
Point
If selected, FPWM
is enabled only
after completion of
tSS
VEN
VOUT
90% of
VOUT Set
Point
0V
Time
t
Triggering event
tEN
EN and Output Voltages
Triggering event
V
tSS
If selected, FPWM
is enabled only
after completion of
tSS
VEN
VOUT Set
Point
VOUT
90% of
VOUT Set
Point
0V
Time
t
图 8-9. Soft Start with and Without Pre-bias Voltage
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8.3.8.1 Recovery from Dropout
Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called
graceful recovery from dropout in this document, differs from soft start in two important ways:
• The reference voltage is set to approximately 1% above what is needed to achieve the existing output
voltage.
• If the device is set to FPWM, it continues to operate in that mode during its recovery from dropout. If output
voltage were to suddenly be pulled up by an external supply, the LMQ664x0-Q1 can pull down on the output.
Note that all protections that are present during normal operation are in place, preventing any catastrophic
failure if output is shorted to a high voltage or ground.
Output Voltage
and Current
V
VIN (2V/DIV)
8V
Load
current
4V
VOUT Set
Point
and max
output
current
VOUT
VOUT (2V/DIV)
5V
Slope
the same
as during
soft start
Load Current (0.2A/DIV)
t
Time
500µs/DIV
图 8-10. Recovery from Dropout
图 8-11. Typical Output Recovery from
Dropout from 8 V to 4 V
Whether output voltage falls due to high load or low input voltage, after the condition that causes output to fall
below its set point is removed, the output climbs at the same speed as during start-up. 图 8-11 shows an
example of this behavior.
8.3.9 Current Limit and Short Circuit
The device is protected from over current conditions by cycle-by-cycle current limiting on both high-side and lowside MOSFETs. High-side MOSFET over current protection is implemented by the typical peak-current mode
control scheme. The HS switch current is sensed when the HS is turned on after a short blanking time. The HS
switch current is compared to either the minimum of a fixed current set point or the output of the internal error
amplifier loop minus the slope compensation every switching cycle. Because the output of the internal error
amplifier loop has a maximum value and slope compensation increases with duty cycle, HS current limit
decreases with increased duty factor if duty factor is typically above 35%.
When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side
device, the low-side device has a turn-off commanded by the internal error amplifier loop. In the case of the lowside device, turn-off is prevented if the current exceeds this value, even if the oscillator normally starts a new
switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be.
This is called the low-side current limit, IVALMAX in 图 8-12. If the LS current limit is exceeded, the LS MOSFET
stays on and the HS switch is not to be turned on. The LS switch is turned off after the LS current falls below this
limit and the HS switch is turned on again as long as at least one clock period has passed since the last time the
HS device has turned on.
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VSW
SW Voltage
VIN
tON < tON_MAX
0
t
Inductor Current
Typically, tSW > Clock setting
iL
IPEAKMAX
IOUT
IVALMAX
t
0
图 8-12. Current Limit Waveforms
Because the current waveform assumes values between IPEAKMAX and IVALMAX, the maximum output current is
very close to the average of these two values unless duty factor is very high. After operating in current limit,
hysteretic control is used and current does not increase as output voltage approaches zero.
The LMQ664x0-Q1 employs hiccup over current protection if there is an extreme overload, and the following
conditions are met:
• Output voltage is below approximately 0.4 times the output voltage set point.
• Greater than tSS has passed since soft start has started.
• The part is not operating in dropout, which is defined as having a minimum off time controlled duty cycle.
In hiccup mode, the device shuts itself down and attempts to soft start after tHICCUP. Hiccup mode helps reduce
the device power dissipation under severe over current conditions and short circuits. See 图 8-13.
After the overload is removed, the device recovers as though in soft start; see 图 8-14.
VOUT (2 V/DIV)
VOUT (2 V/DIV)
IOUT (2 A/DIV)
IOUT (2 A/DIV)
20 ms/DIV
图 8-13. Hiccup Entry
20 ms/DIV
图 8-14. Hiccup Exit
8.3.10 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction
temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal
shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to
approximately 153°C (typical). When the junction temperature falls below 153°C (typical), the device attempts
another soft start.
While the device is shut down due to high junction temperature, power continues to be provided to VCC. To
prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced
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current limit while the part is disabled due to high junction temperature. The LDO only provides a few
milliamperes during thermal shutdown.
8.3.11 Input Supply Current
The device is designed to have very low input supply current when regulating light loads. This is achieved by
powering much of the internal circuitry from the output. The VOUT/FB pin in the fixed-output voltage variants is
the input to the LDO that powers the majority of the control circuits. By connecting the VOUT/FB input pin to the
output node of the regulator, a small amount of current is drawn from the output. This current is reduced at the
input by the ratio of VOUT / VIN.
IQ_VIN = IQ + IEN + IBIAS
VOUT
¾eff x VIN
(1)
where
• IQVIN is the total standby (switching) current consumed by the operating (switching) buck converter when
unloaded.
• IQ is the current drawn from the VIN terminal.
• IEN is current drawn by the EN terminal. Include this current if EN is connected to VIN. Check ILKG-EN in the
Electrical Characteristics for IEN.
• IBIAS is bias current drawn by the BIAS LDO.
• ηeff is the light-load efficiency of the buck converter with IQ_VIN removed from the input current of the buck
converter. ηeff = 0.8 is a conservative value that can be used under normal operating conditions. This can be
traced back as the ISUPPLY in the System Characteristics.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.4 V, both
the converter and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode,
the quiescent current drops to typically 250 nA.
8.4.2 Standby Mode
The internal LDO has a lower EN threshold than the output of the converter. When the EN pin voltage is above 1
V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the
VCC voltage at 3.3 V typical. The precision enable circuitry is ON after VCC is above its UVLO. The internal
power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable
threshold. The device also employs UVLO protection. If the VCC voltage is below its UVLO level, the output of
the converter is turned off.
8.4.3 Active Mode
The device is in active mode whenever the EN pin is above VEN-VOUT, VIN is high enough to satisfy VINMIN, and
no other fault conditions are present. The simplest way to enable the operation is to connect the EN pin to VIN,
which allows the device to start up when the applied input voltage exceeds the minimum VINMIN.
In active mode, depending on the load current, input voltage, and output voltage, the device is in one of five
modes:
• Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
inductor current ripple
• Auto mode – light load operation: PFM when switching frequency is decreased at very light load
• FPWM mode – light load operation: Discontinuous conduction mode (DCM) when the load current is lower
than half of the inductor current ripple
• Minimum on time: At high input voltage and low output voltages, the switching frequency is reduced to
maintain regulation.
• Dropout mode: When switching frequency is reduced to minimize voltage dropout
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8.4.3.1 CCM Mode
The following operating description of the device refers to 节 8.2 and to the waveforms in 图 8-15. In CCM, the
device supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) switches
with varying duty cycle (D). During the HS switch on time, the SW pin voltage, VSW, swings up to approximately
VIN, and the inductor current, iL, increases with a linear slope. The HS switch is turned off by the control logic.
During the HS switch off time, tOFF, the LS switch is turned on. Inductor current discharges through the LS
switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. The converter
loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on time of the HS switch
over the switching period:
D = TON / TSW
(2)
In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage:
D = VOUT / VIN
(3)
SW Voltage
VSW
D=
VIN
tON
VOUT
≈
tSW
VIN
tOFF
tON
0
- IOUTRDSON-LS
t
tSW
Inductor Current
iL
IPEAK
IOUT
0
Iripple
t
图 8-15. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
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8.4.3.2 Auto Mode – Light Load Operation
The LMQ664x0-Q1 can have two behaviors while lightly loaded. One behavior, called auto mode operation,
allows for seamless transition between normal current mode operation while heavily loaded and highly efficient
light load operation. Note that for output voltages between 1-V and 2-V multi-pulsing behavior can be observed
on the switch node waveform when the device transitions from PFM to PWM mode. The other behavior, called
FPWM mode, maintains full frequency even when unloaded. Which mode the device operates in depends on
which variant from this family is selected. Note that all parts operate in FPWM mode when synchronizing
frequency to an external signal.
The light load operation is employed in the device only in auto mode. The light load operation employs two
techniques to improve efficiency:
• Diode emulation, which allows DCM operation. See 图 8-16.
• Frequency reduction. See 图 8-16.
Note that while these two features operate together to improve light load efficiency, they operate independently.
8.4.3.2.1 Diode Emulation
Diode emulation prevents reverse current through the inductor, which requires a lower frequency needed to
regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.
With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to
maintain regulation.
VSW
tON
VOUT
<
tSW
VIN
D=
SW Voltage
VIN
tON
tOFF
tHIGHZ
0
t
tSW
Inductor Current
iL
IPEAK
IOUT
0
t
In auto mode, the low-side device is turned off after SW node current is near zero. As a result, after output current is less than half of
what inductor ripple can be in CCM, the part operates in DCM, which is equivalent to the statement that diode emulation is active.
图 8-16. PFM Operation
The device has a minimum peak inductor current setting (see IPEAKMIN in the Electrical Characteristics) while in
auto mode. After current is reduced to a low value with fixed input voltage, on time is constant. Regulation is
then achieved by adjusting frequency. This mode of operation is called PFM mode regulation.
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8.4.3.2.2 Frequency Reduction
The device reduces frequency whenever output voltage is high. This function is enabled whenever the internal
error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the
regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance
while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when
the part is completely unloaded.
Output Voltage
VOUT
Current
Limit
1% Above
Set point
VOUT Set
Point
Output Current
0
IOUT
In auto mode, after output current drops below approximately 1/10th the rated current of the part, output resistance increases so that
output voltage is 1% high while the buck is completely unloaded.
图 8-17. Steady State Output Voltage Versus Output Current in Auto Mode
In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a
dummy load at VOUT or FPWM mode can be used to reduce or eliminate this offset.
8.4.3.3 FPWM Mode – Light Load Operation
In FPWM mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is
allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see the Electrical
Characteristics for reverse current limit values.
VSW
D=
tON
VOUT
≈
tSW
VIN
SW Voltage
VIN
tOFF
tON
t
0
Inductor Current
tSW
iL
IPEAK
IOUT
0
Iripple
t
In FPWM mode, continuous conduction (CCM) is possible even if IOUT is less than half of Iripple.
图 8-18. FPWM Mode Operation
For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to
command minimum on time even while lightly loaded, allowing good behavior during faults that involve output
being pulled up.
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8.4.3.4 Minimum On-Time (High Input Voltage) Operation
The device continues to regulate output voltage even if the input-to-output voltage ratio requires an on time less
than the minimum on time of the chip with a given clock setting. This is accomplished by using valley current
control. At all times, the compensation circuit dictates both a maximum peak inductor current and a maximum
valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until valley
current falls below that determined by the compensation circuit. If the converter is not operating in current limit,
the maximum valley current is set above the peak inductor current, preventing valley control from being used
unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high, such
that the inductor current peak value exceeds the peak command dictated by compensation, the high-side device
cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit reduces
both peak and valley current. After a low enough current is selected by the compensation circuit, valley current
matches that being commanded by the compensation circuit. Under these conditions, the low-side device is kept
on and the next clock cycle is prevented from starting until inductor current drops below the desired valley
current. Because the on time is fixed at its minimum value, this type of operation resembles that of a device
using a constant on-time (COT) control scheme; see 图 8-19.
SW Voltage
VSW
D=
VIN
tON
VOUT
≈
tSW
VIN
tON = tON_MIN
tOFF
0
- IOUTRDSON-LS
t
tSW > Clock setting
Inductor Current
iL
IOUT
Iripple
IVAL
0
t
In valley control mode, minimum inductor current is regulated, not peak inductor current.
图 8-19. Valley Current Mode Operation
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8.4.3.5 Dropout
Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the
required duty cycle. At a given clock frequency the duty cycle is limited by minimum off time. After this limit is
reached, as shown in 图 8-21, and the clock frequency was to be maintained, the output voltage can fall. Instead
of allowing the output voltage to drop, the device extends the high-side switch on time past the end of the clock
cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle after peak
inductor current is achieved or after a pre-determined maximum on time, tON-MAX, of approximately 9 µs passes.
As a result, after the needed duty cycle cannot be achieved at the selected clock frequency due to the existence
of a minimum off time, frequency drops to maintain regulation. As shown in 图 8-20, if input voltage is low
enough so that output voltage cannot be regulated even with an on time of tON-MAX, output voltage drops to
slightly below the input voltage by VDROP1. For additional information on recovery from dropout, refer to 图 8-10.
Input
Voltage
Output Voltage
VOUT
VDROP1
Output
Voltage
Output
Setting
Switching Frequency
0
Input Voltage
VIN
FSW
FSW-NOM
FSW-LOW
0
Input Voltage
VIN
Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC
reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at FSW-LOW which is
approximately 110-kHz, input voltage tracks output voltage.
图 8-20. Frequency and Output Voltage in Dropout
SW Voltage
VSW
VIN
D=
tON
tSW
VOUT
VIN
tOFF = tOFF_MIN
tON < tON_MAX
0
- IOUTRDSON-LS
t
Inductor Current
tSW > Clock setting
iL
IPEAK
IOUT
0
Iripple
t
Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result,
frequency drops. This frequency drop is limited by tON-MAX.
图 8-21. Dropout Waveforms
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMQ664x0-Q1 step-down DC-to-DC converters are typically used to convert a higher DC voltage to a lower
DC voltage. The LMQ66430-Q1 supports a maximum output current of 3 A while the LMQ66420-Q1 and
LMQ66410-Q1 support a maximum output current of 2 A and 1 A, respectively. The following design procedure
can be used to select components for the LMQ66430-Q1. The design procedure can also be used to select
components for the LMQ66420-Q1 or LMQ66410-Q1 by limiting the maximum output current to 2 A or 1 A,
respectively.
备注
All of the capacitance values given in the following application information refer to effective values
unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and
temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with
an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage
coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance
drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help
mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective
capacitance up to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to
ensure that the minimum value of effective capacitance is provided.
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9.2 Typical Application
For the circuit schematic, bill of materials, PCB layout files, and test results of an LMQ664x0-Q1 implementation
see the LMQ66430-Q1 EVM. As a quick-start guide, 表 9-1 and 表 9-4 provide typical component values for a
range of the most common output voltages.
表 9-1. Typical External Component Values for Adjustable Output LMQ66430-Q1
ƒSW
(kHz)
(1)
VOUT
(V)
L (µH)
Nominal COUT
(Rated
Capacitance)
Minimum
COUT(Effective
Capacitance)(2)
RFBT (kΩ)(3)
RFBB (kΩ)
CIN
CBOOT
CVCC
CFF (4)
400
3.3
10
3 × 22 µF
60 µF
33.2
14.3
4.7 µF
DNP
1 µF
100 pF
2200
3.3
2.2
3 × 22 µF
60 µF
33.2
14.3
4.7 µF
DNP
1 µF
DNP
400
5
10
3 × 22 µF
60 µF
49.9
12.4
4.7 µF
DNP
1 µF
100 pF
2200
5
2.2
3 × 22 µF
60 µF
49.9
12.4
4.7 µF
DNP
1 µF
DNP
(1)
(2)
(3)
(4)
Inductor values are calculated based on typical VIN = 12 V.
Minimum COUT values take into account the effects of DC bias voltage and temperature on the actual capacitance value.
For RFBT and RFBB values outside the range stated above, see 节 9.2.1.2.2.1.
See 节 9.2.1.2.8 for more information.
表 9-2. Typical External Component Values for Adjustable Output LMQ66420-Q1
L (µH)
(1)
VOUT
(V)
Nominal COUT
(Rated
Capacitance)
Minimum
COUT(Effective
Capacitance)(2)
RFBT (kΩ)(3)
RFBB (kΩ)
CIN
CBOOT
CVCC
CFF (4)
400
3.3
6.8
3 × 22 µF
60 µF
33.2
14.3
4.7 µF
DNP
1 µF
100 pF
2200
3.3
2.2
2 × 22 µF
40 µF
33.2
14.3
4.7 µF
DNP
1 µF
DNP
400
5
6.8
3 × 22 µF
60 µF
49.9
12.4
4.7 µF
DNP
1 µF
100 pF
2200
5
2.2
2 × 22 µF
40 µF
49.9
12.4
4.7 µF
DNP
1 µF
DNP
ƒSW
(kHz)
(1)
(2)
(3)
(4)
Inductor values are calculated based on typical VIN = 12 V.
Minimum COUT values take into account the effects of DC bias voltage and temperature on the actual capacitance value.
For RFBT and RFBB values outside the range stated above, see 节 9.2.1.2.2.1.
See 节 9.2.1.2.8 for more information.
表 9-3. Typical External Component Values for Adjustable Output LMQ66410-Q1
ƒSW
(kHz)
(1)
VOUT
(V)
L (µH)
Nominal COUT
(Rated
Capacitance)
Minimum
COUT(Effective
Capacitance)(2)
RFBT (kΩ)(3)
RFBB (kΩ)
CIN
CBOOT
CVCC
CFF (4)
400
3.3
22
2 × 22 µF
40 µF
33.2
14.3
4.7 µF
DNP
1 µF
100 pF
2200
3.3
4.7
1 × 22 µF
20 µF
33.2
14.3
4.7 µF
DNP
1 µF
DNP
400
5
22
2 × 22 µF
40 µF
49.9
12.4
4.7 µF
DNP
1 µF
100 pF
2200
5
4.7
1 × 22 µF
20 µF
49.9
12.4
4.7 µF
DNP
1 µF
DNP
(1)
(2)
(3)
(4)
Inductor values are calculated based on typical VIN = 12 V.
Minimum COUT values take into account the effects of DC bias voltage and temperature on the actual capacitance value.
For RFBT and RFBB values outside the range stated above, see 节 9.2.1.2.2.1.
See 节 9.2.1.2.8 for more information.
表 9-4. Typical External Component Values for Fixed Output LMQ66430-Q1
L (µH)
(1)
VOUT
(V)
Nominal COUT
(Rated
Capacitance)
Minimum
COUT(Effective
Capacitance)(2)
RFBT (Ω)
RFBB (Ω)(3)
CIN
CBOOT
CVCC
CFF
400
3.3
10
3 × 22 µF
60 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
2200
3.3
2.2
2 × 22 µF
40 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
400
5
10
3 × 22 µF
60 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
2200
5
2.2
2 × 22 µF
40 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
ƒSW
(kHz)
(1)
28
Inductor values are calculated based on typical VIN = 12 V.
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(2)
(3)
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Minimum COUT values take into account the effects of DC bias voltage and temperature on the actual capacitance value.
DNP = Do Not Populate.
表 9-5. Typical External Component Values for Fixed Output LMQ66420-Q1
L (µH)
(1)
VOUT
(V)
Nominal COUT
(Rated
Capacitance)
Minimum
COUT(Effective
Capacitance)(2)
RFBT (kΩ)
RFBB (kΩ)(3)
CIN
CBOOT
CVCC
CFF
400
3.3
6.8
3 × 22 µF
60 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
2200
3.3
2.2
2 × 22 µF
40 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
400
5
6.8
3 × 22 µF
60 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
2200
5
2.2
2 × 22 µF
40 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
ƒSW
(kHz)
(1)
(2)
(3)
Inductor values are calculated based on typical VIN = 12 V.
Minimum COUT values take into account the effects of DC bias voltage and temperature on the actual capacitance value.
DNP = Do Not Populate.
表 9-6. Typical External Component Values for Fixed Output LMQ66410-Q1
ƒSW
(kHz)
(1)
VOUT
(V)
L (µH)
Nominal COUT
(Rated
Capacitance)
Minimum
COUT(Effective
Capacitance)(2)
RFBT (kΩ)
RFBB (kΩ)(3)
CIN
CBOOT
CVCC
CFF
400
3.3
22
2 × 22 µF
40 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
2200
3.3
4.7
1 × 22 µF
20 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
400
5
22
2 × 22 µF
40 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
2200
5
4.7
1 × 22 µF
20 µF
0
DNP
4.7 µF
DNP
1 µF
DNP
(1)
(2)
(3)
Inductor values are calculated based on typical VIN = 12 V.
Minimum COUT values take into account the effects of DC bias voltage and temperature on the actual capacitance value.
DNP = Do Not Populate.
9.2.1 Design 1 - Automotive Synchronous Buck Regulator at 2.2 MHz
图 9-1 shows a typical application circuit of the LMQ664x0-Q1 synchronous buck regulator with output voltage
set at 3.3 V and rated load current of 3 A. This device is designed to function over a wide range of external
components and system parameters. However, the internal compensation is optimized for a certain range of
external inductance and output capacitance. In this example the nominal input voltage is 12 V and ranges
between 4 V and 36 V. The maximum switching frequency is set at 2.2 MHz by connecting the MODE/SYNC pin
to GND, which allows for the device to operate in AUTO mode. The VOUT/FB pin is connected directly to the
output voltage node which improves efficiency performance.
L = 3.3 µH
VOUT = 3.3 V
VIN = 4 V … 36 V
SW
VIN
CIN
2 × 10 µF
COUT = 2 × 22 µF
BOOT
EN
LMQ66430-Q1
MODE/
SYNC
PG
VOUT / FB
VCC
CVCC
1 µF
RFBT
SHUNT
GND
RFBB
DNP
图 9-1. Application Circuit 1 - 3.3 V (fixed), 3 A, 2.2 MHz
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9.2.1.1 Design Requirements
节 9.2.1.2 provides a detailed design procedure based on 表 9-7.
表 9-7. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V (4 V to 36 V)
Output voltage
3.3 V
Maximum output current
0 A to 3 A
Switching frequency
2200 kHz
9.2.1.2 Detailed Design Procedure
The following design procedure applies to Figure 9-1 and 表 9-4.
9.2.1.2.1 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more
compact design. For this example, 2200 kHz is used.
For designs that synchronize the switching frequency using the SYNC pin, this pin must not be left floating. To
ensure that the SYNC pin has a known state, place either a pull-up or pull-down resistor depending on the
desired default switching state. If a pull-up resistor is selected, ensure that the pull-up source voltage does not
exceed the absolute maximum rating of the pin.
9.2.1.2.2 Setting the Output Voltage
VOUT / FB of the device can be either connected directly to the output capacitor or a midpoint of a feedback
resistor divider. When connected directly to the output capacitor, the device assumes that a fixed output voltage
of either 3.3 V or 5 V is desired. The 3.3-V or 5-V fixed output options are factory trimmed and the output is
unique to a specific device. See 节 5 for the selection of fixed output voltage versions.
9.2.1.2.2.1 VOUT / FB for Adjustable Output
If other voltages are desired, VOUT / FB can be connected to a feedback resistor divider network to set the output
voltage. The divider network is comprised of RFBT and RFBB, and closes the loop between the output voltage and
the converter. The converter regulates the output voltage by holding the voltage on the VOUT / FB pin equal to
the internal reference voltage, VREF. The converter determines whether fixed output voltage or adjustable output
voltage is required by sensing the resistance of the feedback path during start-up. To ensure that the converter
regulates to the desired output voltage, the typical minimum value for the parallel combination of RFBT and RFBB
is 5 kΩ while the typical maximum value is 10 kΩ as shown in 方程式 4. 方程式 5 can be used as a starting
point to determine the value of RFBT. Reference 表 9-8 for a list of acceptable resistor values for various output
voltages.
5 kΩ < RFBT
RFBB ≤ 10 kΩ
(4)
VOUT
RFBT ≤ 10 kΩ × 1 V
(5)
表 9-8. Recommended Feedback Resistor Values for Various Output Voltages
30
VOUT (V)
RFBT (kΩ)(1)
RFBB (kΩ)
2.5
24.9
16.5
3.3
33.2
14.3
5
49.9
12.4
6
60.4
12.1
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表 9-8. Recommended Feedback Resistor Values for Various Output Voltages (continued)
(1)
VOUT (V)
RFBT (kΩ)(1)
RFBB (kΩ)
9
90.9
11.3
RFBT and RFBB based on 1% standard resistor values.
For this 3.3-V example, the user can choose the LMQ66430MC3RXBRQ1 and connect VOUT / FB directly to the
output capacitor.
9.2.1.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the
maximum output current capability of the device (example 3-A for LMQ66430-Q1). Note that when selecting the
ripple current use the maximum device current. 方程式 6 can be used to determine the value of inductance. The
constant K is the ratio of peak-to-peak inductor current ripple to the maximum device current. For this example,
choose K = 0.2 and find an inductance of L = 1.81 µH. Select the standard value of 2.2 µH.
V
−V
V
IN
OUT
L= f
× VOUT
IN
SW × K × IOUTmax
(6)
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit,
IPEAKMAX (see the Electrical Characteristics). This makes sure that the inductor does not saturate, even during a
short circuit on the output. When the inductor core material saturates, the inductance falls to a very low value,
causing the inductor current to rise very rapidly. Although the valley current limit, IVALMAX, is designed to reduce
the risk of current runaway, a saturated inductor can cause the current to rise to high values very rapidly. This
can lead to component damage. Do not allow the inductor to saturate. Inductors with a ferrite core material have
very hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron
cores exhibit a soft saturation, allowing some relaxation in the current rating of the inductor. However, they have
more core losses at frequencies above about 1 MHz. In any case, the inductor saturation current must not be
less than the maximum peak inductor current at full load.
The maximum inductance is limited by the minimum current ripple for the current mode control to perform
correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device
maximum rated current under nominal conditions.
9.2.1.2.4 Output Capacitor Selection
The current mode control scheme of the LMQ664x0-Q1 devices allows operation over a wide range of output
capacitance. The output capacitor bank is usually limited by the load transient requirements and stability rather
than the output voltage ripple. Refer to 表 9-1 and 表 9-4 for typical output capacitor values for 3.3-V and 5-V
output voltages. Based on 表 9-4, for a fixed 3.3-V output design, the user can choose the recommended 2 × 22µF ceramic output capacitor for this example. For other designs with other output voltages, WEBENCH can be
used as a starting point for selecting the value of output capacitor.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
capacitor placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the
range of 1 nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board
parasitics.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.
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9.2.1.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 4.7 µF is required on
the input of the LMQ664x0-Q1. This must be rated for at least the maximum input voltage that the application
requires, preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple and maintain the input voltage during load transients. For this example, a 4.7-µF, 50-V, X7R (or
better) ceramic capacitor is chosen.
It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramic capacitor. This is
especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of
this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
RMS value of this current can be calculated from 方程式 7 and must be checked against the manufacturers'
maximum ratings.
IRMS #
IOUT
2
(7)
9.2.1.2.6 CBOOT
The LMQ664x0-Q1 has an integrated bootstrap 0.1-μF capacitor connected internally between the BOOT pin
and the SW pin. This capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. If
needed, an additional high-quality ceramic capacitor can be added externally.
9.2.1.2.7 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this
output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for
the power-good function (see 节 8.3.3). A value in the range of 10 kΩ to 100 kΩ is a good choice in this case.
The nominal output voltage on VCC is 3.3 V; see the Electrical Characteristics for limits.
9.2.1.2.8 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. The Optimizing Transient Response of Internally Compensated DC-DC
Converters with Feedforward Capacitor Application Report is helpful when experimenting with a feedforward
capacitor.
Due to the nature of the feedback detect circuitry, the value of CFF must be limited to ensure that the desired
output voltage is established when configuring for adjustable output voltages. 方程式 8 must be followed to
ensure CFF remains below the maximum value.
VOUT
CFF < COUT × 1.2 MΩ
(8)
9.2.1.2.9 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in 图 9-2. The input voltage at which the device turns on is designated
as VON while the turn-off voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100 kΩ, then
方程式 9 and 方程式 10 are used to calculate RENT and VOFF, respectively.
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VIN
RENT
EN
RENB
图 9-2. Setup for External UVLO Application
V
ON
RENT = V
− 1 × RENB
EN − VOUT
V
VOFF = VON × 1 − V EN − HYS
EN − VOUT
(9)
(10)
where
• VON is the VIN turn-on voltage.
• VOFF is the VIN turn-off voltage.
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9.2.1.2.10 Maximum Ambient Temperature
As with any power conversion device, the LMQ664x0-Q1 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance,
RθJA, of the device, and PCB combination. The maximum junction temperature for the LMQ664x0-Q1 must be
limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. 方程式 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. For more information, refer to the
Semiconductor and IC Package Thermal Metrics Application Report.
IOUT
MAX
=
T J − TA
η
1
RθJA × 1 − η × VOUT
(11)
where
• η is the efficiency.
The effective RθJA is a critical parameter and depends on many factors such as the following:
•
•
•
•
•
•
Power dissipation
Air temperature/flow
PCB area
Copper heat-sink area
Number of thermal vias under the package
Adjacent component placement
The IC junction temperature can be estimated for a given operating condition using 方程式 12.
T J ≅ TA + RθJA × IC Power Loss
(12)
where
• TJ is the IC junction temperature (°C).
• TA is the ambient temperature (°C).
• RθJA is the thermal resistance (°C/W).
• IC power loss is the power loss for the IC (W).
The IC power loss mentioned above is the overall power loss minus the loss that comes from the inductor DC
resistance. The overall power loss can be approximated by using WEBENCH for a specific operating condition
and temperature.
图 9-3 below is provided to estimate the thermal resistance of the IC for a particular board area.
34
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80
75
RθJA°C/W)
(
70
65
60
55
50
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Board Area (cm2)
The device operating conditions are as follows: 12-VIN, 3.3-VOUT, 3-A load, 2.2-MHz, 23ºC ambient. 4 layer board, GND plane on MidLayer One, 2.8-mil thick copper on each layer, see LMQ66430-Q1 Buck Controller Evaluation Module User’s Guide for copper pattern
and thermal vias.
图 9-3. RθJA vs Board Area
Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given
application environment:
•
•
•
•
•
•
•
•
Thermal Design by Insight not Hindsight Application Report
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
Semiconductor and IC Package Thermal Metrics Application Report
Thermal Design Made Simple with LM43603 and LM43602 Application Report
PowerPAD™ Thermally Enhanced Package Application Report
PowerPAD™ Made Easy Application Report
Using New Thermal Metrics Application Report
PCB Thermal Calculator
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9.2.1.3 Application Curves
Unless otherwise specified, the following conditions apply: VIN = 12 V, TA = 25°C
90
92
80
88
70
Efficiency (%)
100
96
Efficiency (%)
100
84
80
76
VIN = 12 V
VIN = 18 V
VIN = 24 V
60
50
40
72
30
68
20
VIN = 12 V
VIN = 18 V
VIN = 24 V
64
60
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
LMQ66430MC3
VOUT = 3.3 V
Fixed
0.5
1
10
0
0.001
2 3
2.2 MHz (Auto)
0.005
LMQ66430MC3
图 9-4. Efficiency
3.4
3.306
3.3
3.3045
Output Voltage (V)
Output Voltage (V)
VOUT = 3.3 V
Fixed
1
2 3
2.2 MHz (FPWM)
VIN = 12 V
VIN = 18 V
VIN = 24 V
3.303
3.1
3
2.9
2.8
2.7
2.6
3.3015
3.3
3.2985
3.297
IOUT = 0.5 A
IOUT = 1 A
IOUT = 1.5 A
IOUT = 2 A
2.5
2.4
3.2955
3.294
3.2925
2.3
3
3.2
3.4
LMQ66430MC3
3.6
3.8
4
4.2
Input Voltage (V)
4.4
VOUT = 3.3 V
Fixed
4.6
4.8
0
5
2.2 MHz (Auto)
0.3
0.6
0.9
LMQ66430MC3
图 9-6. Dropout
1.2 1.5 1.8
Load Current (A)
2.1
VOUT = 3.3 V
Fixed
2.4
2.7
3
2.2 MHz (Auto)
图 9-7. Line and Load Regulation
5
1
4.5
0.9
4
0.8
3.5
0.7
Input Current (A)
Input Current (µA)
0.5
图 9-5. Efficiency
3.2
3
2.5
2
1.5
VIN = 12 V
VIN = 18 V
VIN = 24 V
0.6
0.5
0.4
0.3
0.2
1
0.1
0.5
0
0
5
10
LMQ66430MC3
15
20
25
Input Voltage (V)
VOUT = 3.3 V
Fixed
30
35
40
2.2 MHz (Auto)
No Load
图 9-8. Input Switching Current vs Input Voltage
36
0.02 0.05 0.1 0.2
Output Current (A)
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0.3
0.6
LMQ66430MC3
0.9
1.2 1.5 1.8
Load Current (A)
VOUT = 3.3 V
Fixed
2.1
2.4
2.7
3
2.2 MHz (Auto)
图 9-9. Input Current vs Load Current
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VOUT (200mV/DIV)
VOUT (200mV/DIV)
IOUT (1A/DIV)
IOUT (1A/DIV)
100 µs/DIV
100 µs/DIV
LMQ66430MC3
VOUT = 3.3 V
0 A to 2 A,1 A / µs
2.2 MHz (Auto)
Fixed
图 9-10. Load Transient
LMQ66430MC3
VOUT = 3.3 V
0.5 A to 1.5 A,1 A / µs
图 9-11. Load Transient
VOUT (200mV/DIV)
VOUT (200mV/DIV)
IOUT (1A/DIV)
IOUT (1A/DIV)
100 µs/DIV
100 µs/DIV
LMQ66430MC3
VOUT = 3.3 V
0 A to 1 A,1 A / µs
2.2 MHz (FPWM)
Fixed
图 9-12. Load Transient
LMQ66430MC3
VOUT = 3.3 V
0 A to 1 A,1 A / µs
VOUT (50mV/DIV)
100 ms/DIV
1 µs/DIV
VOUT = 3.3 V
Fixed
2.2 MHz (Auto)
Fixed
图 9-13. Load Transient
VOUT (20mV/DIV)
LMQ66430MC3
2.2 MHz (Auto)
Fixed
2 A Load
图 9-14. Output Voltage Ripple
LMQ66430MC3
VOUT = 3.3 V
Fixed
No Load
图 9-15. Output Voltage Ripple
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LMQ66430MC3
VOUT = 3.3 V
Fixed
12 VIN, 2 A, 2.2 MHz
图 9-16. EVM Thermal Performance
VIN = 12.5 V
VOUT = 3.3 V
Fsw = 2.2 MHz
Load = 3 A
图 9-18. CISPR 25 Class 5 Conducted EMI 150
kHz–30 MHz
Yellow: Peak Detect, Green: Average Detect
VIN = 12.5 V
VOUT = 3.3 V
Fsw = 2.2 MHz
Load = 3 A
图 9-20. CISPR 25 Class 5 Radiated EMI, Rod
Antenna, 150 kHz–30 MHz
Blue: Peak Detect, Yellow: Average Detect
38
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LMQ66430MC3
VOUT = 3.3 V
Fixed
12 VIN, 3 A, 2.2 MHz
图 9-17. EVM Thermal Performance
VIN = 12.5 V
VOUT = 3.3 V
Fsw = 2.2 MHz
Load = 3 A
图 9-19. CISPR 25 Class 5 Conducted EMI 30
MHz–108 MHz
Yellow: Peak Detect, Green: Average Detect
VIN = 12.5 V
VOUT = 3.3 V
Fsw = 2.2 MHz
Load = 3 A
图 9-21. CISPR 25 Class 5 Radiated EMI, Biconical
Antenna, Horizontal Polarization, 30 MHz - 300 MHz
Red: Peak Detect, Green: Average Detect
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VIN = 12.5 V
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
VOUT = 3.3 V
VIN = 12.5 V
Fsw = 2.2 MHz
Load = 3 A
图 9-22. CISPR 25 Class 5 Radiated EMI, Biconical
Antenna, Vertical Polarization, 30 MHz - 300 MHz
Orange: Peak Detect, Yellow: Average Detect
VIN = 12.5 V
VOUT = 3.3 V
Fsw = 2.2 MHz
Load = 3 A
图 9-23. CISPR 25 Class 5 Radiated EMI, Log
Antenna, Horizontal Polarization, 300 MHz - 960
MHz
Orange: Peak Detect, Blue: Average Detect
VOUT = 3.3 V
Fsw = 2.2 MHz
Load = 3 A
图 9-24. CISPR 25 Class 5 Radiated EMI, Log Antenna, Vertical Polarization, 300 MHz - 960 MHz
Orange: Peak Detect, Blue: Average Detect
LISN +
0
Ferrite Bead
VIN
RFILT
CFIL1
2.2 F
CBULK
47 F
LISN -
Ferrite Bead Part Number
FBMH3225HM102NT
图 9-25. Typical Input EMI Filter
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9.2.2 Design 2 - Automotive Synchronous Buck Regulator at 400 kHz
图 9-26 shows the schematic diagram of a synchronous buck regulator with an output voltage set at 5 V and a
rated load current of 3 A. The MODE/SYNC pin is connected to a function generator to set the switching
frequency to 400 kHz.
In this example, the nominal input voltage is 12 V and ranges from 7 V to 36 V.
L = 10 µH
VOUT = 5 V
VIN = 7 V … 36 V
SW
VIN
CIN
2 × 10 µF
COUT = 6 × 10 µF
BOOT
EN
LMQ66430-Q1
MODE/
SYNC
SYNC
PG
100 pF
VOUT / FB
VCC
CVCC
1 µF
CFF
RFBT
49.9 k
RFBB
12.4 k
GND
图 9-26. Application Circuit 2 - 5 V (adjustable), 3 A, 400 kHz
9.2.2.1 Design Requirements
表 9-9 describes the intended operating conditions for this design example.
表 9-9. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input Voltage
12 V (7 V to 36 V)
Output Voltage
5V
Maximum Output Current
0 A to 3 A
Switching Frequency
400 kHz
9.2.2.2 Detailed Design Procedure
Refer to 节 9.2.1.2 for detail related to component selection for this 400-kHz design.
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9.2.2.3 Application Curves
Unless otherwise specified, the following conditions apply: VIN = 12 V, VOUT = 5 V, IOUT = 3 A, fSW = 400 kHz,
and TA = 25ºC. 图 9-26 shows the circuit schematic with relevant component values.
5.046
100
90
VIN = 12 V
VIN = 24 V
VIN = 36 V
5.044
80
Output Voltage (V)
Efficiency (%)
70
60
50
40
30
20
VIN = 12 V
VIN = 24 V
VIN = 36 V
10
5.042
5.04
5.038
5.036
5.034
5.032
0
0.001
0.01
LMQ66430MC3
0.1
Output Current (A)
VOUT = 5 V
Adjustable
1
3
400 kHz (FPWM)
图 9-27. Efficiency
0
0.5
LMQ66430MC3
1
1.5
2
Output Current (A)
VOUT = 5 V
Adjustable
2.5
3
3.5
400 kHz (FPWM)
图 9-28. Line and Load Regulation
1.6
VIN = 12 V
VIN = 24 V
VIN = 36 V
1.4
VOUT (200 mV/DIV)
Input Current (A)
1.2
1
IOUT (1 A/DIV)
0.8
0.6
0.4
0.2
100 µs/DIV
0
0
0.5
LMQ66430MC3
1
1.5
2
Output Current (A)
VOUT = 5 V
Adjustable
2.5
3
400 kHz (FPWM)
图 9-29. Input Current vs Load Current
LMQ66430MC3
VOUT = 5 V
0 A to 3 A,1 A / µs
400 kHz (FPWM)
Adjustable
图 9-30. Load Transient
VOUT (200 mV/DIV)
VOUT (20 mV/DIV)
IOUT (1 A/DIV)
2 µs/DIV
100 µs/DIV
LMQ66430MC3
VOUT = 5 V
0 A to 2 A,1 A / µs
400 kHz (FPWM)
Adjustable
图 9-31. Load Transient
LMQ66430MC3
VOUT = 5 V
Adjustable
3 A Load
图 9-32. Output Voltage Ripple
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ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
9.3 Best Design Practices
•
•
•
•
•
•
Do not exceed the Absolute Maximum Ratings.
Do not exceed the Recommended Operating Conditions.
Do not exceed the ESD Ratings.
Do not allow the EN input to float.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
Follow all the guidelines and suggestions found in this data sheet before committing the design to production.
TI application engineers are ready to help critique your design and PCB layout to help make your project a
success.
9.4 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Specifications found in this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded regulator. The
average input current can be estimated with 方程式 13.
IIN
VOUT ˜ IOUT
VIN ˜ K
(13)
where
• η is the efficiency.
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shut down and reset. The best way to solve these kinds of issues is to limit the distance
from the input supply to the regulator or plan to use an aluminum or tantalum input capacitor in parallel with the
ceramics. The moderate ESR of these types of capacitors help dampen the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DC/DC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
9.5 Layout
9.5.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power
ground, as shown in 图 9-33. This loop carries large transient currents that can cause large transient voltages
when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the
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ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
to reduce the parasitic inductance. 图 9-34 shows a recommended layout for the critical components of the
LMQ664x0-Q1.
• Place the input capacitors as close as possible to the VIN and GND terminals.
• Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and
routed with short, wide traces to the VCC and GND pins.
• If an external CBOOT capacitor is desired: Place CBOOT close to the device with short/wide traces to the BOOT
and SW pins.
• Place the feedback divider as close as possible to the VOUT / FB pin of the device. Place RFBB, RFBT, and
CFF, if used, physically close to the device. The connections to VOUT / FB and GND must be short and close
to those pins on the device. The connection to VOUT can be somewhat longer. However, the latter trace must
not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback
path of the regulator.
• Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat
dissipation path.
• Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any
voltage drops on the input or output paths of the converter and maximizes efficiency.
• Provide enough PCB area for proper heat-sinking. As stated in 节 9.2.1.2.10, enough copper area must be
used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. The top
and bottom PCB layers must be made with two-ounce copper and no less than one ounce. If the PCB design
uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer
heat-spreading ground planes.
• Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
•
•
•
•
Layout Guidelines for Switching Power Supplies Application Report
Simple Switcher PCB Layout Guidelines Application Report
Construction Your Power Supply- Layout Considerations Seminar
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
VIN
CIN
SW
GND
图 9-33. Current Loops with Fast Edges
9.5.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground
plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control
circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as
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www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the
ground plane contains much less noise; use for sensitive routes.
TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See
图 9-34 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom
layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting
from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout,
provides low current conduction impedance, proper shielding, and lower thermal resistance.
9.5.2 Layout Example
RENT
RT
NC
VOUT/FB
VCC
NC
CFF
CVCC
NC
SW
NC
CIN
RFBT
NC
VIN
PGND
CIN
PG
RFBB
EN
BOOT
L1
COUT
COUT
COUTHF
图 9-34. Example Layout
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ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
10.1.2 Device Nomenclature
图 10-1 shows the device naming nomenclature of the LMQ664x0-Q1. See 节 5 for the availability of each
variant. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options;
minimum order quantities apply.
LM X 664 X 0 X X X RXBX – Q1
CAPACITOR INTEGRATION
Q: With Internal Capacitors
R: Without Internal Capacitors
OUTPUT CURRENT MAX
1: 1 A
2: 2 A
3: 3 A
MODE
TRIM OPTION
M: Mode/SYNC Trim *No character defaults to:
R: RT Trim
RT – Auto
A: 400 kHz Fixed Frequency
B: 1 MHz Fixed Frequency
C: 2 MHz Fixed Frequency
F: RT – FPWM
VOUT OPTION
3: 3.3 V Fixed
5: 5 V Fixed
PACKAGE
AUTO
RXBR = WQFN 15-pin large reel
RXBT = WQFN 15-pin tape
*Both variants
can be setup
for ADJ voltage
output
图 10-1. Device Naming Nomenclature
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Thermal Design by Insight not Hindsight Application Report
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package Application Report
• Texas Instruments, PowerPAD™ Made Easy Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
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LMQ66410-Q1, LMQ66420-Q1, LMQ66430-Q1
www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
HotRod™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
46
本术语表列出并解释了术语、首字母缩略词和定义。
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www.ti.com.cn
ZHCSLK1B – FEBRUARY 2022 – REVISED MAY 2023
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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English Data Sheet: SNVSBV1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LMQ66410MC3RXBRQ1
ACTIVE
VQFN-FCRLF
RXB
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
1MC3Q
Samples
LMQ66410MC5RXBRQ1
ACTIVE
VQFN-FCRLF
RXB
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
1MC5Q
Samples
LMQ66420MA3RXBRQ1
ACTIVE
VQFN-FCRLF
RXB
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
2MA3Q
Samples
LMQ66420MC3RXBRQ1
ACTIVE
VQFN-FCRLF
RXB
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
2MC3Q
Samples
LMQ66420MC5RXBRQ1
ACTIVE
VQFN-FCRLF
RXB
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
2MC5Q
Samples
LMQ66430MC3RXBRQ1
ACTIVE
VQFN-FCRLF
RXB
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
3MC3Q
Samples
LMQ66430MC5RXBRQ1
ACTIVE
VQFN-FCRLF
RXB
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
3MC5Q
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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