LMR33630-Q1
SNVSB26C – JUNE 2018 – REVISED OCTOBER 2020
LMR33630-Q1 3.8-V to 36-V, 3-A Synchronous Step-Down Voltage Converter
1 Features
3 Description
•
The LMR33630-Q1 automotive-qualified regulator
is an easy-to-use, synchronous, step-down DC/DC
converter that delivers best-in-class efficiency for
rugged applications. The LMR33630-Q1 drives up
to 3 A of load current from an input of up to
36 V. The LMR33630-Q1 provides high light load
efficiency and output accuracy in a very small solution
size. Features such as a power-good flag and
precision enable provide both flexible and easy-touse solutions for a wide range of applications. The
LMR33630-Q1 automatically folds back frequency at
light load to improve efficiency. Integration eliminates
most external components and provides a pinout
designed for simple PCB layout. Protection features
include thermal shutdown, input undervoltage lockout,
cycle-by-cycle current limit, and hiccup short-circuit
protection. The LMR33630-Q1 is available in a 12-pin
3 mm × 2 mm next generation VQFN package with
wettable flanks.
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Configured for rugged automotive applications
– Input voltage range: 3.8 V to 36 V
– Output voltage range: 1 V to 24 V
– Output current: 3 A
– 75-mΩ/50-mΩ RDS-ON power MOSFETs
– Peak-current-mode control
– Short minimum on-time of 68 ns
– Frequency: 400 kHz, 1.4 MHz, 2.1 MHz
– Integrated compensation network
Low EMI and switching noise
– HotRod™ package
– Parallel input current paths
High power conversion at all loads
– Peak efficiency > 95%
– Low shutdown quiescent current of 5 µA
– Low operating quiescent current of 25 µA
Create a custom design using the LMR33630-Q1
with the WEBENCH® Power Designer
2 Applications
•
•
Device Information
PART NUMBER
LMR33630-Q1
(1)
PACKAGE(1)
VQFN (12)
BODY SIZE (NOM)
3.00 mm × 2.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Infotainment and cluster : USB charge
Telematics control unit
BOOT
VIN
VIN
CBOOT
CIN
EN
SW
L1
VOUT
COUT
PGND
VCC
PG
RFBT
CVCC
FB
RFBB
AGND
Simplified Schematic
Minimum Component Example
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR33630-Q1
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SNVSB26C – JUNE 2018 – REVISED OCTOBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Timing Characteristics.................................................8
6.7 System Characteristics............................................... 9
6.8 Typical Characteristics.............................................. 10
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................15
8 Application and Implementation.................................. 19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 19
8.3 What to Do and What Not to Do............................... 30
9 Power Supply Recommendations................................31
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................35
11.1 Device Support........................................................35
11.2 Documentation Support.......................................... 35
11.3 Support Resources................................................. 35
11.4 Receiving Notification of Documentation Updates.. 35
11.5 Trademarks............................................................. 35
11.6 Electrostatic Discharge Caution.............................. 36
11.7 Glossary.................................................................. 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2019) to Revision C (October 2020)
Page
• Added functional safety bullet in the Features ...................................................................................................1
• Added low EMI and switching noise bullet to the Features ............................................................................... 1
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
Changes from Revision A (November 2018) to Revision B (March 2019)
Page
• Changed block diagram to fix drawing error..................................................................................................... 11
Changes from Revision * (June 2018) to Revision A (November 2018)
Page
• First release of production-data data sheet ....................................................................................................... 1
2
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Device Comparison Table
DEVICE OPTION
PACKAGE
LMR33630AQRNX
LMR33630BQRNX
RNX (12-pin VQFN)
3 × 2 × 0.85 mm
LMR33630CQRNX
FREQUENCY
RATED CURRENT
400 kHz
3A
1400 kHz
3A
2100 kHz
3A
OUTPUT VOLTAGE
Adjustable
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5 Pin Configuration and Functions
SW
12
11 PGND
PGND 1
VIN
2
10 VIN
NC
3
9 EN
BOOT
4
8 PG
5
VCC
6
7
AGND
FB
Figure 5-1. 12-Pin VQFN RNX Package (Top View)
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1, 11
PGND
G
Power ground terminal. Connect to system ground and AGND. Connect to a bypass capacitor with short wide
traces.
2, 10
VIN
P
Input supply to regulator. Connect a high-quality bypass capacitor(s) directly to this pin and PGND.
3
NC
—
On the VQFN package, connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT
capacitor to the SW pin. This pin has no internal connection to the regulator.
4
BOOT
P
Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this pin to
the SW pin. On the VQFN package connect the SW pin to NC on the PCB. This simplifies the connection from
the CBOOT capacitor to the SW pin.
5
VCC
P
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be
used as logic supply for power-good flag. Connect a high quality 1-µF capacitor from this pin to GND.
6
AGND
G
Analog ground for regulator and system. Ground reference for internal references and logic. All electrical
parameters are measured with respect to this pin. Connect to system ground on PCB.
7
FB
A
Feedback input to regulator. Connect to tap point of feedback voltage divider. DO NOT FLOAT. DO NOT
GROUND.
8
PG
A
Open drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High
= power OK, low = power bad. Flag pulls low when EN = Low. Can be left open when not used.
9
EN
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; DO NOT FLOAT.
12
SW
P
Regulator switch node. Connect to power inductor. On the VQFN package the SW pin must be connected to
NC on the PCB. This simplifies the connection from the CBOOT capacitor to the SW pin.
A = Analog, P = Power, G = Ground
4
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
PARAMETER
MIN
MAX
UNIT
VIN to PGND
–0.3
38
EN to AGND(2)
–0.3
VIN + 0.3
FB to AGND
–0.3
5.5
0
22
AGND to PGND
–0.3
0.3
SW to PGND
–0.3
VIN + 0.3
SW to PGND less than 100-ns transients
–3.5
38
BOOT to SW
–0.3
5.5
VCC to AGND(4)
–0.3
5.5
TJ
Junction temperature(3)
–40
150
°C
Tstg
Storage temperature
–55
150
°C
PG to AGND(2)
Voltages
(1)
(2)
(3)
(4)
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V
Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
Under some operating conditions the VCC LDO voltage may increase beyond 5.5V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
±2500
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over the recommended operating temperature range of –40 °C to 125 °C (unless otherwise noted) (1)
MIN
VIN to PGND
MAX
UNIT
3.8
36
EN (2)
0
VIN
PG(2)
0
18
Adjustable output voltage
VOUT (3)
1
24
V
Output current
IOUT
0
3
A
Input voltage
(1)
(2)
(3)
V
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Section 6.5.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
The maximum output voltage can be extended to 95% of VIN; contact TI for details. Under no conditions should the output voltage be
allowed to fall below zero volts.
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6.4 Thermal Information
The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For design information see Maximum Ambient Temperature
section.
LMR336x0
THERMAL METRIC(1) (2)
RNX (VQFN)
UNIT
12 PINS
72.5(2)
°C/W
Junction-to-case (top) thermal resistance
35.9
°C/W
RθJB
Junction-to-board thermal resistance
23.3
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
23.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes.
These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For design information see Maximum Ambient Temperature section.
6.5 Electrical Characteristics
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VIN
Minimum operating input
voltage
IQ
Non-switching input current;
measured at VIN pin (2)
VFB = 1.2 V
ISD
Shutdown quiescent current;
measured at VIN pin
EN = 0
VEN-VCC-H
EN input level required to turn
on internal LDO
Rising threshold
VEN-VCC-L
EN input level required to turn
off internal LDO
Falling threshold
0.3
VEN-H
EN input level required to start
Rising threshold
switching
1.2
VEN-HYS
Hysteresis below VEN-H
Hysteresis below VEN-H; falling
100
mV
ILKG-EN
Enable input leakage current
VEN = 3.3 V
0.2
nA
3.8
V
24
34
µA
5
10
µA
1
V
ENABLE
V
1.231
1.26
V
INTERNAL SUPPLIES
VCC
Internal LDO output voltage
appearing at the VCC pin
VBOOT-UVLO
Bootstrap voltage
undervoltage lock-out
threshold(3)
6 V ≤ VIN ≤ 36 V
4.75
5
5.25
2.2
V
V
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage; ADJ option
IFB
Current into FB pin; ADJ
option
0.985
FB = 1 V
ISC
High-side current limit
LMR33630
3.85
ILIMIT
Low-side current limit
LMR33630
2.9
IPEAK-MIN
Minimum peak inductor current LMR33630
1
1.015
V
0.2
50
nA
4.5
5.05
A
3.5
4.1
A
CURRENT LIMITS(4)
6
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0.69
A
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Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER
IZC
TEST CONDITIONS
MIN
Zero current detector threshold
TYP
MAX
-0.106
UNIT
A
SOFT START
tSS
Internal soft-start time
2.9
4
6
ms
POWER GOOD (PG PIN)
VPG-HIGH-UP
Power-good upper threshold rising
% of FB voltage
105%
107%
110%
VPG-HIGH-DN
Power-good upper threshold falling
% of FB voltage
103%
105%
108%
VPG-LOW-UP
Power-good lower threshold rising
% of FB voltage
92%
94%
97%
VPG-LOW-DN
Power-good lower threshold falling
% of FB voltage
90%
92%
95%
tPG
Power-good glitch filter
delay(1)
RPG
Power-good flag RDSON
VIN-PG
Minimum input voltage for
proper PG function
50-µA, EN = 0 V
VPG
PG logic low output
50-µA, EN = 0 V, VIN = 2V
ƒSW
Switching frequency
"A" Version
340
400
460
kHz
ƒSW
Switching frequency
"B" Version
1.2
1.4
1.6
MHz
ƒSW
Switching frequency
"C" Version, RNX package
1.8
2.1
2.3
MHz
60
170
VIN = 12 V, VEN = 4 V
76
150
VEN = 0 V
35
60
µs
Ω
2
V
0.2
V
OSCILLATOR
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Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFETS
RDS-ON-HS
High-side MOSFET ONresistance
RNX package
75
145
mΩ
RDS-ON-LS
Low-side MOSFET ONresistance
RNX package
50
95
mΩ
(1)
(2)
(3)
(4)
See Power-Good Flag Output for details.
This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge CBOOT.
The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
6.6 Timing Characteristics
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 12 V, VEN = 4 V.
MIN
8
NOM
MAX
UNIT
tON-MIN
Minimum switch on-time
RNX package
68
80
tOFF-MIN
Minimum switch off-time
RNX package
52
70
ns
tON-MAX
Maximum switch on-time
7
9
µs
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6.7 System Characteristics
The following specifications apply to a typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to
the case of typical components over the temperature range of TJ = –40°C to 125°C. These specifications are not ensured by
production testing.
PARAMETER
VIN
Operating input voltage range
Output voltage regulation for VOUT = 5
V(1)
VOUT
Output voltage regulation for VOUT = 3.3
V(1)
TEST CONDITIONS
VOUT = 3.3 V, IOUT= 0 A
MIN
TYP
MAX
3.8
36
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A to
max. load
–1.5%
2.5%
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A to
max. load
–1.5%
1.5%
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 0 A
to max. load
–1.5%
2.5%
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 1 A
to max. load
–1.5%
1.5%
UNIT
V
ISUPPLY
Input supply current when in regulation
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ
VDROP
Dropout voltage; (VIN – VOUT)
DMAX
Maximum switch duty cycle(2)
VHC
FB pin voltage required to trip short-circuit
hiccup mode
0.4
V
tHC
Time between current-limit hiccup burst
94
ms
tD
Switch voltage dead time
TSD
(1)
(2)
Thermal shutdown temperature
25
µA
VOUT = 5 V, IOUT = 1A
Dropout at –1% of regulation,
ƒSW = 140 kHz
150
mV
VIN = VOUT = 12 V, IOUT = 1 A
98%
2
ns
Shutdown temperature
165
°C
Recovery temperature
148
°C
Deviation is with respect to VIN =12 V, IOUT = 1 A.
In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: ƒMIN =
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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6.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 12 V
36
12
11
10
Shutdown Current (µA)
Quiescent Current (µA)
34
32
30
28
26
-40C
24
9
8
7
6
5
4
25C
22
5
10
15
20
25
30
35
-40C
2
25C
1
125C
20
0
3
Input Voltage (V)
125C
0
0
40
5
10
15
25
30
35
40
Input Voltage (V)
C005
C003
EN = 0 V
VFB = 1.2 V
Figure 6-2. Shutdown Supply Current
Figure 6-1. Non-Switching Input Supply Current
1000
Short Circuit Output Current (mA)
20
1.35
1.30
EN Threshold Voltage (V)
900
800
700
-40C
600
25C
1.25
1.20
1.15
1.10
UP
1.05
DN
125C
500
0
1.00
5
10
15
20
25
30
35
40
Input Voltage (V)
VOUT = 0 V
ƒS = 400 kHz
±40
±20
0
20
40
60
80
100
120
Temperature (C)
C004
140
C006
See Figure 8-29
Figure 6-3. Short-Circuit Output Current
Figure 6-4. Precision Enable Thresholds
1,200
OUTPUT VOLTAGE (0.8V/Div)
Peak Inductor Current (mA)
1,100
1,000
900
800
700
25C
500
DN
125C
UP
400
5
10
15
20
25
30
Input Voltage (V)
0
INPUT VOLTAGE (1V/Div)
IOUT = 1 mA
See Figure 8-29
IOUT = 0 A
ƒSW = 400 kHz
Figure 6-5. UVLO Thresholds
10
-40C
600
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VOUT = 5 V
35
40
C006
See Figure 8-29
Figure 6-6. IPEAK-MIN
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7 Detailed Description
7.1 Overview
The LMR33630-Q1 is a synchronous peak-current-mode buck regulator designed for a wide variety of
applications. Advanced high speed circuitry allows the device to regulate from an input voltage of 20 V, while
providing an output voltage of 3.3 V at a switching frequency of 2.1 MHz. The innovative architecture allows
the device to regulate a 3.3-V output from an input of only 3.8 V. The regulator automatically switches modes
between PFM and PWM depending on load. At heavy loads, the device operates in PWM at a constant
switching frequency. At light loads, the mode changes to PFM with diode emulation allowing DCM. This reduces
the input supply current and keeps efficiency high. The device features internal loop compensation which
reduces design time and requires fewer external components than externally compensated regulators.
The LMR33630-Q1 is available in an ultra-miniature VQFN package with wettable flanks. This package features
extremely small parasitic inductance and resistance, enabling very high efficiency while minimizing switch node
ringing and dramatically reducing EMI. The VIN/PGND pin layout is symmetrical on either side of the VQFN
package. This allows the input current magnetic fields to partially cancel, resulting in reduce EMI generation.
7.2 Functional Block Diagram
VCC
INT. REG.
BIAS
OSCILLATOR
EN
VIN
ENABLE
LOGIC
BOOT
HS CURRENT
SENSE
1.0V
Reference
ERROR
AMPLIFIER
FB
+
-
PG
+
-
PWM
COMP.
CONTROL
LOGIC
PFM MODE
CONTROL
SW
DRIVER
LS CURRENT
SENSE
POWER GOOD
CONTROL
AGND
PGND
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7.3 Feature Description
7.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR33630-Q1 can be used to reset a system
microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault
conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents
false flag operation for short excursions of the output voltage, such as during line and load transients. The timing
parameters of the glitch filter are found in Section 6.5. Output voltage excursions lasting less than tPG do not trip
the power-good flag. Power-good operation can best be understood by reference to Figure 7-1 and Figure 7-2.
Note that during initial power up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted
to the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered
during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT, through a 100-kΩ resistor, as desired. If this function
is not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With
EN low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into the
power-good flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the
device is enabled and about 65 mA when the device is disabled. The internal current limit protects the device
from any transient currents that can occur when discharging a filter capacitor connected to this output.
VOUT
VPG-HIGH_UP (107%)
VPG-HIGH-DN (105%)
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
PG
High = Power Good
Low = Fault
Figure 7-1. Static Power-Good Operation
12
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Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
< tPG
PG
tPG
tPG
tPG
Figure 7-2. Power-Good-Timing Behavior
7.3.2 Enable and Start-up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see Section 8.2.2.10). Applying a voltage of
≥ VEN-VCC_H causes the device to enter standby mode, powering the internal VCC, but not producing an output
voltage. Increasing the EN voltage to VEN-H fully enables the device, allowing it to enter start-up mode and start
the soft-start period. When the EN input is brought below VEN-H by VEN-HYS, the regulator stops running and
enters standby mode. Further decrease in the EN voltage to below VEN-VCC-L completely shuts down the device.
This behavior is shown in Figure 7-3. The EN input can be connected directly to VIN if this feature is not needed.
This input must not be allowed to float. The values for the various EN thresholds can be found in Section 6.5.
The LMR33630-Q1 uses a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. A typical start-up waveform is shown in Figure 7-4, indicating typical
timings. The rise time of the output voltage is about 4 ms (see the Section 6.5).
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EN
VEN-H
VEN-H ± VEN-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5V
0
VOUT
VOUT
0
Figure 7-3. Precision Enable Behavior
EN, 3V/Div
VOUT, 2V/Div
PG, 5V/Div
Inductor Current, 3A/Div
2ms/Div
Figure 7-4. Typical Start-up Behavior VIN = 12 V, VOUT = 5 V, IOUT = 3 A
7.3.3 Current Limit and Short Circuit
The LMR33630-Q1 incorporates both peak and valley inductor current limit to provide protection to the device
from overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor
current runaway during short circuits on the output, while both peak and valley limits work together to limit the
maximum output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode
is used for sustained short circuits. Finally, a zero current detector is used on the low-side power MOSFET to
implement DEM at light loads (see the Glossary). The typical value of this current limit is found under IZC in
Section 6.5.
When the device is overloaded, the valley of the inductor current may not reach below ILIMIT (see Section
6.5) before the next clock cycle. When this occurs, the valley current limit control skips that cycle, causing
the switching frequency to drop. Further overload causes the switching frequency to continue to drop, and the
inductor ripple current to increase. When the peak of the inductor current reaches the high-side current limit, ISC
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(see Section 6.5), the switch duty cycle is reduced and the output voltage falls out of regulation. This represents
the maximum output current from the converter and is given approximately by Equation 1.
IOUT
max
ILIMIT ISC
2
(1)
If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
into hiccup mode. In this mode, the device stops switching for tHC (see Section 6.7), or about 94 ms and then
goes through a normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit
for about 20 ms (typical) and then shuts down again. This cycle repeats, as shown in Figure 7-5 as long as the
short-circuit-condition persists. This mode of operation helps reduce the temperature rise of the device during
a hard short on the output. The output current is greatly reduced during hiccup mode. Once the output short is
removed and the hiccup delay is passed, the output voltage recovers normally as shown in Figure 7-6.
Short triggered
Short Released
Output
Voltage
2V/div
Inductor
Curent
2A/
Inductor
Curent
1A/
50ms/div
50ms/div
Figure 7-5. Inductor Current Burst in Short-Circuit
Mode
Figure 7-6. Short-Circuit Transient and Recovery
7.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR33630-Q1 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC
pin). When VCC reaches about 3.7 V, the device is ready to receive an EN signal and start up. When VCC falls
below about 3 V, the device shuts down, regardless of EN status. Because the LDO is in dropout during these
transitions, the above values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 165°C, the device shuts down; re-start occurs when the temperature falls to about
148°C.
7.4 Device Functional Modes
7.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM. The load current for which the device moves from
PFM to PWM can be found in Section 8.2.3. The output current at which the device changes modes depends
on the input voltage, inductor value, and the nominal switching frequency. For output currents above the curve,
the device is in PWM mode. For currents below the curve, the device is in PFM. The curves apply for a nominal
switching frequency of 400 kHz and the BOM shown in Table 8-3. At higher switching frequencies, the load at
which the mode change occurs is greater. For applications where the switching frequency must be known for a
given condition, the transition between PFM and PWM must be carefully tested before the design is finalized.
In PWM mode, the regulator operates as a constant frequency converter using PWM to regulate the output
voltage. While operating in this mode, the output voltage is regulated by switching at a constant frequency and
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modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and
low output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load.
The duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The periodicity
of these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency
(see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current
required to regulate the output voltage at light loads. PFM results in very good light-load efficiency, but also
yields larger output voltage ripple and variable switching frequency. Also, a small increase in output voltage
occurs at light loads. The actual switching frequency and output voltage ripple depends on the input voltage,
output voltage, and load. Typical switching waveforms in PFM and PWM are shown in Figure 7-7 and Figure 7-8.
See Section 8.2.3 for output voltage variation with load in auto mode.
SW,
5V/Div
SW,
5V/Div
VOUT,
10mV/Div
VOUT,
10mV/Div
Inductor
Current,
0.5A/Div
Inductor
Current,
2A/Div
50µs/Div
2µs/Div
Figure 7-7. Typical PFM Switching Waveforms VIN = Figure 7-8. Typical PWM Switching Waveforms VIN
= 12 V, VOUT = 5 V, IOUT = 3 A, ƒS = 400 kHz
12 V, VOUT = 5 V, IOUT = 10 mA
7.4.2 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage level
approaches the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value (see
Section 6.6). Beyond this point, the switching can become erratic, and the output voltage falls out of regulation.
To avoid this problem, the LMR33630-Q1 automatically reduces the switching frequency to increase the effective
duty cycle and maintain regulation. In this data sheet, the dropout voltage is defined as the difference between
the input and output voltage when the output has dropped by 1% of its nominal value. Under this condition,
the switching frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit
detection threshold is not activated when in dropout mode. Typical dropout characteristics can be found in Figure
7-9, Figure 7-10, Figure 7-11, and Figure 7-12.
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6
0.45
0.4
Drop-Out Voltage (V)
Output Voltage (V)
5.5
5
4.5
1A
4
2A
3.5
3A
0.35
0.3
0.25
0.2
0.15
0.1
5V
0.05
0A
3.3V
3
0
4
4.5
5
5.5
6
6.5
7
Input Voltage (V)
0.5
1
2.4
2.2
2.2
Switching Frequency (MHz)
1.8
1.6
1.4
1.2
1
0.8
0.6
1A
0.4
2A
0.2
2
2.5
3
C011
2
1.8
1.6
1.4
1.2
1
0.8
0.6
1A
0.4
2A
0.2
3A
0
3.5
Figure 7-10. Typical Dropout Voltage versus
Output Current in Frequency Foldback ƒSW = 140
kHz
2.4
2
1.5
Output Current (A)
C017
Figure 7-9. Overall Dropout Characteristic VOUT = 5
V
Switching Frequency (MHz)
0
3A
0
3.5
4
4.5
5
5.5
6
6.5
Input Voltage (V)
7
7.5
8
3.5
4
5
5.5
6
6.5
7
7.5
Input Voltage (V)
C026
Figure 7-11. Typical Switching Frequency in
Dropout Mode VOUT = 3.3 V, fSW = 2.1 MHz
4.5
8
8.5
9
9.5 10
C025
Figure 7-12. Typical Switching Frequency in
Dropout Mode VOUT = 5 V, fSW = 2.1 MHz
7.4.3 Minimum Switch On-Time
Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking
times associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the LMR33630-Q1 automatically reduces the switching frequency when the
minimum on-time limit is reached. This way the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before
frequency foldback occurs is found in Equation 2. The values of tON and fSW can be found in Section 6.5. As
the input voltage is increased, the switch on-time (duty-cycle) reduces to regulate the output voltage. When the
on-time reaches the limit, the switching frequency drops, while the on-time remains fixed. This relationship is
highlighted in Figure 7-13 for a nominal switching frequency of 2.1 MHz.
VIN d
VOUT
t ON ˜ fSW
(2)
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2.6
Switching Frequency (MHz)
2.4
2.2
2
1.8
1.6
1.4
1.2
1A
2A
3A
1
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
Input Voltage (V)
C024
Figure 7-13. Switching Frequency versus Input Voltage VOUT = 3.3 V
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The LMR33630-Q1 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to
select components for the LMR33630-Q1. Alternately, the WEBENCH Design Tool can be used to generate a
complete design. This tool utilizes an iterative design procedure and has access to a comprehensive database of
components. This allows the tool to create an optimized design and allows the user to experiment with various
options.
Note
In this data sheet, the effective value of capacitance is defined as the actual capacitance under
D.C. bias and temperature; not the rated or nameplate values. Use high-quality, low-ESR, ceramic
capacitors with an X5R or better dielectric throughout. All high value ceramic capacitors have a
large voltage coefficient in addition to normal tolerances and temperature effects. Under D.C. bias
the capacitance drops considerably. Large case sizes and/or higher voltage ratings are better in this
regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum
effective capacitance up to the required value. This can also ease the RMS current requirements on
a single capacitor. A careful study of bias and temperature variation of any capacitor bank should be
made in order to ensure that the minimum value of effective capacitance is provided.
8.2 Typical Application
Figure 8-1 shows a typical application circuit for the LMR33630-Q1. This device is designed to function over a
wide range of external components and system parameters. However, the internal compensation is optimized for
a certain range of external inductance and output capacitance. As a quick start guide, Figure 8-1 provide typical
component values for a range of the most common output voltages. The values given in the table are typical.
Other values can be used to enhance certain performance criterion as required by the application. Note that for
the VQFN package, the input capacitors are split and placed on either side of the package; see Section 8.2.2.6
for more details.
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L
VIN
6 V to 36 V
VOUT
SW
VIN
5V
3A
8 µH
CIN
CHF
10 µF
CBOOT
220 nF
COUT
BOOT
EN
4x 22 µF
0.1 µF
RFBT
CFF
PG
100 NŸ
PG
100 NŸ
VCC
CVCC
1 µF
FB
PGND
AGND
RFBB
24.9 NŸ
Figure 8-1. Example Application Circuit (400 kHz)
8.2.1 Design Requirements
Table 8-1 provides the parameters for our detailed design procedure example:
Table 8-1. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V (6 V to 36 V)
Output voltage
5V
Maximum output current
0 A to 3 A
Switching frequency
400 kHz
Table 8-2. Typical External Component Values
ƒSW
(kHz)
VOUT (V)
COUT (RATED
L (µH) CAPACITANC
E)
RFBT (Ω)
RFBB (Ω)
CIN + CHF
CBOOT
CVCC
CFF
400
3.3
6.8
4 × 22 µF
100 k
43.2 k
10 µF + 220 nF
100 nF
1 µF
open
1400
3.3
2.2
2 × 22 µF
100 k
43.2 k
10 µF + 220 nF
100 nF
1 µF
open
2100
3.3
1.2
2 × 22 µF
100 k
43.2 k
10 µF + 220 nF
100 nF
1 µF
open
400
5
8
4 × 22 µF
100 k
24.9 k
10 µF + 220 nF
100 nF
1 µF
open
1400
5
2.2
2 × 22 µF
100 k
24.9 k
10 µF + 220 nF
100 nF
1 µF
open
2100
5
1.5
2 × 22 µF
100 k
24.9 k
10 µF + 220 nF
100 nF
1 µF
open
400
12
15
4 × 22 µF
100 k
9.09 k
10 µF + 220 nF
100 nF
1 µF
open
1400
12
4.7
4 × 10 µF
100 k
9.09 k
10 µF + 220 nF
100 nF
1 µF
open
2100
12
3.3
4 × 10 µF
100 k
9.09 k
10 µF + 220 nF
100 nF
1 µF
open
8.2.2 Detailed Design Procedure
The following design procedure applies to Figure 8-1 and Table 8-1.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR33630-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
20
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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a
more compact design. For this example, 400 kHz was chosen.
8.2.2.3 Setting the Output Voltage
The output voltage of the LMR33630-Q1 is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in Section 6.3. The divider network is comprised of RFBT and RFBB, and
closes the loop between the output voltage and the converter. The converter regulates the output voltage by
holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the divider
is a compromise between excessive noise pick-up and excessive loading of the output. Smaller values of
resistance reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for RFBT is
100 kΩ; with a maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a feedforward capacitor must be
used across this resistor to provide adequate loop phase margin (see Section 8.2.2.9). Once RFBT is selected,
Equation 3 is used to select RFBB. VREF is nominally 1 V (see Section 6.5 for limits).
RFBB
RFBT
ª VOUT
«
¬ VREF
º
1»
¼
(3)
For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ are chosen.
8.2.2.4 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based
on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of
the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current. Note that when selecting the ripple current for applications with much smaller maximum
load than the maximum available from the device, the maximum device current should be used. Equation 4 can
be used to determine the value of inductance. The constant K is the percentage of inductor current ripple. For
this example, K = 0.3 was chosen and an inductance L = 8.1 µH was found; the next standard value of 8 µH was
selected.
L
VIN VOUT
V
˜ OUT
fSW ˜ K ˜ IOUT max VIN
(4)
Ideally, the saturation current rating of the inductor must be at least as large as the high-side switch current
limit, ISC (see Section 6.5). This ensures that the inductor does not saturate even during a short circuit on
the output. When the inductor core material saturates, the inductance falls to a very low value, causing the
inductor current to rise very rapidly. Although the valley current limit, ILIMIT, is designed to reduce the risk of
current run-away, a saturated inductor can cause the current to rise to high values very rapidly. This can lead
to component damage; do not allow the inductor to saturate. Inductors with a ferrite core material have very
hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores
exhibit a soft saturation, allowing for some relaxation in the current rating of the inductor. However, they have
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more core losses at frequencies typically above 1 MHz. In any case, the inductor saturation current must not
be less than the device low-side current limit, ILIMIT (see the Section 6.5). The maximum inductance is limited
by the minimum current ripple required for the current mode control to perform correctly. As a rule-of-thumb, the
minimum inductor ripple current must be no less than about 10% of the device maximum rated current under
nominal conditions.
LMIN t 0.28 ˜
VOUT
fSW
(5)
8.2.2.5 Output Capacitor Selection
The value of the output capacitor and the ESR of the capacitor determine the output voltage ripple and load
transient performance. The output capacitor bank is usually limited by the load transient requirements, rather
than the output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance
and an upper bound on the ESR, which is required to meet a specified load transient.
COUT t
ESR d
D
fSW
'IOUT
˜ 'VOUT ˜ K
º
K2
˜ 2 D»
12
»¼
ª
˜«1 D ˜ 1 K
«¬
2 K ˜ 'VOUT
ª
2 ˜ 'IOUT «1 K
«¬
K2
12
§
1 ·º
¸¸»
˜ ¨¨1
© (1 D) ¹»¼
VOUT
VIN
(6)
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = ripple factor from Section 8.2.2.4
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the peak-to-peak
output voltage ripple; Vr.
Vr # 'IL ˜ ESR 2
1
8 ˜ fSW ˜ COUT
2
(7)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example, a ΔVOUT ≤ 250 mV for an output current step of ΔIOUT = 2 A is required. Equation 6 gives a
minimum value of 52 µF and a maximum ESR of 0.11 Ω. Assuming a 20% tolerance and a 10% bias de-rating,
you arrive at a minimum capacitance of 72 µF. This can be achieved with a bank of 4 × 22-µF, 16-V ceramic
capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response.
Ceramic capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic
capacitor can be placed in parallel with the ceramics to help build up the required value of capacitance. In
general, use a capacitor of at least 10 V for output voltages of 3.3 V or less and a capacitor of 16 V or more for
output voltages of 5 V and above.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and Bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range
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of 1 nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board
parasitics.
The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000
µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of
start-up at full load and loop stability must be performed.
8.2.2.6 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the
ripple current and isolating switching noise from other circuits. A minimum of 10 µF of ceramic capacitance is
required on the input of the LMR33630-Q1. This must be rated for at least the maximum input voltage that the
application requires; preferably twice the maximum input voltage. This capacitance can be increased to help
reduce input voltage ripple and maintain the input voltage during load transients. In addition, a small case size,
220-nF ceramic capacitor must be used at the input, as close as possible to the regulator. This provides a high
frequency bypass for the control circuits internal to the device. For this example, a 4.7-µF, 50-V, X7R (or better)
ceramic capacitor is chosen. The 220 nF must also be rated at 50 V with an X7R dielectric. The VQFN (RNX)
package provides two input voltage pins and two power ground pins on opposite sides of the package. This
allows the input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus
improving the effectiveness of the input bypassing. In this example, a single 4.7-µF and two 100-nF ceramic
capacitors at each VIN/PGND location.
Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is
especially true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR
of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of
this additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high
impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
worst case RMS value of this current can be calculated from Equation 8 and must be checked against the
manufacturers' maximum ratings.
IRMS #
IOUT
2
(8)
8.2.2.7 CBOOT
The LMR33630-Q1 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This
capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic
capacitor of 100 nF and at least 10 V is required.
8.2.2.8 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, avoid
loading this output with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see Section 7.3.1). A value of 100 kΩ is a good choice in this case. The nominal output
voltage on VCC is 5 V; see Section 6.5 for limits. Do not short this output to ground or any other external voltage.
8.2.2.9 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help to mitigate this effect. Equation 9 can be used to estimate the value of CFF.
The value found with Equation 9 is a starting point; use lower values to determine if any advantage is gained by
the use of a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feed-forward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.
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VOUT ˜ COUT
CFF
120 ˜ RFBT ˜
VREF
VOUT
(9)
8.2.2.10 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can
be accomplished by using the circuit shown in Figure 8-2. The input voltage at which the device turns on is
designated VON while the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100
kΩ and then Equation 10 is used to calculate RENT and VOFF.
VIN
RENT
EN
RENB
Figure 8-2. Setup for External UVLO Application
R ENT
§ V ON
¨¨
© VEN H
·
1¸¸ ˜ R ENB
¹
V OFF
§
V ON ˜ ¨¨ 1
©
VEN HYS
VEN H
·
¸¸
¹
(10)
where
•
•
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
8.2.2.11 Maximum Ambient Temperature
As with any power conversion device, the LMR33630-Q1 dissipates internal power while operating. The effect
of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance,
RθJA, of the device and PCB combination. The maximum internal die temperature for the LMR33630-Q1 must
be limited to 125°C. This establishes a limit on the maximum device power dissipation and therefore the
load current. Equation 11 shows the relationships between the important parameters. It is easy to see that
larger ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and
IC Package Thermal Metrics Application Report, the value of RθJA given in Section 6.4 is not valid for design
purposes and must not be used to estimate the thermal performance of the application. The values reported in
that table were measured under a specific set of conditions that are rarely obtained in an actual application.
IOUT
MAX
TJ TA
1
K
˜
˜
R TJA
1 K VOUT
(11)
where
•
24
η = efficiency
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3.5
65
3
Maximum Output Current (A)
70
60
55
R
JA (ƒC/w)
The effective RθJA is a critical parameter and depends on many factors such as power dissipation, air
temperature/flow, PCB area, copper heat-sink area, number of thermal vias under the package, and adjacent
component placement, just to mention just a few. Due to the ultra-miniature size of the VQFN (RNX) package, a
DAP is not available. This means that this package exhibits a somewhat large value RθJA. A typical example of
RθJA vs copper board area can be found in Figure 8-3. The copper area given in the graph is for each layer; the
top and bottom layers are 2 oz. copper each, while the inner layers are 1 oz. A typical curve of maximum output
current vs. ambient temperature is shown in Figure 8-4. This data was taken with a device/PCB combination
giving an RθJA of about 50°C/W. It must be remembered that the data given in these graphs are for illustration
purposes only, and the actual performance in any given application depends on all of the previously mentioned
factors.
50
45
2.5
2
1.5
1
0.5
RNX, 4L
40
0
10
20
30
40
Copper Area
(cm2)
50
60
70
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
C005
Figure 8-3. RθJA versus Copper Board Area for the
VQFN (RNX) Package
Ambient Temperature (ƒC)
VIN = 12 V
ƒSW = 400 kHz
C006
VOUT = 5 V
RθJA = 50°C/W
Figure 8-4. Maximum Output Current versus
Ambient Temperature
Use the following resources as a guide to optimal thermal PCB design and estimating RθJA for a given
application environment:
•
•
•
•
•
•
•
Thermal Design by Insight not Hindsight
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Semiconductor and IC Package Thermal Metrics
Thermal Design Made Simple with LM43603 and LM43602
PowerPAD™ Thermally Enhanced Package
PowerPAD™ Made Easy
Using New Thermal Metrics
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8.2.3 Application Curves
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C. The circuit is shown in Figure
8-29, with the appropriate BOM from Table 8-3.
80
75
70
8V
65
0.01
0.1
1
VOUT = 5 V
400 kHz
12V
24V
36V
50
0.001
10
Output Current (A)
8V
55
36V
50
0.001
70
60
24V
55
75
65
12V
60
80
RNX Package
VOUT = 3.3 V
95
90
90
85
85
Efficiency (%)
Efficiency (%)
100
95
80
75
70
8V
65
55
1
80
75
70
5V
12V
24V
36V
50
0.001
10
Output Current (A)
RNX Package
VOUT = 3.3 V
95
90
90
85
85
Efficiency (%)
Efficiency (%)
100
80
75
70
8V
65
55
1
80
75
70
8V
12V
24V
10
36V
50
0.001
0.01
RNX Package
0.1
Output Current (A)
C010
VOUT = 3.3 V
Figure 8-9. Efficiency
26
C020
55
36V
2.1 MHz
10
RNX Package
60
24V
VOUT = 5 V
1.4 MHz
65
12V
60
0.1
1
Figure 8-8. Efficiency
95
Output Current (A)
0.1
Output Current (A)
100
0.01
0.01
C019
Figure 8-7. Efficiency
50
0.001
C008
55
36V
1.4 MHz
10
RNX Package
60
24V
VOUT = 5 V
400 kHz
65
12V
60
0.1
1
Figure 8-6. Efficiency
100
0.01
0.1
Output Current (A)
C007
Figure 8-5. Efficiency
50
0.001
0.01
2.1 MHz
1
10
C009
RNX Package
Figure 8-10. Efficiency
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5.06
32
8V
5.055
Output Voltage (V)
Input Supply Current (µA)
12V
5.05
24V
5.045
36V
5.04
5.035
5.03
5.025
5.02
30
28
26
24
22
5.015
5V
5.01
0
0.5
1
1.5
2
2.5
3
20
0
3.5
Output Current (A)
10
15
20
25
30
35
40
Input Voltage (V)
C011
VOUT = 5 V
VOUT = 5 V
Figure 8-11. Line and Load Regulation
IOUT = 0 A
C017
RFBT = 1 MΩ
Figure 8-12. Input Supply Current
0.6
10000
Switching Frequency (kHz)
0.5
Output Current (A)
5
0.4
0.3
9
PWM
0.2
PFM
;
0.1
1000
100
10
8V
1
12V
18V
5V
0
0
5
10
15
20
25
30
35
Input Voltage (V)
VOUT = 5 V
0.1
0.00001
40
0.0001
0.01
0.1
1
10
Output Current (A)
C012
ƒSW = 400 kHz
VOUT = 5 V
Figure 8-13. Mode Change Thresholds
0.001
C022
ƒSW = 2100 kHz
Figure 8-14. Switching Frequency versus Output
Current
VOUT,
300mV/Div
VOUT,
300mV/Div
Output Current,
1A/Div
Output Current,
1A/Div
100µs/Div
100µs/Div
0
0
VIN = 12 V
tf = tr = 2 µs
VOUT = 5 V
IOUT = 0 A to 3 A
Figure 8-15. Load Transient
VIN = 12 V
tf = tr = 2 µs
VOUT = 5 V
IOUT = 1 A to 3 A
Figure 8-16. Load Transient
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32
3.35
5V
12V
3.34
24V
3.335
36V
Input Supply Current (µA)
Output Voltage (V)
3.345
3.33
3.325
3.32
3.315
30
28
26
24
22
3.3V
20
0
3.31
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
5
10
15
C011
VOUT = 3.3 V
VOUT = 3.3 V
20
25
30
Input Voltage (V)
IOUT = 0 A
35
40
C016
RFBT = 1 MΩ
Figure 8-18. Input Supply Current
Figure 8-17. Line and Load Regulation
0.8
10000
Switching Frequency (kHz)
Output Current (A)
0.7
0.6
0.5
0.4
9
PWM
0.3
0.2
PFM
;
0.1
0
0
5
10
15
100
10
5V
1
12V
18V
3.3V
20
25
30
35
Input Voltage (V)
VOUT = 3.3 V
1000
0.1
0.00001
40
0.0001
VOUT = 3.3 V
A.
Figure 8-19. Mode Change Thresholds
0.01
0.1
1
10
Output Current (A)
C012
ƒSW = 400 kHz
0.001
C023
ƒSW = 2100 kHz
Figure 8-20. Switching Frequency versus Output
Current
VOUT,
300mV/Div
VOUT,
300mV/Div
Output Current,
1A/Div
Output Current,
1A/Div
100µs/Div
0
VIN = 12 V
tf = tr = 2 µs
VOUT = 3.3 V
IOUT = 0 A to 3 A
Figure 8-21. Load Transient
28
100µs/Div
0
VIN = 12 V
VOUT = 3.3V
tf = tr = 2 µs
IOUT = 1 A to 3 A
Figure 8-22. Load Transient
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VIN = 12 V
VOUT = 5 V
ƒSW = 400 kHz
IOUT = 3 A
RNX package
Figure 8-23. Conducted EMI
VIN = 12 V
VOUT = 5 V
ƒSW = 400 kHz
IOUT = 3 A
RNX package
Figure 8-25. Radiated EMI Biconical Antenna
(Vertical)
VIN = 12 V
VOUT = 5 V
ƒSW = 400 kHz
IOUT = 3 A
RNX package
Figure 8-27. Radiated EMI Log-periodic Antenna
(Vertical)
VIN = 12 V
VOUT = 5 V
ƒSW = 400 kHz
IOUT = 3 A
RNX package
Figure 8-24. Radiated EMI Biconical Antenna
(Horizontal)
VIN = 12 V
VOUT = 5 V
ƒSW = 400 kHz
IOUT = 3 A
RNX package
Figure 8-26. Radiated EMI Log-periodic Antenna
(Horizontal)
VIN = 12 V
VOUT = 5 V
ƒSW = 400 kHz
IOUT = 3 A
RNX package
Figure 8-28. Radiated EMI
Rod Antenna
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L
VIN
VIN
VOUT
SW
U1
CBOOT
CIN
CHF
COUT
BOOT
EN
0.1 µF
RFBT
PG
100 NŸ
PG
100 NŸ
VCC
CVCC
1 µF
FB
PGND
AGND
RFBB
Figure 8-29. Circuit for Application Curves
Table 8-3. BOM for Typical Application Curves RNX Package(1)
VOUT
(1)
FREQUENCY
RFBB
COUT
CIN + CHF
L
U1
3.3 V
400 kHz
43.3 kΩ
4 × 22 µF
3.3 V
1400 KHz
43.3 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
6.8 µH, 14 mΩ
LMR33630ARNX
2 × 4.7 µF + 2 × 100 nF
2.2 µH, 11.4 mΩ
LMR33630BRNX
3.3 V
2100 kHz
43.3 kΩ
5V
400 kHz
24.9 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
1.2 µH, 7 mΩ
LMR33630CRNX
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
8 µH, 25 mΩ
LMR33630ARNX
5V
1400 KHz
5V
2100 kHz
24.9 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
2.2 µH, 11.4 mΩ
LMR33630BRNX
24.9 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
1.5 µH, 8.2 mΩ
LMR33630CRNX
The values in this table were selected to enhance certain performance criteria and may not represent typical values.
+
100µF
0.1µF
4.7µF
3.3µF
2x 0.1µF
3x 4.7µF
2x 0.1µF
Input Supply
2x 4.7µF
Ferrite Bead
Input to
Regulator
Figure 8-30. Typical Input EMI Filter
Filter Used Only for EMI Measurements Found in Application Curves
8.3 What to Do and What Not to Do
•
•
•
•
•
•
•
30
Don't: Exceed the Absolute Maximum Ratings.
Don't: Exceed the ESD Ratings.
Don't: Exceed the Recommended Operating Conditions.
Don't: Allow the EN input to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Don't: Use the value of RθJA given in the Thermal Information table to design your application. Use the
information in the Maximum Ambient Temperature section.
Do: Follow all the guidelines and suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see Section 11.3).
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9 Power Supply Recommendations
The characteristics of the input supply must be compatible with Section 6.1 and Section 6.3 found in this data
sheet. In addition, the input supply must be capable of delivering the required input current to the loaded
regulator. The average input current can be estimated with Equation 12, where η is the efficiency.
IIN
VOUT ˜ IOUT
VIN ˜ K
(12)
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic
input capacitors, can form an under damped resonant circuit, resulting in overvoltage transients at the input to
the regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient
is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause
the regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and/or use an aluminum or tantalum input capacitor in parallel
with the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and
reduce any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and
help to hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The user guide
AN-2162 Simple Success With Conducted EMI From DCDC Converters provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this
device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than
the output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharges through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then a Schottky diode between the input supply and the output should be used.
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10 Layout
10.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter,
the most critical PCB feature is the loop formed by the input capacitor or input capacitors, and power ground,
as shown in Figure 10-1. This loop carries large transient currents that can cause large transient voltages when
reacting with the trace inductance. These unwanted transient voltages will disrupt the proper operation of the
converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
to reduce the parasitic inductance. Figure 10-2 shows a recommended layout for the critical components of the
LMR33630-Q1.
1. Place the input capacitor or capacitors as close as possible to the VIN and GND terminals. VIN and
GND pins are adjacent, simplifying the input capacitor placement. With the VQFN package there are two
VIN/PGND pairs on either side of the package. This provides for a symmetrical layout and helps minimize
switching noise and EMI generation. A wide VIN plane must be used on a lower layer to connect both of the
VIN pairs together to the input supply; see the layout example.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the
BOOT and SW pins. It is important to route the SW connection under the device to the NC pin, and use this
path to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF,
if used, physically close to the device. The connections to FB and GND must be short and close to those
pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act
as a heat dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat sinking. As stated in Section 8.2.2.11, enough copper
area must be used to ensure a low RθJA, commensurate with the maximum load current and ambient
temperature. Make the top and bottom PCB layers with two-ounce copper; and no less than one ounce.
If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the
inner layer heat-spreading ground planes.
8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node should be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
•
•
•
•
32
Layout Guidelines for Switching Power Supplies
Simple Switcher PCB Layout Guidelines
Construction Your Power Supply- Layout Considerations
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x
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VIN
KEEP
CURRENT
LOOP
SMALL
CIN
SW
GND
Figure 10-1. Current Loops with Fast Edges
10.1.1 Ground and Thermal Considerations
As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass
capacitors. PGND pins are connected directly to the source of the low side MOSFET switch, and also connected
directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching
frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be
constrained to one side of the ground planes. The other side of the ground plane contains much less noise and
must be used for sensitive routes.
Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat
dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz /
1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current
conduction impedance, proper shielding, and lower thermal resistance.
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10.2 Layout Example
VOUT
VOUT
INDUCTOR
COUT
COUT
COUT
COUT
GND
GND
CIN
CIN
CHF
12
11
2
10
3
9
4
8
5
6
VIN
EN
PGOOD
7
RFBT
CBOOT
1
VIN
CHF
CVCC
RFBB
GND
HEATSINK
GND
HEATSINK
INNER GND PLANE
Top Trace/Plane
Inner GND Plane
VIN Strap on Inner Layer
Top
VIA to Signal Layer
Inner GND Plane
VIA to GND Planes
VIN Strap and
GND Plane
VIA to VIN Strap
Signal traces
and GND Plane
Trace on Signal Layer
Figure 10-2. Example Layout for VQFN Package
34
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM33630-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Thermal Design by Insight not Hindsight
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
• Semiconductor and IC Package Thermal Metrics
• Thermal Design Made Simple with LM43603 and LM43602
• PowerPADTM Thermally Enhanced Package
• PowerPADTM Made Easy
• Using New Thermal Metrics
• Layout Guidelines for Switching Power Supplies
• Simple Switcher PCB Layout Guidelines
• Construction Your Power Supply- Layout Considerations
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.5 Trademarks
HotRod™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LMR33630-Q1
35
LMR33630-Q1
www.ti.com
SNVSB26C – JUNE 2018 – REVISED OCTOBER 2020
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
36
This glossary lists and explains terms, acronyms, and definitions.
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LMR33630-Q1
LMR33630-Q1
www.ti.com
SNVSB26C – JUNE 2018 – REVISED OCTOBER 2020
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LMR33630-Q1
37
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMR33630AQRNXRQ1
ACTIVE
VQFN-HR
RNX
12
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
Z630AQ
LMR33630AQRNXTQ1
ACTIVE
VQFN-HR
RNX
12
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
Z630AQ
LMR33630BQRNXRQ1
ACTIVE
VQFN-HR
RNX
12
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
Z630BQ
LMR33630BQRNXTQ1
ACTIVE
VQFN-HR
RNX
12
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
Z630BQ
LMR33630CQRNXRQ1
ACTIVE
VQFN-HR
RNX
12
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
Z630CQ
LMR33630CQRNXTQ1
ACTIVE
VQFN-HR
RNX
12
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
Z630CQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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