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LMR36006-Q1
SNVSAY7C – AUGUST 2018 – REVISED OCTOBER 2019
LMR36006-Q1 4.2-V to 60-V, 0.6-A Ultra-Small Synchronous Step-Down Converter
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
AEC-Q100-qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Designed for automotive applications
– Junction temperature range –40°C to +150°C
– Protection features: thermal shutdown, input
undervoltage lockout, cycle-by-cycle current
limit, hiccup short-circuit protection
– 0.2-V dropout with 0.6-A load (typical)
– ±1.5% reference voltage tolerance
– 3.3-V fixed-output voltage option available
Suited for scalable power supplies
– Pin compatible with:
– LMR36015-Q1 (60 V, 1.5 A)
– LMR33620/30-Q1 (36 V, 2 A, or 3 A)
– 400-kHz, 2.1-MHz frequency options
Integration reduces solution size and cost
– Small, 2-mm × 3-mm VQFN package with
wettable flanks
– Few external components
Low power dissipation across load spectrum
– 94% efficiency at 400 kHz (12VIN, 5VOUT, 0.6A)
– Increased light load efficiency in PFM
– Low operating quiescent current of 26 µA
Optimized for ultra low EMI requirements
– Meets CISPR25 class 5 standard
– Hotrod™ package minimizes switch node
ringing
– Parallel input path minimizes parasitic
inductance
– Spread spectrum reduces peak emissions
Create a custom design using the LMR36006-Q1
with the WEBENCH® Power Designer
ADAS camera module
Body control module
3 Description
The LMR36006-Q1 regulator is an easy-to-use,
synchronous, step-down DC/DC converter. With
integrated high-side and low-side power MOSFETs,
up to 0.6 A of output current is delivered over a wide
input voltage range of 4.2 V to 60 V. Tolerance goes
up to 66 V.
The LMR36006-Q1 uses peak-current-mode control
to provide optimal efficiency and output voltage
accuracy. Advanced high speed circuitry allows the
LMR36006-Q1 to regulate from an input of 20 V to an
output of 5 V at a fixed frequency of 2.1 MHz.
Precision enable gives flexibility by enabling a direct
connection to the wide input voltage or precise
control over device start-up and shutdown. The
power-good flag, with built-in filtering and delay,
offers a true indication of system status eliminating
the requirement for an external supervisor.
The LMR36006-Q1 is in a HotRod™ package which
enables low EMI, higher efficiency, and the smallest
package to die ratio. The device requires few external
components and has a pinout designed for simple
PCB layout. The small solution size and feature set of
the LMR36006-Q1 are designed to simplify
implementation for a wide range of end equipment.
Device Information(1)
PART NUMBER
LMR36006-Q1
PACKAGE
BODY SIZE (NOM)
VQFN-HR (12)
2.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
BOOT
VIN
VIN
CIN
CBOOT
EN
VOUT
SW
L1
COUT
PGND
LMR36006-Q1
PG
VCC
RFBT
CVCC
FB
RFBB
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR36006-Q1
SNVSAY7C – AUGUST 2018 – REVISED OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
5
5
5
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
System Characteristics .............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
9.3 What to Do and What Not to Do ............................. 34
10 Power Supply Recommendations ..................... 35
11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
11.2 Layout Example .................................................... 38
12 Device and Documentation Support ................. 39
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
40
40
40
40
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2019) to Revision C
Page
•
Added EMI description to the Features .................................................................................................................................. 1
•
Added Figure 34 through Figure 43 ..................................................................................................................................... 29
Changes from Revision A (November 2018) to Revision B
•
Updated package quantities in Device Comparison Table. ................................................................................................... 3
Changes from Original (April 2018) to Revision A
•
2
Page
Page
First release of production-data data sheet ........................................................................................................................... 1
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SNVSAY7C – AUGUST 2018 – REVISED OCTOBER 2019
5 Device Comparison Table
ORDERABLE PART
NUMBER
OUTPUT VOLTAGE
SPREAD
SPECTRUM
FPWM
fSW
PACKAGE QUANTITY
LMR36006AQRNXTQ1
Adjustable
No
No
400 kHz
250
3000
LMR36006AQRNXRQ1
Adjustable
No
No
400 kHz
LMR36006FSCQRNXTQ1
Adjustable
Yes
Yes
2.1 MHz
250
LMR36006FSCQRNXRQ1
Adjustable
Yes
Yes
2.1 MHz
3000
LMR36006FSC3RNXTQ1
3.3-V fixed
Yes
Yes
2.1 MHz
250
LMR36006FSC3RNXRQ1
3.3-V fixed
Yes
Yes
2.1 MHz
3000
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6 Pin Configuration and Functions
RNX Package
12-Pin VQFN-HR
Top View
SW
12
5
PGND 1
11 PGND
10 VIN
VIN 2
NC
3
9 EN
BOOT
4
8 PG
5
6
7
VCC AGND FB
Pin Functions
NO.
NAME
TYPE
DESCRIPTION
1, 11
PGND
G
Power ground terminal. Connect to system ground and AGND. Connect to CIN with short wide traces.
2, 10
VIN
P
Input supply to regulator. Connect to CIN with short wide traces.
3
NC
—
Connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT capacitor to the
SW pin. This pin has no internal connection to the regulator.
4
BOOT
P
Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this
pin to the SW pin. Connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT
capacitor to the SW pin.
5
VCC
P
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to
GND.
6
AGND
G
Analog ground for regulator and system. Ground reference for internal references and logic. All electrical
parameters are measured with respect to this pin. Connect to system ground on PCB.
7
FB
A
Feedback input to regulator. Connect to output voltage node for fixed VOUT applications. Connect to tap
point of feedback voltage divider. DO NOT FLOAT. DO NOT GROUND.
8
PG
A
Open drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. Goes low when EN = Low. Can be open or grounded when
not used.
9
EN
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; DO NOT FLOAT.
12
SW
P
Regulator switch node. Connect to power inductor. Connect the SW pin to NC on the PCB. This
simplifies the connection from the CBOOT capacitor to the SW pin.
A = Analog, P = Power, G = Ground
4
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating junction temperature range of -40°C to 150°C (unless otherwise noted) (1)
MIN
MAX
Input voltage
VIN to PGND
–0.3
66
V
Input voltage
EN to AGND
–0.3
66.3
V
Input voltage
FB to AGND
–0.3
5.5
V
Input voltage
PG to AGND
–0.3
22
V
Input voltage
AGND to PGND
–0.3
0.3
V
Output voltage
SW to PGND
–0.3
66.3
V
Output voltage
SW to PGND less than 10-ns transients
–3.5
66.3
V
Output voltage
CBOOT to SW
–0.3
5.5
V
Output voltage
VCC to AGND
–0.3
5.5
V
Junction Temperature TJ
-40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
V(ESD)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
(1)
VALUE
UNIT
±2500
V
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 ℃ to 150 ℃ (unless otherwise noted) (1)
MIN
MAX
4.2
60
V
EN to PGND (2)
0
60
V
(2)
0
18
V
0
0.6
A
VIN to PGND
Input voltage
PG to PGND
Output current
(1)
(2)
IOUT
UNIT
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
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7.4 Thermal Information
LMR36006
THERMAL METRIC (1)
RNX (VQFN-HR)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
72.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.9
°C/W
RθJB
Junction-to-board thermal resistance
23.3
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
23.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
18
26
36
UNIT
SUPPLY VOLTAGE (VIN PIN)
IQ-nonSW
Operating quiescent current (nonswitching) (2)
VEN = 3.3 V (PFM variant only)
ISD
Shutdown quiescent current;
measured at VIN pin
VEN = 0 V
5
µA
µA
ENABLE (EN PIN)
VEN-VCC-H
Enable input high level for VCC output
VENABLE rising
VEN-VCC-L
Enable input low level for VCC output
VENABLE falling
0.3
1.14
V
VEN-VOUT-H
Enable input high level for VOUT
VENABLE rising
1.157
VEN-VOUT-HYS
Enable input hysteresis for VOUT
Hysteresis below VENABLE-H; falling
110
mV
ILKG-EN
Enable input leakage current
VEN = 3.3V
0.2
nA
V
1.231
1.3
V
INTERNAL LDO (VCC PIN)
VCC
VCC-UVLORising
VCC-UVLOFalling
Internal VCC voltage
6 V ≤ VIN ≤ 60 V
Internal VCC undervoltage lockout
Internal VCC undervoltage lockout
4.75
5
5.25
V
VCC rising
3.6
3.8
4.0
V
VCC falling
3.1
3.3
3.5
V
3.23
3.3
3.37
V
0.985
1
1.015
V
1.8
µA
VOLTAGE REFERENCE (FB PIN)
VOUT-3.3V-
Output voltage
Fixed
VFB
Feedback voltage
ILKG-VOUT-
Feedback leakage current
VOUT = 3.3 V (Fixed Option)
1.4
Feedback leakage current
FB = 1 V
0.2
3.3V-Fixed
ILKG-FB
nA
CURRENT LIMITS AND HICCUP
ISC
High-side current limit (3)
0.8
(3)
0.6
ILS-LIMIT
Low-side current limit
IPEAK-MIN
Minimum inductor peak current (3)
IL-NEG
Negative current limit (3)
(1)
(2)
(3)
6
1
1.2
A
0.8
0.95
A
0.18
FPWM variant only
-0.95
–0.6
A
–0.25
A
MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
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Electrical Characteristics (continued)
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP
Power-Good upper threshold - rising
% of FB voltage
105%
107%
110%
VPG-LOW-DN
Power-Good lower threshold - falling
% of FB voltage
90%
93%
95%
VPG-HYS
Power-Good hysteresis (rising &
falling)
% of FB voltage
TPG
Power-Good rising/falling edge
deglitch delay
VPG-VALID
Minimum input voltage for proper
Power-Good function
RPG
Power-Good on-resistance
VEN = 2.5 V
RPG
Power-Good on-resistance
VEN = 0 V
FOSC
Internal oscillator frequency
2.1-MHz variant
FOSC
Internal oscillator frequency
400-kHz variant
RDS-ON-HS
High-side MOSFET ON-resistance
RDS-ON-LS
Low-side MOSFET ON-resistance
2%
80
140
200
µs
2
V
80
165
Ω
35
90
Ω
1.95
2.1
2.35
MHz
340
400
460
kHz
IOUT = 0.5 A
225
435
mΩ
IOUT = 0.5 A
150
280
mΩ
OSCILLATOR
MOSFETS
7.6 Timing Requirements
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
MIN
NOM
MAX
UNIT
tON-MIN
Minimum switch on-time
55
83
tOFF-MIN
Minimum switch off-time
53
73
ns
tON-MAX
Maximum switch on-time
7
12
µs
tSS
Internal soft-start time
4.5
6
ms
(1)
3
ns
MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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7.7 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40℃ to 150℃. These specifications are not ensured by production
testing.
PARAMETER
VIN
Operating input voltage range
VOUT
Adjustable output voltage
regulation (1)
VOUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.2
60
PFM operation
–1.5%
2.5%
Adjustable output voltage
regulation (1)
FPWM operation
–1.5%
1.5%
VOUT
Voltage regulation for VOUT = 3.3 V
fixed (1)
FPWM operation
3.28
ISUPPLY
Input supply current when in
regulation
VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
DMAX
Maximum switch duty cycle (2)
VHC
FB pin voltage required to trip shortcircuit hiccup mode
0.4
V
tHC
Time between current-limit hiccup
burst
94
ms
tD
Switch voltage dead time
2
ns
FsSS
Frequency span of spread spectrum
operation
±4
%
FrSS
Triangular spread spectrum
repetition frequency
16
kHz
TSD
Thermal shutdown temperature
Shutdown temperature
170
°C
TSD
Thermal shutdown temperature
Recovery temperature
158
°C
(1)
(2)
8
3.33
26
3.37
V
V
µA
98%
Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to 0.6A
In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN =
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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7.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C. VIN = 24 V.
30
10
29
9
Shutdown Current (µA)
Quiescent Current (µA)
28
27
26
25
24
23
8
7
6
5
4
22
25C
150C
-40C
3
21
2
20
5
10
15
20
25 30 35 40
Input Voltage (V)
45
50
55
5
60
10
20
LMR3
25 30 35 40
Input Voltage (V)
45
50
55
60
Shut
EN = 0 V
VFB = 1 V
Figure 2. Shutdown Supply Current
Figure 1. Non-Switching Input Supply Current
1.5
1
1.3
0.8
Current (A)
Current (A)
15
1.1
0.9
0.6
0.4
0.2
0.7
0.5
-40
0
40
80
Temperatuer (°C)
120
0
-40
150
hs-c
0
40
80
Temperature (°C)
120
150
ls-c
VIN = 24 V
VIN = 24 V
Figure 4. Low Side Current Limit
Figure 3. High Side Current Limit
1.02
370
1.016
Peak Inductor Current (mA)
1.012
Voltage (V)
1.008
1.004
1
0.996
0.992
0.988
320
270
220
170
25C
150C
-40C
0.984
0.98
-40
120
0
40
80
Temperature (°C)
120
150
5
10
15
vref
IOUT = 0 A
Figure 5. Reference Voltage Drift
20
25 30 35 40
Input Voltage (V)
VOUT = 3.3 V
45
50
55
LMR3
ƒSW = 2100 kHz
Figure 6. IPEAK-MIN
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8 Detailed Description
8.1 Overview
The LMR36006-Q1 is a synchronous peak-current-mode buck regulator designed for a wide variety of
automotive applications. The regulator automatically switches modes between PFM and PWM depending on
load. At heavy loads, the device operates in PWM at a constant switching frequency. At light loads the mode
changes to PFM, with diode emulation allowing DCM. This reduces the input supply current and keeps efficiency
high. The device features internal loop compensation which reduces design time and requires fewer external
components than externally compensated regulators.
The LMR36006-Q1 is designed with a flip-chip or HotRod™ technology, greatly reducing the parasitic inductance
of pins. In addition, the layout of the device allows for reduction in the radiated noise generated by the switching
action through partial cancellation of the current generated magnetic field. As a result the switch-node waveform
exhibits less overshoot and ringing.
2V/div
50ns/div
BW:500MHz
Figure 7. Switch Node Waveform
10
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8.2 Functional Block Diagram
VCC
INT. REG.
BIAS
OSCILLATOR
EN
VIN
ENABLE
LOGIC
BOOT
HS CURRENT
SENSE
1.0V
Reference
ERROR
AMPLIFIER
FB
+
-
+
-
PG
PWM
COMP.
CONTROL
LOGIC
PFM MODE
CONTROL
SW
DRIVER
LS CURRENT
SENSE
POWER GOOD
CONTROL
AGND
PGND
8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36006-Q1 can be used to reset a system
microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault
conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents
false flag operation for short excursions of the output voltage, such as during line and load transients. Output
voltage excursions lasting less than tPG do not trip the power-good flag. Power-good operation can best be
understood by reference to Figure 8 and Figure 9. Note that during initial power-up a delay of about 4 ms
(typical) is inserted from the time that EN is asserted to the time that the power-good flag goes high. This delay
only occurs during start-up and is not encountered during normal operation of the power-good function.
The power-good output consists of an open drain NMOS; requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT, through an appropriate resistor, as desired. If this function
is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4
mA.
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Feature Description (continued)
VOUT
VPG-HIGH_UP (107%)
VPG-HIGH-DN (105%)
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
PG
High = Power Good
Low = Fault
Figure 8. Static Power-Good Operation
12
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Feature Description (continued)
Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help to mitigate this effect. Equation 9 can be used to estimate the value of CFF.
The value found with Equation 9 is a starting point; use lower values to determine if any advantage is gained by
the use of a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feed-forward Capacitor Application Report is helpful when experimenting with a feed-forward capacitor.
VOUT ˜ COUT
CFF
VREF
120 ˜ RFBT ˜
VOUT
(9)
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9.2.1.2.9.1 External UVLO
In some cases an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in Figure 20 can be used. The input voltage at which the device turns
on is designated VON; while the turnoff voltage is VOFF. First a value for RENB is chosen in the range of 10 kΩ to
100 kΩ and then Equation 10 is used to calculate RENT and VOFF.
VIN
RENT
EN
RENB
Figure 20. Set-up for External UVLO Application
RENT
§ VON
¨¨
© VEN H
VOFF
§
VEN HYS
VON ˜ ¨¨1
VEN
©
·
1¸¸ ˜ RENB
¹
·
¸¸
¹
where
•
•
26
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
(10)
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9.2.1.2.10 Maximum Ambient Temperature
As with any power conversion device, the LMR36006-Q1 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
RθJA of the device and PCB combination. The maximum internal die temperature for the LMR36006-Q1 must be
limited to 150°C. This establishes a limit on the maximum device power dissipation and therefore the load
current. Equation 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The converter
efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions
cannot be found in one of the curves, then interpolation can be used to estimate the efficiency. Alternatively, the
EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly.
The correct value of RθJA is more difficult to estimate. As stated in Semiconductor and IC Package Thermal
Metrics, the values given in are not valid for design purposes and must not be used to estimate the thermal
performance of the application. The values reported in that table were measured under a specific set of
conditions that are rarely obtained in an actual application.
IOUT
MAX
TJ TA
1
K
˜
˜
R TJA
1 K VOUT
where
•
η = Efficiency
(11)
The effective RθJA is a critical parameter and depends on many factors such as power dissipation, air
temperature/flow, PCB area, copper heat-sink area, number of thermal vias under the package, and adjacent
component placement; to mention just a few. Due to the ultra-miniature size of the VQFN (RNX) package, a DAP
is not available. This means that this package exhibits a somewhat greater RθJA. A typical example of RθJA vs
copper board area can be found in Figure 21. Note that the data given in this graph is for illustration purposes
only, and the actual performance in any given application depends on all of the factors mentioned above.
70
60
55
R
JA (ƒC/w)
65
50
45
RNX, 4L
40
0
10
20
30
40
50
Copper Area (cm2)
60
70
C005
Figure 21. RθJA versus Copper Board Area for the VQFN (RNX) Package
Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given application
environment:
• Thermal Design by Insight not Hindsight Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
• Thermal Design Made Simple with LM43603 and LM43602 Application Report
• Using New Thermal Metrics Application Report
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9.2.2 Application Curves
Unless otherwise specified the following conditions apply: VIN = 24 V, TA = 25°C. The circuit is shown in
Figure 18, with the appropriate BOM from Table 5.
90%
80%
80%
70%
70%
60%
60%
Efficiency
100%
90%
Efficiency
100%
50%
40%
30%
10%
0
0.001
0.01
0.1
Output Current (A)
VOUT = 5 V
40%
30%
8 VIN
12 VIN
24 VIN
48 VIN
60 VIN
20%
50%
6 VIN
12 VIN
24 VIN
48 VIN
60 VIN
20%
10%
0
0.001
1
0.01
0.1
Output Current (A)
5Vou
400 kHz
VOUT = 3.3 V
Figure 22. Efficiency
3p3V
400 kHz
Figure 23. Efficiency
3.335
5.04
8 VIN
12 VIN
24 VIN
48 VIN
60 VIN
5.02
6 VIN
12 VIN
24 VIN
48 VIN
60 VIN
3.33
3.325
Output Voltage (V)
5.03
Output Voltage (V)
1
5.01
5
4.99
4.98
3.32
3.315
3.31
3.305
3.3
3.295
3.29
4.97
3.285
3.28
4.96
0
0.1
0.2
0.3
0.4
Output Current (A)
VOUT = 5 V
0.5
0
0.6
0.1
400 kHz
VOUT = 3.3 V
Figure 24. Load Regulation
0.5
LMR3
400 kHz
4.5E+5
IOUT = 1.5 mA
IOUT = 300 mA
IOUT = 600 mA
4E+5
Switching Frequency (Hz)
5.5
5
4.5
4
3.5E+5
3E+5
2.5E+5
2E+5
1.5E+5
1E+5
3.5
IOUT = 300 mA
IOUT = 600 mA
5E+4
3
0
4
4.2
4.4
VOUT = 5 V
4.6
4.8
5
5.2
Input Voltage (V)
5.4
5.6
5.8
6
5
5.1
5.2
LMR3
400 kHz
VOUT = 5 V
Figure 26. Overall Dropout Characteristic
28
0.6
Figure 25. Load Regulation
6
Output Voltage (V)
0.2
0.3
0.4
Output Current (A)
5vou
5.3
5.4 5.5 5.6
Input Voltage (V)
5.7
5.8
5.9
6
LMR3
400 kHz
Figure 27. Frequency Dropout Characteristic
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50
225
45
200
Output Current (mA)
Input Supply Current (mA)
www.ti.com
40
35
30
25
175
150
125
100
20
75
5
10
15
20
VOUT = 3.3 V
25 30 35 40
Input Voltage (V)
45
50
55
60
5
10
IOUT= 0 A
RFBT= 100 kΩ
VOUT = 3.3 V
400 kHz
400 kHz
ILOAD= 0 A - 0.3 A
25 30 35 40
Input Voltage (V)
45
50
55
60
LMR3
400 kHz
Figure 29. Mode Change Thresholds
400 kHz
Figure 31. Start-Up Waveform
Figure 30. Start-Up Waveform
VOUT = 5 V
Slew Rate=1µs/A
20
VOUT = 3.3 V
Figure 28. Input Supply Current
VOUT = 5 V
15
iq-v
VOUT = 3.3 V
Slew Rate = 1 µs/A
Figure 32. Load Transient
400 kHz
ILOAD= 0 A - 0.3 A
Figure 33. Load Transient
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VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 150kHz to 30 MHz
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IOUT = 1.5 A
Figure 34. Conducted EMI vs. CISPR25 Limits (Yellow:
Peak Signal, Blue: Average Signal)
VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 150 kHz to 30 MHz
IOUT = 1.5 A
Figure 36. Radiated EMI Rod vs. CISPR25 Limits
VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 30 MHz to 200 MHz
IOUT = 1.5 A
Figure 38. Radiated EMI Bicon Horizontal vs. CISPR25
Limits
30
VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 30 MHz to 108 MHz
IOUT = 1.5 A
Figure 35. Conducted EMI vs. CISPR25 Limits (Yellow:
Peak Signal, Blue: Average Signal)
VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 30 MHz to 200 MHz
IOUT = 1.5 A
Figure 37. Radiated EMI Bicon Vertical vs. CISPR25 Limits
VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 200 MHz to 1 GHz
IOUT = 1.5 A
Figure 39. Radiated EMI Log Vertical vs. CISPR25 Limits
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VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 200 MHz to 1 GHz
SNVSAY7C – AUGUST 2018 – REVISED OCTOBER 2019
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 1.83 GHz to 2.5 GHz
IOUT = 1.5 A
Figure 41. Radiated EMI Horn Vertical vs. CISPR25 Limits
Figure 40. Radiated EMI Log Horizontal vs. CISPR25 Limits
83H9652
VIN
IN+
FB1
+
CD = 100 uF
GND
IN±
CF1 = 4.7 uF
VIN = 13.5 V
VOUT = 5 V
Frequency Tested: 1.8 GHz to 2.5 GHz
CF2 = 0.1 uF
CF3 = 4.7 uF
IOUT = 1.5 A
Figure 42. Radiated EMI Horn Horizontal vs. CISPR25
Limits
Figure 43. Recommended Input EMI Filter
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9.2.3 Design 2: High Density 12-V, 600-mA FPWM Converter
9.2.3.1 Design Requirements
Example requirements for a typical 3.3-V application. The input voltages are here for illustration purposes only.
See Specifications for the operating input voltage range.
Table 6. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
6-V to 18-V steady state, 4.2-V to 60-V transients
Output voltage
3.3 V
Maximum output current
0 A to 600 mA
Switching frequency
2100 kHz
Current consumption at 0-A load
Not critical: < 100 mA acceptable
Switching frequency at 0-A load
Critical: Need fixed frequency operation
Table 7. List of Components for Design 2
VOUT
FREQUENCY
RFBB
COUT
L
U1
3.3 V
2100 kHz
43.2 kΩ
1 × 15 µF
7.8 µH, 13.6 mΩ
LMR36006FSCQRNXRQ1
9.2.3.2 Detailed Design Procedure
See Detailed Design Procedure.
32
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9.2.3.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C. The circuit is shown in Figure 18, with the
appropriate BOM from Table 7.
100%
3.38
90%
3.36
80%
3.34
Output Voltage (V)
Efficiency
70%
60%
50%
40%
30%
3.32
3.3
3.28
3.26
20%
6 VIN
12 VIN
18 VIN
10%
6 VIN
12 VIN
18 VIN
3.24
0
3.22
0
0.1
0.2
0.3
0.4
Output Current (A)
VOUT = 3.3 V
0.5
0.6
0
0.1
2100 kHz
VOUT = 3.3 V
Figure 44. Efficiency
24
2.2E+6
23
Input Supply Current (mA)
Swithcing Frequency (Hz)
2E+6
1.8E+6
1.6E+6
1.4E+6
1.2E+6
1E+6
8E+5
6E+5
4E+5
IOUT = 300 mA
IOUT = 600 mA
2E+5
0.5
0.6
D009
2100 kHz
Figure 45. Load Regulation
2.4E+6
0
10
0.2
0.3
0.4
Output Current (A)
D007
22
21
20
19
18
17
16
15
14
15
20
25
30
35
40
Input Voltage (V)
45
50
55
60
5
10
15
Freq
VOUT = 3.3 V
Figure 46. Switching Frequency vs Input Voltage
VOUT = 3.3 V
2100 kHz
20
25 30 35 40
Input Voltage (V)
45
50
55
60
iqvi
IOUT= 0 A
RFBT= 100 kΩ
Figure 47. Input Supply Current
VOUT = 3.3 V
Slew Rate = 1 µs/A
Figure 48. Start-Up Waveform
2100 kHz
ILOAD= 0 A - 0.3 A
Figure 49. Load Transient
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Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C. The circuit is shown in Figure 18, with the
appropriate BOM from Table 7.
VOUT = 3.3 V
Slew Rate = 1 µs/A
2100 kHz
ILOAD= 0 A - 0.6 A
Figure 50. Load Transient
9.3 What to Do and What Not to Do
•
•
•
•
•
•
34
Don't: Exceed the Absolute Maximum Ratings.
Don't: Exceed the ESD Ratings.
Don't: Allow the EN input to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Don't: Use the thermal data given in the Thermal Information table to design your application.
Do: Follow all the guidelines and/or suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see Support Resources).
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Specifications found in this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded regulator. The
average input current can be estimated with Equation 12.
VOUT ˜ IOUT
IIN
VIN ˜ K
where
•
η is the efficiency
(12)
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip may cause the
regulator to momentarily shutdown and/or reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and/or use an aluminum or tantalum input capacitor in parallel with
the ceramics. The moderate ESR of these types of capacitors help to damp the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DCDC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow may damage the device.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter the most critical PCB feature is the loop formed by the input capacitor(s) and power ground, as shown
in Figure 51. This loop carries large transient currents that can cause large transient voltages when reacting with
the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because
of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the
parasitic inductance. Figure 52 shows a recommended layout for the critical components of the LMR36006-Q1.
1. Place the input capacitor(s) as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and
routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the BOOT
and SW pins. Route the SW pin to the N/C pin and used to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as
a heat dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature section,
enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and
ambient temperature. The top and bottom PCB layers must be made with two ounce copper; and no less
than one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also
be connected to the inner layer heat-spreading ground planes.
8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies Application Report
• Simple Switcher PCB Layout Guidelines Application Report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
36
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Layout Guidelines (continued)
VIN
CIN
SW
GND
Figure 51. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control circuitry.
Connect the AGND and PGND pins to the ground planes using vias next to the bypass capacitors. PGND pins
are connected directly to the source of the low side MOSFET switch and also connected directly to the grounds
of the input and output capacitors. The PGND net contains noise at the switching frequency and may bounce
due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of
the ground planes. The other side of the ground plane contains much less noise; use for sensitive routes.
Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat
dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1
oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current
conduction impedance, proper shielding and lower thermal resistance.
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11.2 Layout Example
VOUT
VOUT
INDUCTOR
COUT
COUT
COUT
COUT
GND
GND
CIN
CIN
CHF
12
11
2
10
3
9
EN
4
8
PGOOD
VIN
T
5
6
7
CVCC
RFBT
CBOO
1
VIN
CHF
RFBB
GND
HEATSINK
GND
HEATSINK
INNER GND PLANE
Top Trace/Plane
Inner GND Plane
VIN Strap on Inner Layer
VIA to Signal Layer
VIA to GND Planes
VIA to VIN Strap
Top
Inner GND Plane
VIN Strap and
GND Plane
Signal
traces and
GND Plane
Trace on Signal Layer
Figure 52. Example Layout
38
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
• Two-Stage Power Supply Reference Design for Field Transmitters
• Wide Vin Power Supply Reference Design for Space-Constrained Industrial Sensors
• Automotive ADAS camera power supply reference design optimized for solution size and low noise
• How a DC/DC converter package and pinout design can enhance automotive EMI performance
• Introduction to Buck Converters Features: UVLO, Enable, Soft Start, Power Good
• Introduction to Buck Converters: Understanding Mode Transitions
• Introduction to Buck Converters: Minimum On-time and Minimum Off-time Operation
• Introduction to Buck Converters: Understanding Quiescent Current Specifications
• Trade-offs between thermal performance and small solution size with DC/DC converters
• Reduce EMI and shrink solution size with Hot Rod packaging
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR36006-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Designing High-Performance, Low-EMI Automotive Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Application Report
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
Hotrod, HotRod, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: LMR36006-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMR36006AQRNXRQ1
ACTIVE
VQFN-HR
RNX
12
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
NH06AQ
LMR36006AQRNXTQ1
ACTIVE
VQFN-HR
RNX
12
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
NH06AQ
LMR36006FSC3RNXRQ1
ACTIVE
VQFN-HR
RNX
12
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
NH6C3Q
LMR36006FSC3RNXTQ1
ACTIVE
VQFN-HR
RNX
12
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
NH6C3Q
LMR36006FSCQRNXRQ1
ACTIVE
VQFN-HR
RNX
12
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
NH06CQ
LMR36006FSCQRNXTQ1
ACTIVE
VQFN-HR
RNX
12
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
NH06CQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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