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LMR36510
SNVSBD7A – OCTOBER 2019 – REVISED FEBRUARY 2020
LMR36510 SIMPLE SWITCHER® 4.2-V to 65-V, 1-A Synchronous Step-down Converter
1 Features
3 Description
•
The LMR36510 regulator is an easy-to-use,
synchronous, step-down DC/DC SIMPLE SWITCHER
converter. With integrated high-side and low-side
power MOSFETs, output current up to 1 A is
delivered over a wide input voltage range of 4.2 V to
65 V. The transient tolerance that goes up to 70 V
reduces the solution size and cost to protect against
overvoltages and meets the surge immunity
requirements of IEC 61000-4-5.
1
•
•
•
•
Designed for reliable and rugged applications
– Input transient protection up to 70 V
– Protection features: thermal shutdown, input
undervoltage lockout, cycle-by-cycle current
limit, hiccup short-circuit protection
Well-suited for scalable industrial power supplies
– Pin compatible with:
– LMR36520 (65 V, 2 A)
– LMR33610/LMR33620/LMR33630/
LMR33640 (36 V, 1 A, 2 A, 3 A, or 4 A)
– Internal compensation helps reduce solution
size, cost and design complexity
– 400-kHz frequency
Wide conversion range
– Input voltage range: 4.2 V to 65 V
– Output voltage range: 1 V to 95% of VIN
Low-power dissipation across load spectrum
– 90% efficiency: 24 VIN, 5 VOUT, 1 A at 400 kHz
– Increased light-load efficiency in PFM mode
– Low operating quiescent current of 26 µA
Power-good output with filter and delayed release
2 Applications
•
•
•
•
•
•
IP network cameras
Analog security cameras
HVAC valve and actuator control
AC drive and servo drive control modules
Analog input modules and mixed IO modules
General purpose wide VIN power supply
The LMR36510 uses peak-current mode control to
provide optimal efficiency and output voltage
accuracy. Precision enable gives flexibility by
enabling a direct connection to the wide input voltage
or precise control over device start-up and shutdown.
The power-good flag, with built-in filtering and delay,
offers a true indication of system status, eliminating
the requirement for an external supervisor.
Integration and internal compensation eliminates
many external components and provides a pinout
designed for a simple PCB layout. The feature set of
the device is designed to simplify implementation for
a wide range of end equipment. The LMR36510 is
pin-to-pin compatible with the LMR36520 (65 V, 2 A)
and LMR33610, LMR33620, LMR33630 and
LMR33640 (36 V, 1 A/2 A/3 A/4 A), completing the
latest family of SIMPLE SWITCHER converters. This
increases the ease of use and scalability of wide Vin
converters across various commonly used voltage
and current ratings without having the need to
redesign the board layout. As a result, the overall
cost, design effort and time to market are optimized.
The LMR36510 is in an 8-pin HSOIC package.
Device Information(1)
PART NUMBER
LMR36510
PACKAGE
HSOIC (8)
BODY SIZE (NOM)
5.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency versus Output Current
VOUT = 5 V, 400 kHz
Simplified Schematic
BOOT
100
VIN
VIN
CBOOT
95
90
CIN
EN
SW
L1
Efficiency (%)
85
VOUT
COUT
PGND
80
75
70
VCC
65
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
60
55
50
45
0.001 0.002
0.005 0.01 0.02
0.05 0.1
Load Current (A)
0.2 0.3 0.5
PG
RFBT
CVCC
FB
RFBB
1
Effi
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR36510
SNVSBD7A – OCTOBER 2019 – REVISED FEBRUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
6
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
System Characteristics .............................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 17
8.3 What to Do and What Not to Do ............................. 26
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2019) to Revision A
•
2
Page
Changed device status from Advance Information to Production Data ................................................................................. 1
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SNVSBD7A – OCTOBER 2019 – REVISED FEBRUARY 2020
5 Pin Configuration and Functions
DDA Package
8-Pin HSOIC
Top View
PGND
1
VIN
2
8
SW
7
BOOT
THERMAL PAD
EN
3
6
VCC
PG
4
5
FB
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
PGND
1
G
Power and analog ground terminal. Connect to bypass capacitor with short, wide traces. Ground
reference for internal references and logic. All electrical parameters are measured with respect to this
pin.
VIN
2
P
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin and
PGND.
EN
3
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not float.
PG
4
A
Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be left open when
not used.
FB
5
A
Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do not
ground.
VCC
6
P
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to
PGND.
BOOT
7
P
Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this
pin to the SW pin.
SW
8
P
Regulator switch node. Connect to a power inductor.
PAD
THERMAL
PAD
Therm Major heat dissipation path of the device. A direct thermal connection to a ground plane is required.
al
The PAD is not meant as an electrical interconnect. Electrical characteristics are not ensured.
A = Analog, P = Power, G = Ground
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SNVSBD7A – OCTOBER 2019 – REVISED FEBRUARY 2020
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6 Specifications
6.1 Absolute Maximum Ratings
Over junction temperature range of -40°C to 150°C (unless otherwise noted) (1)
MIN
MAX
Input voltage
VIN to PGND
–0.3
70
UNIT
V
Input voltage
EN to PGND
–0.3
70.3
V
Input voltage
FB to PGND
–0.3
5.5
V
Input voltage
PG to PGND
–0.3
20
V
Output voltage
SW to PGND
–0.3
70.3
V
Output voltage
SW to PGND less than 10-ns transients
–3.5
70
V
Output voltage
CBOOT to SW
–0.3
5.5
V
Output voltage
VCC to PGND
–0.3
5.5
V
Junction Temperature TJ
-40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM) (1)
±2500
Charged-device model (CDM) (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 ℃ to 125 ℃ (unless otherwise noted) (1)
MIN
MAX
4.2
65
V
EN to PGND (2)
0
65
V
PG to PGND (2)
0
18
V
Output voltage
VOUT
1
28
V
Output current
IOUT
0
1
A
VIN to PGND
Input voltage
(1)
(2)
4
UNIT
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
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6.4 Thermal Information
LMR36510
THERMAL METRIC (1)
DDA (HSOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
4.3
°C/W
ψJB
Junction-to-board characterization parameter
13.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.3
°C/W
(1)
42.9
°C/W
54
°C/W
13.6
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
36
UNIT
SUPPLY VOLTAGE (VIN PIN)
IQ-nonSW
Operating quiescent current (nonswitching) (2)
VEN = 3.3 V (PFM variant only)
26
ISD
Shutdown quiescent current;
measured at VIN pin
VEN = 0 V
5.3
µA
µA
ENABLE (EN PIN)
VEN-VCC-H
Enable input high level for VCC output
VENABLE rising
VEN-VCC-L
Enable input low level for VCC output
VENABLE falling
0.3
1.14
V
VEN-VOUT-H
Enable input high level for VOUT
VENABLE rising
1.157
VEN-VOUT-HYS
Enable input hysteresis for VOUT
Hysteresis below VENABLE-H; falling
110
mV
ILKG-EN
Enable input leakage current
VEN = 3.3V
2.7
nA
V
1.231
1.3
V
INTERNAL LDO (VCC PIN)
VCC
VCC-UVLORising
VCC-UVLOFalling
Internal VCC voltage
6 V ≤ VIN ≤ 65 V
Internal VCC undervoltage lockout
Internal VCC undervoltage lockout
4.75
5
5.25
V
VCC rising
3.6
3.8
4.0
V
VCC falling
3.1
3.3
3.5
V
1
1.015
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
ILKG-FB
Feedback leakage current
0.985
FB = 1 V
2.1
V
nA
CURRENT LIMITS AND HICCUP
High-side current limit (3)
ISC
ILS-LIMIT
Low-side current limit
IL-ZC
Zero cross detector threshold
IPEAK-MIN
Minimum inductor peak current (3)
(1)
(2)
(3)
1.6
(3)
1
PFM variants only
2
2.4
A
1.3
1.6
A
0.04
A
0.28
A
MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
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Electrical Characteristics (continued)
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP
Power-Good upper threshold - rising
% of FB voltage
105%
107%
110%
VPG-LOW-DN
Power-Good lower threshold - falling
% of FB voltage
90%
93%
95%
VPG-HYS
Power-Good hysteresis (rising &
falling)
% of FB voltage
VPG-VALID
Minimum input voltage for proper
Power-Good function
RPG
Power-Good on-resistance
VEN = 2.5 V
RPG
Power-Good on-resistance
VEN = 0 V
RDS-ON-HS
High-side MOSFET ON-resistance
RDS-ON-LS
Low-side MOSFET ON-resistance
1.5%
2
V
80
165
Ω
35
90
Ω
IOUT = 0.5 A
245
465
mΩ
IOUT = 0.5 A
165
310
mΩ
MOSFETS
6.6 Timing Requirements
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
MIN
NOM
MAX
UNIT
tON-MIN
Minimum switch on-time
92
tOFF-MIN
Minimum switch off-time
80
102
ns
tON-MAX
Maximum switch on-time
7
12
µs
tSS
Internal soft-start time
4.5
6
ms
(1)
3
ns
MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
6.7 Switching Characteristics
TJ = -40°C to 125°C, VIN = 24 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
340
400
460
kHz
OSCILLATOR
FOSC
6
Internal oscillator frequency
400-kHz variant
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SNVSBD7A – OCTOBER 2019 – REVISED FEBRUARY 2020
6.8 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40℃ to 125℃. These specifications are not ensured by production
testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Operating input voltage range
VOUT
Adjustable output voltage regulation (1)
PFM operation
ISUPPLY
Input supply current when in regulation
VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
DMAX
Maximum switch duty cycle (2)
VHC
FB pin voltage required to trip short-circuit
hiccup mode
tD
Switch voltage dead time
2
ns
TSD
Thermal shutdown temperature
Shutdown temperature
170
°C
TSD
Thermal shutdown temperature
Recovery temperature
158
°C
(1)
(2)
4.2
65
–1.5%
2.5%
UNIT
VIN
26
V
µA
98%
0.4
V
Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load
In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN =
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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6.9 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 24 V.
12
500
475
Peak Inductor Current (mA)
Input Current (PA)
10
8
6
4
25qC
125qC
-40qC
450
425
400
375
350
25qC
125qC
-40qC
325
2
300
5
10
15
20
25
30 35 40 45
Input Voltage (V)
50
55
60
65
5
10
Shut
EN = 0 V
IOUT = 0 A
Figure 1. Shutdown Supply Current
8
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15
20
25
30 35 40 45
Input Voltage (V)
VOUT = 3.3 V
See Figure 34
50
55
60
65
Imin
ƒSW = 400 kHz
Figure 2. IPEAK-MIN
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7 Detailed Description
7.1 Overview
The LMR36510 is a synchronous peak-current mode buck regulator designed for a wide variety of industrial
applications. The regulator automatically switches modes between PFM and PWM, depending on load. At heavy
loads, the device operates in PWM at a constant switching frequency. At light loads, the mode changes to PFM
with diode emulation, allowing DCM. This reduces the input supply current and keeps efficiency high. The device
features internal loop compensation, which reduces design time and requires fewer external components than
externally compensated regulators.
7.2 Functional Block Diagram
VCC
INT. REG.
BIAS
OSCILLATOR
EN
VIN
ENABLE
LOGIC
BOOT
HS CURRENT
SENSE
1.0 V
Reference
ERROR
AMPLIFIER
FB
+
±
+
±
PWM
COMP
CONTROL
LOGIC
PFM
MODE
CONTROL
PG
DRIVER
SW
LS CURRENT
SENSE
POWER GOOD
CONTROL
PGND
7.3 Feature Description
7.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36510 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. Output voltage excursions
lasting less than tPG do not trip the power-good flag. Power-good operation can best be understood by
referencing Figure 3 and Figure 4. Note that during initial power-up, a delay of about 4 ms (typical) is inserted
from the time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during
start-up and is not encountered during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. If this function
is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4
mA.
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Feature Description (continued)
Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)