LMR50410-Q1
SLUSDW4A – OCTOBER 2019 – REVISEDLMR50410-Q1
NOVEMBER 2020
SLUSDW4A – OCTOBER 2019 – REVISED NOVEMBER 2020
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LMR50410-Q1 SIMPLE SWITCHER® 4-V to 36-V, 1-A Buck Converter in SOT-23-6
Package
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified
– Temperature grade 1: –40°C to 125°C ambient
operating temperature range
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Configured for rugged automotive applications
– Input voltage range: 4 V to 36 V
– 1-A continuous output current
– Minimum switching-on time: 60 ns
– 2.1-MHz fixed switching frequency
– Junction temperature range: –40°C to 150°C
– 98% maximum duty cycle
– Monotonic start-up with pre-biased output
– Internal short circuit protection with hiccup
mode
– ±1% tolerance voltage reference
– Precision enable
Small solution size and ease of use
– Integrated synchronous rectification
– Internal compensation for ease of use
– SOT-23-6 package
Pin-to-pin compatible with TPS560430-Q1
Various options in pin-to-pin compatible package
– PFM and forced PWM (FPWM) options
– Fixed 3.3-V and 5.0-V output option
Create a custom design using the LMR50410-Q1
with the WEBENCH® Power Designer
Body electronics and lighting
Infotainment and cluster
ADAS
General purpose wide VIN power supplies
3 Description
The LMR50410-Q1 is a wide-V IN, easy-to-use
synchronous buck converter capable of driving up to
1-A load current. With a wide input range of 4 V to 36
V, the device is suitable for a wide range of
automotive applications for power conditioning from
an unregulated source.
The LMR50410-Q1 operates at 2.1-MHz switching
frequency to support use of relatively small inductors
for an optimized solution size. It has an PFM version
to realize high efficiency at light load and FPWM
version to achieve constant frequency, and small
output voltage ripple over the full load range. Softstart and compensation circuits are implemented
internally which allows the device to be used with
minimum external components.
The device has built-in protection features, such as
cycle-by-cycle current limit, hiccup mode short-circuit
protection, and thermal shutdown in case of excessive
power dissipation. The LMR50410-Q1 is available in
SOT-23-6 package.
Device Information
(1)
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LMR50410-Q1
SOT-23-6
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
VIN up to 36 V
VIN
90
CB
CIN
80
CBOOT
EN
VOUT
SW
RFBT
Efficiency(%)
70
L
60
50
PFM, VIN=8V
PFM, VIN=12V
PFM, VIN=24V
PFM, VIN=36V
FPWM, VIN=8V
FPWM, VIN=12V
FPWM, VIN=24V
FPWM, VIN=36V
40
30
20
GND
FB
COUT
RFBB
10
0
0.001
0.01
0.1
1
2
IOUT(A)
Simplified Schematic
Efficiency versus Output Current VOUT = 5 V,
2.1MHz
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements.................................................. 6
7.7 Switching Characteristics............................................6
7.8 System Characteristics............................................... 6
7.9 Typical Characteristics................................................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................16
9 Application and Implementation.................................. 17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................26
11 Layout........................................................................... 27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 Device Support....................................................... 29
12.2 Documentation Support.......................................... 29
12.3 Receiving Notification of Documentation Updates..29
12.4 Support Resources................................................. 29
12.5 Trademarks............................................................. 29
12.6 Electrostatic Discharge Caution..............................29
12.7 Glossary..................................................................29
13 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (July 2020) to Revision A (November 2020)
Page
• Added FPWM OPNs...........................................................................................................................................3
• Added VOUT-3.3V-Fixed, VOUT-5V-Fixed, ILKG-VOUT-3.3V-Fixed, and ILKG-VOUT-5V-Fixed for new OPNs............................ 5
• Updated Overview with FPWM version............................................................................................................ 10
• Updated Overcurrent and Short Circuit Protection with FPWM version........................................................... 14
• Updated Active Mode with FPWM version....................................................................................................... 16
2
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5 Device Comparison Table
ORDERABLE PART NUMBER
FREQUENCY
PFM OR FPWM
OUTPUT
LMR50410YQDBVRQ1
2.1 MHz
PFM
Adjustable
LMR50410YFQDBVRQ1
2.1 MHz
FPWM
Adjustable
LMR50410Y3FQDBVRQ1
2.1 MHz
FPWM
3.3 V
LMR50410Y5FQDBVRQ1
2.1 MHz
FPWM
5.0 V
6 Pin Configuration and Functions
CB
1
6
SW
GND 2
5
VIN
3
4
EN
FB
Figure 6-1. 6-Pin SOT-23-6 DBV Package (Top View)
Table 6-1. Pin Functions
PIN
(1)
TYPE(1)
DESCRIPTION
NAME
NO
CB
1
P
Bootstrap capacitor connection for high-side FET driver. Connect a high quality 100-nF
capacitor from this pin to the SW pin.
GND
2
G
Power ground terminals, connected to the source of low-side FET internally. Connect to
system ground, ground side of CIN and COUT. Path to CIN must be as short as possible.
FB
3
A
Feedback input to the converter. Connect a resistor divider to set the output voltage. Never
short this terminal to ground during operation. For fixed output version, directly connect to
output point.
EN
4
A
Precision enable input to the converter. Do not float. High = on, low = off. Can be tied to VIN.
Precision enable input allows adjustable UVLO by external resistor divider.
VIN
5
P
Supply input terminal to internal bias LDO and high-side FET. Connect to input supply and
input bypass capacitors CIN. Input bypass capacitors must be directly connected to this pin and
GND.
SW
6
P
Switching output of the converter. Internally connected to source of the high-side FET and
drain of the low-side FET. Connect to power inductor.
A = Analog, P = Power, G = Ground.
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7 Specifications
7.1 Absolute Maximum Ratings
Over junction temperature range of -40°C to 150°C (unless otherwise noted)(1)
Input voltage
Output voltage
MIN
MAX
VIN to GND
–0.3
38
UNIT
V
EN to GND
–0.3
VIN+0.3
V
FB to GND
–0.3
5.5
V
SW to GND
–0.3
VIN+0.3
V
SW to GND less than 10-ns transients
–3.5
38
V
CB to SW
–0.3
5.5
V
Junction Temperature TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
(HBM)(1)
V(ESD)
Electrostatic discharge
Human body model
V(ESD)
Electrostatic discharge
Charged device model (CDM)
(1)
Human body model
(HBM)(1)
Charged device model (CDM)
VALUE
UNIT
±2500
V
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 °C to 150°C (unless otherwise noted)(1)
MIN
MAX
UNIT
VIN to GND
4
36
V
EN to GND(2)
0
VIN
V
Output voltage
VOUT (3) (4)
1
28
V
Output current
IOUT
0
1
A
Input voltage
(1)
(2)
(3)
(4)
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
Under no conditions should the output voltage be allowed to fall below zero volts.
Maximum VOUT ensured up to 90% of VIN in final production.
7.4 Thermal Information
The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For example, with a 2-layer PCB, a RθJA = 80℃/W can be
achieved. For design information see Maximum Output Current versus Ambient Temperature.
LMR50410
THERMAL METRIC(1)
DBV(SOT-23-6)
UNIT
6 PINS
4
RθJA
Junction-to-ambient thermal resistance
173
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
116
°C/W
RθJB
Junction-to-board thermal resistance
31
°C/W
ψJT
Junction-to-top characterization parameter
20
°C/W
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The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For example, with a 2-layer PCB, a RθJA = 80℃/W can be
achieved. For design information see Maximum Output Current versus Ambient Temperature.
LMR50410
THERMAL
METRIC(1)
UNIT
DBV(SOT-23-6)
6 PINS
ψJB
(1)
Junction-to-board characterization parameter
30
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Rising threshold
3.55
3.75
4
V
Falling threshold
3.25
3.45
3.65
V
SUPPLY VOLTAGE (VIN PIN)
VIN_UVLO
Undervoltage lockout thresholds
Hysteresis
0.3
IQ-nonSW
Operating quiescent current (nonswitching)(2)
VEN = 3.3 V, VFB=1.1V (PFM variant
only)
80
120
µA
ISD
Shutdown quiescent current;
measured at VIN pin
VEN = 0 V
3
10
µA
1.23
1.36
V
1.1
1.22
V
ENABLE (EN PIN)
VEN-VOUT-H
Enable input high-level for VOUT
VENABLE rising
1.1
VEN-VOUT-L
Enable input low-level for VOUT
VENABLE falling
0.95
VEN-VOUT-HYS Enable input hysteresis for VOUT
Hysteresis
130
ILKG-EN
VEN = 3.3V
10
Enable input leakage current
V
mV
200
nA
VOLTAGE REFERENCE (FB PIN)
0.99
1
1.01
V
VOUT-3.3V-Fixed Output voltage
VFB
Feedback voltage
Vin=12V
3.25
3.3
3.35
V
4.925
5.0
5.075
VOUT-5V-Fixed
Output voltage
Vin=12V
ILKG-FB
Feedback leakage current
FB = 1.2 V
0.2
nA
ILKG-VOUT-3.3V-
Feedback leakage current
VOUT = 3.3 V (Fixed Option)
1.7
µA
Feedback leakage current
VOUT = 5V (Fixed Option)
2.6
µA
Fixed
ILKG-VOUT-5VFixed
V
CURRENT LIMITS AND HICCUP
ISC
High-side current limit(3)
Vin=12V
1.25
1.6
1.9
A
ILS-LIMIT
Low-side current limit(3)
Vin=12V
0.9
1.1
1.3
A
IL-ZC
Zero cross detector threshold
PFM variants only
0.02
A
IL-NEG
Negative current limit(3)
FPWM variant only
–0.6
A
RDS-ON-HS
High-side MOSFET ON-resistance
TJ=25 ℃, VIN = 12 V
450
mΩ
RDS-ON-LS
Low-side MOSFET ON-resistance
TJ=25 ℃, VIN = 12 V
240
mΩ
Shutdown threshold
170
°C
MOSFETS
THERMAL SHUTDOWN
TSD-Rising (1)
Thermal shutdown
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Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TSD-Falling (1)
(1)
(2)
(3)
TEST CONDITIONS
Thermal shutdown
MIN
TYP
Recovery threshold
MAX
UNIT
158
°C
MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range verified through correlation
using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
7.6 Timing Requirements
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V- 36 V.
PARAMETER
tON-MIN
TEST CONDTIONS
MIN
TYP
MAX
UNIT
Minimum switch on-time
IOUT=1A
60
tOFF-MIN
Minimum switch off-time
IOUT=1A
110
ns
tON-MAX
Maximum switch on-time
7.5
µs
tSS
Internal soft-start time
1.8
ms
tHC
Time between current-limit hiccup
burst
135
ms
(1)
ns
MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range verified through correlation
using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
7.7 Switching Characteristics
TJ = -40°C to 150°C, VIN = 4 V-36 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8
2.1
2.4
MHz
OSCILLATOR
FOSC
Internal oscillator frequency
2.1-MHz variant
7.8 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = -40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
6
VIN
Operating input voltage range
VOUT
Adjustable output voltage
regulation(1)
VOUT
TEST CONDITIONS
MIN
TYP
MAX
4
36
PFM operation
–1.5%
2.5%
Adjustable output voltage
regulation(1)
FPWM operation
–1.5%
1.5%
ISUPPLY
Input supply current when in
regulation
VIN =12 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
DMAX
Maximum switch duty cycle(2)
VHC
FB pin voltage required to trip shortcircuit hiccup mode
tD
Switch voltage dead time
TSD
Thermal shutdown temperature
90
UNIT
V
µA
98%
Shutdown temperature
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0.4
V
2
ns
170
°C
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The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = -40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
TSD
(1)
(2)
Thermal shutdown temperature
TEST CONDITIONS
Recovery temperature
MIN
TYP
158
MAX
UNIT
°C
Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load
In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN
= 1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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7.9 Typical Characteristics
100
100
90
90
80
80
70
70
Efficiency(%)
Efficiency(%)
VIN = 12 V, fSW = 2.1 Mhz ,TA = 25°C, unless otherwise specified.
60
50
PFM, VIN=8V
PFM, VIN=12V
PFM, VIN=24V
PFM, VIN=36V
FPWM, VIN=8V
FPWM, VIN=12V
FPWM, VIN=24V
FPWM, VIN=36V
40
30
20
10
0
0.001
0.01
0.1
1
60
50
PFM, VIN=8V
PFM, VIN=12V
PFM, VIN=24V
PFM, VIN=36V
FPWM, VIN=8V
FPWM, VIN=12V
FPWM, VIN=24V
FPWM, VIN=36V
40
30
20
10
0
0.001
2
0.01
0.1
fSW = 2.1 MHz
VOUT = 3.3 V
fSW = 2.1 MHz
Figure 7-1. 3.3-V Efficiency versus Load Current
2
VOUT = 5 V
Figure 7-2. 5-V Efficiency versus Load Current
3.36
5.06
VIN=8V
VIN=12V
VIN=24V
VIN=36V
3.35
VIN=8V
VIN=12V
VIN=24V
VIN=36V
5.05
5.04
5.03
VOUT(V)
3.34
VOUT(V)
1
IOUT(A)
IOUT(A)
3.33
5.02
5.01
5
3.32
4.99
3.31
4.98
0
0.1
0.2
fSW = 2.1 MHz
0.3
0.4
0.5 0.6
IOUT(A)
VOUT = 3.3 V
0.7
0.8
0.9
1
0
0.2
0.4
0.6
0.8
1
IOUT(A)
PFM version
fSW = 2.1 MHz
Figure 7-3. 3.3-V Load Regulation
VOUT = 5 V
PFM version
Figure 7-4. 5-V Load Regulation
5.2
3.4
5
3.35
4.8
3.3
3.25
4.4
VOUT(V)
VOUT(V)
4.6
4.2
4
3.2
3.15
3.8
IOUT=0A
IOUT=0.1A
IOUT=0.5A
IOUT=1A
3.6
3.4
3.2
3.5
4
fSW = 2.1 MHz
4.5
5
5.5
VIN(V)
VOUT = 5 V
6
6.5
7
PFM version
7.5
3.1
IOUT=0A
IOUT=0.1A
IOUT=0.5A
IOUT=1A
3.05
3
3.5
4
fSW = 2.1 MHz
Figure 7-5. 5-V Dropout
8
4.5
5
5.5
VIN(V)
VOUT = 3.3 V
6
6.5
7
7.5
PFM version
Figure 7-6. 3.3-V Dropout
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90
3.9
3.8
VIN UVLO(V)
IQ(uA)
85
80
75
70
3.7
3.6
3.5
3.4
65
-50
-25
0
25
50
75
100
Temperature(qC)
125
150
3.3
-50
175
Figure 7-7. IQ versus Temperature
-25
0
25
50
75
100
Temperature({qC)
125
150
175
Figure 7-8. VIN UVLO versus Temperature
1.8
1.003
HS Current Limit
LS Current Limit
1.6
Current Limit(A)
Reference Voltage(V)
1.002
1.001
1
1.4
1.2
0.999
0.998
-50
-25
0
25
50
75
100
Temperature(qC)
125
150
175
Figure 7-9. Reference Voltage versus Temperature
1
-45
-20
5
30
55
80
Temperature (qC)
105
130
155
Figure 7-10. HS and LS Current Limit versus
Temperature
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8 Detailed Description
8.1 Overview
The LMR50410-Q1 converter is an easy-to-use synchronous step-down DC-DC converter operating from a 4-V
to 36-V supply voltage. It is capable of delivering up to 1-A DC load current in a very small solution size. The
family has multiple versions applicable to various applications. See Section 5 for detailed information.
The LMR50410-Q1 employs fixed-frequency peak-current mode control. The PFM version enters PFM Mode at
light load to achieve high efficiency. A FPWM version is provided to achieve low output voltage ripple, tight
output voltage regulation, and constant switching frequency at light load. The device is internally compensated,
which reduces design time and requires few external components.
Additional features such as precision enable and internal soft start provide a flexible and easy-to-use solution for
a wide range of applications. Protection features include thermal shutdown, V IN undervoltage lockout, cycle-bycycle current limit, and hiccup mode short-circuit protection.
This family of devices requires very few external components and has a pin-out designed for simple, optimum
PCB layout.
8.2 Functional Block Diagram
EN
VCC
Enable
LDO
VIN
Precision
Enable
CB
HSI Sense
Internal
SS
EA
REF
FB
±
+
RC
TSD
UVLO
CC
PWM CONTROL LOGIC
PFM
Detector
Ton_min/Toff_min
Detector
SW
Slope
Comp
Freq
Foldback
HICCUP
Detector
Zero
Cross
LSI Sense
Oscillator
FB
GND
10
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8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Control
The following operating description of the LMR50410-Q1 refers to Section 8.2 and to the waveforms in Figure
8-1. The LMR50410-Q1 is a step-down synchronous buck converter with integrated high-side (HS) and low-side
(LS) switches (synchronous rectifier). The LMR50410-Q1 supplies a regulated output voltage by turning on the
high-side and low-side NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin
voltage swings up to approximately VIN, and the inductor current, iL, increases with linear slope (VIN – VOUT) / L.
When the high-side switch is turned off by the control logic, the low-side switch is turned on after an anti-shootthrough dead time. Inductor current discharges through the low-side switch with a slope of –VOUT / L. The control
parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch ON time
and TSW is the switching period. The converter control loop maintains a constant output voltage by adjusting the
duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and
inversely proportional to the input voltage: D = VOUT / VIN.
VSW
SW Voltage
VIN
D = tON/ TSW
tOFF
tON
t
0
TSW
iL
Inductor Current
ILPK
IOUT
¨LL
t
0
Figure 8-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LMR50410-Q1 employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally-compensated, which allows for fewer
external components, making designing easy, and providing stable operation when using a variety of output
capacitors. The converter operates with fixed switching frequency at normal load conditions. During light-load
condition, the LMR50410-Q1 operates in PFM mode to maintain high efficiency (PFM version) or in FPWM mode
for low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM version).
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8.3.2 Adjustable Output Voltage
A precision 1.0-V reference voltage (V REF) is used to maintain a tightly regulated output voltage over the entire
operating temperature range. The output voltage is set by a resistor divider from V OUT to the FB pin. It is
recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
bottom-side resistor R FBB for the desired divider current and use Equation 1 to calculate top-side resistor R FBT.
The recommend range for R FBT is 10 kΩ to 100 kΩ. A lower R FBT value can be used if pre-loading is desired to
reduce V OUT offset in PFM operation. Lower R FBT reduces efficiency at very light load. Less static current goes
through a larger RFBT and can be more desirable when light-load efficiency is critical. However, RFBT larger than
1 MΩ is not recommended because it makes the feedback path more susceptible to noise. Larger R FBT values
require more carefully designed feedback path trace from the feedback resistors to the feedback pin of the
device. The tolerance and temperature variation of the resistor divider network affect the output voltage
regulation.
VOUT
RFBT
FB
RFBB
Figure 8-2. Output Voltage Setting
R FBT =
V OUT - V REF
V REF
× R FBB
(1)
8.3.3 Enable
The voltage on the EN pin controls the ON/OFF operation of the LMR50410-Q1. A voltage of less than 0.95 V
shuts down the device, while a voltage of greater than 1.36 V is required to start the converter. The EN pin is an
input and cannot be left open or floating. The simplest way to enable the operation of the LMR50410-Q1 is to
connect the EN to VIN. This allows self-start-up of the LMR50410-Q1 when VIN is within the operating range.
Many applications benefit from the employment of an enable divider R ENT and R ENB (Figure 8-3) to establish a
precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supplying
protection, such as a battery discharge level. An external logic signal can also be used to drive EN input for
system sequencing and protection. Note, the EN pin voltage must not to be greater than V IN + 0.3 V. It is not
recommended to apply EN voltage when VIN is 0 V.
VIN
RENT
EN
RENB
Figure 8-3. System UVLO by Enable Divider
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8.3.4 Minimum ON-Time, Minimum OFF-Time, and Frequency Foldback
Minimum ON-time (T ON_MIN) is the shortest duration of time that the high-side switch can be turned on. T ON_MIN
is typically 60 ns for the LMR50410-Q1. Minimum OFF-time (T OFF_MIN) is the shortest duration of time that the
high-side switch can be off. T OFF_MIN is typically 110 ns. In CCM operation, T ON_MIN and T OFF_MIN limit the
voltage conversion range without switching frequency foldback.
The minimum duty cycle without frequency foldback allowed is:
DMIN = TON_MIN × fSW
(2)
The maximum duty cycle without frequency foldback allowed is:
DMAX = 1 - TOFF_MIN × fSW
(3)
Given a required output voltage, the maximum VIN without frequency foldback can be found by:
V IN_MAX =
V OUT
f SW × T ON_MIN
(4)
The minimum VIN without frequency foldback can be calculated by:
VIN_MIN =
V OUT
1- f SW × T OFF_MIN
(5)
In the LMR50410-Q1, a frequency foldback scheme is employed once the T ON_MIN or T OFF_MIN is triggered,
which can extend the maximum duty cycle or lower the minimum duty cycle.
The on-time decreases while V IN voltage increases. Once the on-time decreases to T ON_MIN, the switching
frequency starts to decrease while V IN continues to go up, which lowers the duty cycle further to keep V OUT in
regulation according to Equation 2.
The frequency foldback scheme also works once larger duty cycle is needed under low V IN condition. The
frequency decreases once the device hits its T OFF_MIN, which extends the maximum duty cycle according to
Equation 3. In such condition, the frequency can be as low as approximately 133 kHz. Wide range of frequency
foldback allows for the LMR50410-Q1 output voltage to stay in regulation with a much lower supply voltage V IN,
which leads to a lower effective dropout.
With frequency foldback while maintaining a regulated output voltage, V IN_MAX is raised, and V IN_MIN is lowered
by decreased fSW.
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2400
2200
2200
2000
2000
1800
1800
1600
Frequency(kHz)
Frequency(kHz)
SLUSDW4A – OCTOBER 2019 – REVISED NOVEMBER 2020
1600
1400
1200
1000
1400
1200
1000
800
600
800
600
400
IOUT=0.2A
IOUT=0.5A
IOUT=1A
400
200
20
22
VOUT = 3.3 V
24
IOUT=0.2A
IOUT=0.5A
IOUT=1A
200
26
28
VIN(V)
30
32
34
fSW = 2.1 MHz
36
0
4.5
5.5
VOUT = 5 V
Figure 8-4. Frequency Foldback at TON_MIN
6.5
7.5
8.5
VIN(V)
9.5
10.5
11.5
fSW = 2.1 MHz
Figure 8-5. Frequency Foldback at TOFF_MIN
8.3.5 Bootstrap Voltage
The LMR50410-Q1 provides an integrated bootstrap voltage converter. A small capacitor between the CB and
SW pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when
the high-side MOSFET is off and the low-side switch is on. The recommended value of the bootstrap capacitor is
0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher is
recommended for stable performance over temperature and voltage.
8.3.6 Overcurrent and Short Circuit Protection
The LMR50410-Q1 incorporates both peak and valley inductor current limit to provide protection to the device
from overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor
current runaway during short circuits on the output, while both peak and valley limits work together to limit the
maximum output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is
used for sustained short circuits.
High-side MOSFET overcurrent protection is implemented by the nature of the Peak Current Mode control. The
high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch
current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle.
See Section 8.2 for more details. The peak current of high-side switch is limited by a clamped maximum peak
current threshold Isc (see Section 7.5), which is constant.
The current going through low-side MOSFET is also sensed and monitored. When the low-side switch turns on,
the inductor current begins to ramp down. The low-side switch is not turned OFF at the end of a switching cycle
if its current is above the low-side current limit ILS_LIMIT (see Section 7.5). The low-side switch is kept ON so that
inductor current keeps ramping down, until the inductor current ramps below the I LS_LIMIT. Then the low-side
switch is turned OFF and the high-side switch is turned on after a dead time. After I LS_LIMIT is achieved, peak
and valley current limit controls the max current deliver and it can be calculated using Equation 6.
IOUT
=
max
I LS_LIMIT +ISC
2
(6)
If the feedback voltage is lower than 40% of the VREF, the current of the low-side switch triggers ILS_LIMIT for 256
consecutive cycles and hiccup current protection mode is activated. In hiccup mode, the converter shuts down
and keeps off for a period of hiccup, T HICCUP (135 ms typical) before the LMR50410-Q1 tries to start again. If
overcurrent or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup
mode reduces power dissipation under severe overcurrent conditions, prevents over-heating and potential
damage to the device.
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For FPWM version, the inductor current is allowed to go negative. When this current exceed the low-side
negative current limit I LS_NEG, the low-side switch is turned off and high-side switch is turned on immediately.
This is used to protect the low-side switch from excessive negative current.
8.3.7 Soft Start
The integrated soft-start circuit prevents input inrush current impacting the LMR50410-Q1 and the input power
supply. Soft start is achieved by slowly ramping up the internal reference voltage when the device is first enabled
or powered up. The typical soft-start time is 1.8 ms.
The LMR50410-Q1 also employs overcurrent protection blanking time, T OCP_BLK (33 ms typical), at the
beginning of power up. Without this feature, in applications with a large amount of output capacitors and high V
OUT, the inrush current is large enough to trigger the current-limit protection, which can cause a false start as the
device entering into hiccup mode. This results in a continuous recycling of soft start without raising up to the
programmed output voltage. The LMR50410 is able to charge the output capacitor to the programmed V OUT by
controlling the average inductor current during the start-up sequence in the blanking time TOCP_BLK.
8.3.8 Thermal Shutdown
The LMR50410-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C. Both high-side and low-side FETs stop switching in thermal shutdown. Once the die
temperature falls below 158°C, the device reinitiates the power-up sequence controlled by the internal soft-start
circuitry.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON/OFF control for the LMR50410-Q1. When VEN is below 0.95 V, the device is in
shutdown mode. The LMR50410-Q1 also employs VIN undervoltage lock out protection (UVLO). If VIN voltage is
below its UVLO threshold 3.25 V, the converter is turned off.
8.4.2 Active Mode
The LMR50410-Q1 is in Active Mode when both VEN and VIN are above their respective operating threshold. The
simplest way to enable the LMR50410-Q1 is to connect the EN pin to VIN pin. This allows self-start-up when the
input voltage is in the operating range of 4.0 V to 36 V. See Section 8.3.3 for details on setting these operating
levels.
In Active Mode, depending on the load current, the LMR50410-Q1 is in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is greater than half of
the peak-to-peak inductor current ripple (for both PFM and FPWM versions)
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is less than half of
the peak-to-peak inductor current ripple(only for PFM version)
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for
PFM version)
4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for
FPWM version).
8.4.3 CCM Mode
Continuous Conduction Mode (CCM) operation is employed in the LMR50410-Q1 when the load current is
greater than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed,
output voltage ripple is at a minimum in this mode and the maximum output current of 1 A can be supplied by the
LMR50410-Q1.
8.4.4 Light-Load Operation (PFM Version)
For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the
LMR50410-Q1 operates in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode
(DEM). In DCM operation, the low-side switch is turned off when the inductor current drops to I LS_ZC (20 mA
typical) to improve efficiency. Both switching losses and conduction losses are reduced in DCM, compared to
forced PWM operation at light load.
During light load operation, Pulse Frequency Modulation (PFM) mode is activated to maintain high efficiency
operation. When either the minimum high-side switch ON time t ON_MIN or the minimum peak inductor current I
PEAK_MIN (300 mA typical) is reached, the switching frequency decreases to maintain regulation. In PFM mode,
switching frequency is decreased by the control loop to maintain output voltage regulation when load current
reduces. Switching loss is further reduced in PFM operation due to a significant drop in effective switching
frequency.
8.4.5 Light-Load Operation (FPWM Version)
For FPWM version, LMR50410-Q1 is locked in PWM mode at full load range. This operation is maintained, even
in no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off
reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching
frequency.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The LMR50410-Q1 is a step-down DC-to-DC converter. It is typically used to convert a higher input voltage to a
lower output DC voltage with a maximum output current of 1 A. The following design procedure can be used to
select components for the LMR50410-Q1. Alternately, the WEBENCH® software can be used to generate
complete designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and
accesses comprehensive databases of components. Go to ti.com for more details.
9.2 Typical Application
The LMR50410-Q1 only requires a few external components to convert from a wide voltage range supply to a
fixed output voltage. Figure 9-1 shows a basic schematic.
VIN 12 V
VIN
CB
CIN
2.2 µF
CBOOT
0.1 µF
L
4.7 µH
EN
VOUT 5 V
SW
RFBT
88.7 NŸ
GND
COUT
10 µF
FB
RFBB
22.1 NŸ
Figure 9-1. Application Circuit
The external components have to fulfill the needs of the application and the stability criteria of the control loop of
the device. Table 9-1 can be used to simplify the output filter component selection.
Table 9-1. L and COUT Typical Values
fSW (MHz)
2.1
(1)
VOUT (V)
L (µH)
COUT (µF) (1)
RFBT (kΩ)
RFBB (kΩ)
3.3
3.3
10 µF / 10 V
51
22.1
5
4.7
10 µF / 10 V
88.7
22.1
12
10
22 µF / 25 V
243
22.1
Ceramic capacitor is used in this table.
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9.2.1 Design Requirements
The detailed design procedure is described based on a design example. For this design example, use the
parameters listed in the following table as the input parameters.
Table 9-2. Design Example Parameters
PARAMETER
Input voltage, VIN
VALUE
12 V typical, range from 6 V to 36 V
Output voltage, VOUT
5 V ±3%
Maximum output current, IOUT_MAX
1A
Output overshoot/ undershoot (0 A to 1 A )
5%
Output voltage ripple
0.5%
Operating frequency
2.1 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR50410-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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9.2.2.2 Output Voltage Set-Point
The output voltage of the LMR50410-Q1 device is externally adjustable using a resistor divider network. The
divider network is comprised of top feedback resistor R FBT and bottom feedback resistor R FBB. Equation 7 is
used to determine the output voltage of the converter:
R FBT =
V OUT - V REF
V REF
× R FBB
(7)
Choose the value of R FBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the V REF = 1.0 V, the R
FBT value can then be calculated using Equation 7. The formula yields to a value 88.4 kΩ, a standard value of
88.7 kΩ is selected.
9.2.2.3 Switching Frequency
The higher switching frequency allows for lower value inductors and smaller output capacitors, which results in
smaller solution size and lower component cost. However, higher switching frequency brings more switching
loss, making the solution less efficient and produce more heat. The switching frequency is also limited by the
minimum on-time of the integrated power switch, the input voltage, the output voltage, and the frequency shift
limitation as mentioned in Section 8.3.4. For this example, a switching frequency of 2.1 MHz is selected.
9.2.2.4 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The
inductance is based on the desired peak-to-peak ripple current Δi L. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance L MIN. Use
Equation 9 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current of the device. A reasonable value of K IND must
be 20% to 60% of maximum I OUT supported by converter. During an instantaneous overcurrent operation event,
the RMS and peak inductor current can be high. The inductor saturation current must be higher than peak
current limit level.
ûL L
L MIN =
V OUT × V IN_MAX - V OUT
V IN_MAX × L × f SW
VIN_MAX - V OUT
I OUT × K IND
×
(8)
V OUT
VIN_MAX × f SW
(9)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. Too low of
an inductance can generate too large of an inductor current ripple such that overcurrent protection at the full load
can be falsely triggered. It also generates more inductor core loss since the current ripple is larger. Larger
inductor current ripple also implies larger output voltage ripple with the same output capacitors. With peak
current mode control, it is recommended to have adequate amount of inductor ripple current. A larger inductor
ripple current improves the comparator signal-to-noise ratio.
For this design example, choose K IND = 0.4. The minimum inductor value is calculated to be 5.16 µH. Choose
the nearest standard 4.7-µH ferrite inductor with a capability of 1.5-A RMS current and 2.5-A saturation current.
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9.2.2.5 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. It is generally desired to minimize the output
capacitance to keep cost and size down. The output capacitor or capacitors, C OUT, must be chosen with care
since it directly affects the steady state output voltage ripple, loop stability, and output voltage overshoot and
undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One
part is caused by the inductor ripple current flowing through the Equivalent Series Resistance (ESR) of the
output capacitors:
û9 OUT_ESR
ûL L × ESR = K IND × I OUT × ESR
(10)
The other part is caused by the inductor current ripple charging and discharging the output capacitors:
û9 OUT_C
ûL L
. IND × I OUT
8 × f SW × C OUT
8 × f SW × C OUT
(11)
The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than
the sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rates. When a large load step occurs, output
capacitors provide the required charge before the inductor current can slew to an appropriate level. The control
loop of the converter usually requires eight or more clock cycles to regulate the inductor current equal to the new
load level during this time. The output capacitance must be large enough to supply the current difference for 8
clock cycles to maintain the output voltage within the specified range. Equation 12 shows the minimum output
capacitance needed for a specified VOUT overshoot and undershoot.
C OUT >
8 × I OH - I OL
1
×
2 f SW × û9 OUT_SHOOT
(12)
where
•
•
•
•
KIND = Ripple ratio of the inductor current (ΔiL / IOUT)
IOL = Low level output current during load transient
IOH = High level output current during load transient
VOUT_SHOOT = Target output voltage overshoot or undershoot
For this design example, the target output ripple is 30 mV. Assuming ΔV OUT_ESR = ΔV OUT_C = 30 mV, choose K
= 0.4. Equation 10 yields ESR no larger than 75 mΩ and Equation 11 yields C OUT no smaller than 0.79 µF.
For the target overshoot and undershoot limitation of this design, ΔV OUT_SHOOT = 8% × V OUT = 400 mV. The C
OUT can be calculated to be no less than 4.76 µF by Equation 12. In summary, the most stringent criteria for the
output capacitor is 4.76 µF. Considering derating, one 10-µF, 10-V, X7R ceramic capacitor with 10-mΩ ESR is
used.
IND
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9.2.2.6 Input Capacitor Selection
The LMR50410-Q1 device requires a high frequency input decoupling capacitor or capacitor. The typical
recommended value for the high frequency decoupling capacitor is 2.2 µF or higher. A high-quality ceramic type
X5R or X7R with sufficiency voltage rating is recommended. The voltage rating must be greater than the
maximum input voltage. To compensate the derating of ceramic capacitors, a voltage rating of twice the
maximum input voltage is recommended. For this design, one 2.2-µF, X7R dielectric capacitor rated for 50 V is
used for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ, and the
current rating is 1 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close
as possible to the device pins.
9.2.2.7 Bootstrap Capacitor
Every LMR50410-Q1 design requires a bootstrap capacitor, C BOOT. The recommended bootstrap capacitor is
0.1 µF and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
9.2.2.8 Undervoltage Lockout Set-Point
The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R ENT and R
The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brown outs when the input voltage is falling. Equation 13 can be used to determine the VIN UVLO level.
ENB.
VIN_RISING = V ENH ×
R ENT + R ENB
R ENB
(13)
The EN rising threshold (V ENH) for LMR50410-Q1 is set to be 1.23 V (typical). Choose a value of 200 kΩ for R
ENB to minimize input current from the supply. If the desired V IN UVLO level is at 6.0 V, then the value of R ENT
can be calculated using Equation 14:
§ V IN_RISING
·
R ENT = ¨
- 1 ¸ × R ENB
¨ V ENH
¸
©
¹
(14)
The above equation yields a value of 775.6 kΩ, a standard value of 768 kΩ is selected. The resulting falling
UVLO threshold, equals 5.3 V, can be calculated by Equation 15 where EN hysteresis voltage, V EN_HYS, is 0.13
V (typical).
VIN_FALLING = V ENH - V EN_HYS ×
R ENT + R ENB
R ENB
(15)
9.2.2.9 Maximum Ambient Temperature
As with any power conversion device, the LMR50410-Q1 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance, R
θJA, of the device and PCB combination. The maximum internal die temperature for the LMR50410-Q1 must be
limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. Equation 16 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (T A) and larger values of R θJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of R θJA is more difficult to estimate. As stated in the Semiconductor and IC
Package Thermal Metrics Application Report, the value of R θJA given in Section 7.4 is not valid for design
purposes and must not be used to estimate the thermal performance of the application. The values reported in
that table were measured under a specific set of conditions that are rarely obtained in an actual application.
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IOUT
MAX
TJ TA
1
K
˜
˜
R TJA
1 K VOUT
(16)
where
•
η = efficiency
The effective RθJA is a critical parameter and depends on many factors such as the following:
•
•
•
•
•
Power dissipation
Air temperature/flow
PCB area
Number of thermal vias under the package
Adjacent component placement
Figure 9-2 shows the typical curves of maximum output current versus ambient temperature. This data was
taken with a device and PCB combination, giving an RθJA which is 80°C/W. It must be remembered that the data
given in these graphs are for illustration purposes only and the actual performance in any given application
depends on all of the previously mentioned factors.
115
Ambient Temperature - °C
105
95
85
75
65
55
45
VIN = 12V
VIN = 24V
35
25
0.5
0.55
0.6
0.65
0.7 0.75 0.8 0.85
Output Current - A
0.9
0.95
1
Tama
Figure 9-2. Maximum Output Current versus Ambient Temperature
22
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Use the following resources as a guide to optimal thermal PCB design and estimating R θJA for a given
application environment:
•
•
•
•
•
•
•
Thermal Design by Insight not Hindsight Application Report
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
Semiconductor and IC Package Thermal Metrics Application Report
Thermal Design Made Simple with LM43603 and LM43602 Application Report
PowerPAD™ Thermally Enhanced Package Application Report
PowerPAD™ Made Easy Application Report
Using New Thermal Metrics Application Report
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: V IN = 12 V, V OUT = 5 V, f SW =2.1 MHz, L = 4.7 µH, C
OUT = 10 µF, TA = 25°C.
VSW [5V/div]
VSW [5V/div]
VOUT(AC) [10mV/div]
VOUT(AC) [10mV/div]
IL [1A/div]
IL [500mA/div]
Time [1ms/div]
IOUT = 1 A
Figure 9-3. Ripple at No Load
Time [400ns/div]
Figure 9-4. Ripple at Full Load
VIN [5V/div]
VEN [2V/div]
VOUT [2V/div]
VOUT [2V/div]
IL [1A/div]
IL [1A/div]
Time [1ms/div]
IOUT = 1 A
IOUT = 1 A
Figure 9-5. Start Up by VIN
Time [1ms/div]
Figure 9-6. Start-Up by EN
VOUT [2V/div]
IOUT [200mA/div]
IL [1A/div]
VOUT(AC) [100mV/div]
IOUT = 0.5 to 1 A, 100mA / s
Time [200us/div]
Figure 9-7. Load Transient
24
IOUT = 0 mA to short
Time [100ms/div]
Figure 9-8. Short Protection
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VOUT [2V/div]
IL [1A/div]
IOUT = short to 0 mA
Time [100ms/div]
Figure 9-9. Short Recovery
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10 Power Supply Recommendations
The LMR50410-Q1 is designed to operate from an input voltage supply range between 4.0 V and 36 V. This
input supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage.
The resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LMR50410-Q1 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LMR50410-Q1 additional bulk capacitance can be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 10-µF
or 22-µF electrolytic capacitor is a typical choice.
26
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11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The input bypass capacitor CIN must be placed as close as possible to the VIN and GND pins. Grounding for
both the input and output capacitors should consist of localized top side planes that connect to the GND pin.
2. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB, must be located close to the
FB pin. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT
sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.
3. Use ground plane in one of the middle layers as noise shielding and heat dissipation path if possible.
4. Make VIN, VOUT, and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
5. Provide adequate device heat-sinking. GND, VIN, and SW pins provide the main heat dissipation path, make
the GND, VIN, and SW plane area as large as possible. Use an array of heat-sinking vias to connect the top
side ground plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these
thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area
is used for heat-sinking to keep the junction temperature below 125°C.
11.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass
capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing a
ceramic bypass capacitor or capacitors as close as possible to the VIN and GND pins is the key to EMI
reduction.
The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) must be used for high current
conduction path to minimize parasitic resistance. The output capacitors must be placed close to the V OUT end of
the inductor and closely grounded to GND pin.
11.1.2 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider close
to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace
length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from V
OUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for
voltage drops along the traces and provides the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider must be routed away from the SW node path and the inductor to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. It is recommended to route the voltage
sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that
there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further
shielding for the voltage feedback path from EMI noises.
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11.2 Layout Example
Notes:
VOUT
1. BOOT capacitor should be
close to CB and SW pins.
2. SW area should be small.
Output Bypass
Capacitor
Output
Inductor
BOOT
Capacitor
3. Output voltage set resistors
should be close to FB pin.
4. Input bypass capacitor
should be close to VIN and GND
pins.
5. Use ground plane to keep a
low GND impedance.
GND
CB
SW
GND
VIN
FB
EN
VIN
Input Bypass
Capacitor
Output Voltage
Set Resistors
GND
VIA (Connect to GND Plane)
Figure 11-1. Layout
28
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR50410-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMR50410Y3FQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
4AY3
LMR50410Y5FQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
4AY5
LMR50410YFQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
4AYF
LMR50410YQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
4AYA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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