LMT86-Q1
SNIS201A – OCTOBER 2017 – REVISED JUNE 2022
LMT86-Q1 2.2-V, SC70,
Analog Temperature Sensor
1 Features
3 Description
•
The LMT86-Q1 are precision CMOS temperature
sensors with ±0.4°C typical accuracy (±2.7°C
maximum) and a linear analog output voltage that
is inversely proportional to temperature. The 2.2-V
supply voltage operation, 5.4-μA quiescent current,
and 0.7-ms power-on time enable effective powercycling architectures to minimize power consumption
for battery-powered applications such as drones
and sensor nodes. The LMT86-Q1-Q1 device
is AEC-Q100 Grade 0 qualified and maintains
±2.7°C maximum accuracy over the full operating
temperature range without calibration; this makes the
LMT86-Q1-Q1 suitable for automotive applications
such as infotainment, cluster, and powertrain systems.
The accuracy over the wide operating range and other
features make the LMT86-Q1 an excellent alternative
to thermistors.
•
•
•
•
•
•
•
•
•
•
LMT86-Q1-Q1 is AEC-Q100 Qualified for
Automotive Applications:
– Device Temperature Grade 0: –40°C to +150°C
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Very Accurate: ±0.4°C Typical
Low 2.2-V Operation
Average Sensor Gain of –10.9 mV/°C
Low 5.4-µA Quiescent Current
Wide Temperature Range: –50°C to 150°C
Output is Short-Circuit Protected
Push-Pull Output With ±50-µA Drive Capability
Footprint Compatible With the Industry-Standard
LM20/19 and LM35 Temperature Sensors
Cost-Effective Alternative to Thermistors
2 Applications
Automotive
Infotainment and Cluster
Powertrain Systems
Smoke and Heat Detectors
Drones
Appliances
Device Information(1)
PART NUMBER
LMT86-Q1
(1)
100%
PACKAGE
SOT (5)
BODY SIZE (NOM)
2.00 mm × 1.25 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VDD (+2.2V to +5.5V)
90%
FINAL TEMPERATURE
•
•
•
•
•
•
For devices with different average sensor gains and
comparable accuracy, refer to Comparable Alternative
Devices for alternative devices in the LMT8x family.
80%
VDD
70%
LMT86
60%
CBP
50%
OUT
40%
30%
GND
20%
LMT8xLPG
Thermistor
10%
0
0
20
40
60
TIME (s)
80
100
D003
Copyright © 2016, Texas Instruments Incorporated
Output Voltage vs Temperature
* Fast thermal response NTC
Thermal Time Constant
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMT86-Q1
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SNIS201A – OCTOBER 2017 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Accuracy Characteristics............................................ 5
7.6 Electrical Characteristics.............................................5
7.7 Typical Characteristics................................................ 6
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Applications.................................................. 12
10 Power Supply Recommendations..............................13
11 Layout........................................................................... 14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Receiving Notification of Documentation Updates..15
12.2 Support Resources................................................. 15
12.3 Trademarks............................................................. 15
12.4 Electrostatic Discharge Caution..............................15
12.5 Glossary..................................................................15
13 Mechanical, Packaging, and Orderable
Information.................................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2017) to Revision A (June 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added Functional Safety bullets to the Features section....................................................................................1
2
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5 Device Comparison
Table 5-1. Available Device Packages
ORDER NUMBER(1)
PACKAGE
PIN
BODY SIZE (NOM)
MOUNTING TYPE
LMT86DCK
SOT (AKA(2): SC70, DCK)
5
2.00 mm × 1.25 mm
Surface Mount
LMT86LP
TO-92 (AKA(2): LP)
3
4.30 mm × 3.50 mm
Through-hole; straight leads
LMT86LPG
TO-92S (AKA(2): LPG)
3
4.00 mm × 3.15 mm
Through-hole; straight leads
LMT86LPM
TO-92
(AKA(2):
3
4.30 mm × 3.50 mm
Through-hole; formed leads
LMT86DCK-Q1
SOT (AKA(2): SC70, DCK)
5
2.00 mm × 1.25 mm
Surface Mount
(1)
(2)
LPM)
For all available packages and complete order numbers, see the Package Option addendum at the end of the data sheet.
AKA = Also Known As
Table 5-2. Comparable Alternative Devices
DEVICE NAME
AVERAGE OUTPUT SENSOR GAIN
POWER SUPPLY RANGE
LMT84-Q1
–5.5 mV/°C
1.5 V to 5.5 V
LMT85-Q1
–8.2 mV/°C
1.8 V to 5.5 V
LMT86-Q1
–10.9 mV/°C
2.2 V to 5.5 V
LMT87-Q1
–13.6 mV/°C
2.7 V to 5.5 V
6 Pin Configuration and Functions
1
5
GND
VDD
2
GND
LMT86
3
4
OUT
VDD
Figure 6-1. 5-Pin SOT (SC70) DCK Package (TOP VIEW)
Table 6-1. Pin Functions
PIN
NAME
GND
SOT (SC70)
1,
2(1)
TYPE
Ground
DESCRIPTION
EQUIVALENT CIRCUIT
N/A
FUNCTION
Power Supply Ground
VDD
OUT
3
Analog
Output
VDD
4, 5
Power
Outputs a voltage that is inversely proportional
to temperature
GND
(1)
N/A
Positive Supply Voltage
Direct connection to the back side of the die
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7 Specifications
7.1 Absolute Maximum Ratings
See (1) (2)
MIN
MAX
UNIT
Supply voltage
–0.3
6
V
Voltage at output pin
–0.3
(VDD + 0.5)
V
Output current
–7
7
mA
Input current at any pin (3)
–5
Maximum junction temperature (TJMAX)
Storage temperature, Tstg
(1)
(2)
(3)
–65
5
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability
Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. Reflow
temperature profiles are different for lead-free and non-lead-free packages.
When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V), the current at that pin should be limited to 5 mA.
7.2 ESD Ratings
VALUE
UNIT
LMT86DCK-Q1 in SC70 package
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2500
Charged-device model (CDM), per AEC Q100-011
±1000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
Specified temperature
Supply voltage (VDD)
MAX
UNIT
TMIN ≤ TA ≤ TMAX
°C
−50 ≤ TA ≤ 150
°C
2.2
5.5
V
7.4 Thermal Information
LMT86-Q1
THERMAL METRIC(1) (2)
DCK (SOT/SC70)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance (3) (4)
275
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
84
°C/W
RθJB
Junction-to-board thermal resistance
56
°C/W
ψJT
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
55
°C/W
(1)
(2)
(3)
(4)
4
For information on self-heating and thermal response time, see section Mounting and Thermal Conductivity.
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
The junction to ambient thermal resistance (RθJA) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
Changes in output due to self-heating can be computed by multiplying the internal dissipation by the thermal resistance.
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7.5 Accuracy Characteristics
These limits do not include DC load regulation. These stated accuracy limits are with reference to the values in Table 8-1.
MIN(1)
TYP(2)
MAX(1)
40°C to 150°C; VDD = 2.2 V to 5.5 V
–2.7
±0.4
2.7
°C
0°C to 40°C; VDD = 2.4 V to 5.5 V
–2.7
±0.7
2.7
°C
PARAMETER
Temperature
accuracy(3)
CONDITIONS
0°C to 70°C; VDD = 3.0 V to 5.5 V
±0.3
–50°C to 0°C; VDD = 3.0 V to 5.5 V
–2.7
(1)
(2)
(3)
°C
±0.7
–50°C to 0°C; VDD = 3.6 V to 5.5 V
UNIT
2.7
±0.25
°C
°C
Limits are specified to TI's AOQL (Average Outgoing Quality Level).
Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
Accuracy is defined as the error between the measured and reference output voltages, tabulated in the Transfer Table at the specified
conditions of supply gain setting, voltage, and temperature (expressed in °C). Accuracy limits include line regulation within the
specified conditions. Accuracy limits do not include load regulation; they assume no dc load.
7.6 Electrical Characteristics
Unless otherwise noted, these specifications apply for +VDD = 2.2 V to 5.5 V. MIN and MAX limits apply for TA = TJ = TMIN to
TMAX , unless otherwise noted; typical values apply for TA = TJ = 25°C.
PARAMETER
Average sensor gain (output
transfer function slope)
Load regulation(3)
TEST CONDITIONS
MIN(1)
–30°C and 90°C used to calculate average
sensor gain
Source ≤ 50 μA, (VDD – VOUT) ≥ 200 mV
Supply current
CL
Output load capacitance
(1)
(2)
(3)
(4)
(5)
MAX(1)
–10.9
–1
Sink ≤ 50 μA, VOUT ≥ 200 mV
UNIT
mV/°C
–0.22
0.26
Line regulation(4)
IS
TYP(2)
mV
1
200
mV
μV/V
TA = 30°C to 150°C, (VDD – VOUT) ≥ 100 mV
5.4
8.1
μA
TA = –50°C to 150°C, (VDD – VOUT) ≥ 100 mV
5.4
9
μA
1.9
ms
50
µA
1100
Power-on time(5)
CL= 0 pF to 1100 pF
Output drive
TA = TJ = 25°C
0.7
–50
pF
Limits are specific to TI's AOQL (Average Outgoing Quality Level).
Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
Source currents are flowing out of the LMT86-Q1. Sink currents are flowing into the LMT86-Q1.
Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest
supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in Output Voltage Shift.
Specified by design and characterization.
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7.7 Typical Characteristics
4
TEMPERATURE ERROR (ºC)
3
2
1
0
-1
-2
-3
-4
-50
-25
0
25
50
75
100 125 150
TEMPERATURE (ºC)
Figure 7-1. Temperature Error vs Temperature
6
Figure 7-2. Minimum Operating Temperature vs Supply Voltage
Figure 7-3. Supply Current vs Temperature
Figure 7-4. Supply Current vs Supply Voltage
Figure 7-5. Load Regulation, Sourcing Current
Figure 7-6. Load Regulation, Sinking Current
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7.7 Typical Characteristics (continued)
Figure 7-7. Change in VOUT vs Overhead Voltage
Figure 7-8. Supply-Noise Gain vs Frequency
Figure 7-9. Output Voltage vs Supply Voltage
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8 Detailed Description
8.1 Overview
The LMT86-Q1 is an analog output temperature sensor. The temperature-sensing element is comprised of a
simple base emitter junction that is forward biased by a current source. The temperature-sensing element is then
buffered by an amplifier and provided to the OUT pin. The amplifier has a simple push-pull output stage thus
providing a low impedance output source.
8.2 Functional Block Diagram
Full-Range Celsius Temperature Sensor (−50°C to +150°C)
VDD
OUT
Thermal Diodes
GND
8.3 Feature Description
8.3.1 LMT86-Q1 Transfer Function
Table 8-1 shows the output voltage of the LMT86-Q1 across the complete operating temperature range. This
table is the reference from which the LMT86-Q1 accuracy specifications (listed in the Accuracy Characteristics
table) are determined. This table can be used, for example, in a host processor look-up table. A file containing
this data is available for download at LMT86-Q1 product folder under Tools and Software Models.
Table 8-1. LMT86-Q1 Transfer Table
TEMP
(°C)
8
VOUT
(mV)
TEMP
(°C)
VOUT
(mV)
TEMP
(°C)
VOUT
(mV)
TEMP
(°C)
VOUT
(mV)
TEMP
(°C)
VOUT
(mV)
-50
2616
-10
2207
30
1777
70
1335
110
883
-49
2607
-9
2197
31
1766
71
1324
111
872
-48
2598
-8
2186
32
1756
72
1313
112
860
-47
2589
-7
2175
33
1745
73
1301
113
849
-46
2580
-6
2164
34
1734
74
1290
114
837
-45
2571
-5
2154
35
1723
75
1279
115
826
-44
2562
-4
2143
36
1712
76
1268
116
814
-43
2553
-3
2132
37
1701
77
1257
117
803
-42
2543
-2
2122
38
1690
78
1245
118
791
-41
2533
-1
2111
39
1679
79
1234
119
780
-40
2522
0
2100
40
1668
80
1223
120
769
-39
2512
1
2089
41
1657
81
1212
121
757
-38
2501
2
2079
42
1646
82
1201
122
745
-37
2491
3
2068
43
1635
83
1189
123
734
-36
2481
4
2057
44
1624
84
1178
124
722
-35
2470
5
2047
45
1613
85
1167
125
711
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Table 8-1. LMT86-Q1 Transfer Table (continued)
TEMP
(°C)
VOUT
(mV)
TEMP
(°C)
VOUT
(mV)
TEMP
(°C)
VOUT
(mV)
TEMP
(°C)
VOUT
(mV)
TEMP
(°C)
VOUT
(mV)
-34
2460
6
2036
46
1602
86
1155
126
699
-33
2449
7
2025
47
1591
87
1144
127
688
-32
2439
8
2014
48
1580
88
1133
128
676
-31
2429
9
2004
49
1569
89
1122
129
665
-30
2418
10
1993
50
1558
90
1110
130
653
-29
2408
11
1982
51
1547
91
1099
131
642
-28
2397
12
1971
52
1536
92
1088
132
630
-27
2387
13
1961
53
1525
93
1076
133
618
-26
2376
14
1950
54
1514
94
1065
134
607
-25
2366
15
1939
55
1503
95
1054
135
595
-24
2355
16
1928
56
1492
96
1042
136
584
-23
2345
17
1918
57
1481
97
1031
137
572
-22
2334
18
1907
58
1470
98
1020
138
560
-21
2324
19
1896
59
1459
99
1008
139
549
-20
2313
20
1885
60
1448
100
997
140
537
-19
2302
21
1874
61
1436
101
986
141
525
-18
2292
22
1864
62
1425
102
974
142
514
-17
2281
23
1853
63
1414
103
963
143
502
-16
2271
24
1842
64
1403
104
951
144
490
-15
2260
25
1831
65
1391
105
940
145
479
-14
2250
26
1820
66
1380
106
929
146
467
-13
2239
27
1810
67
1369
107
917
147
455
-12
2228
28
1799
68
1358
108
906
148
443
-11
2218
29
1788
69
1346
109
895
149
432
150
420
Although the LMT86-Q1 is very linear, its response does have a slight umbrella parabolic shape. Table 8-1 very
accurately reflects this shape. The Transfer Table can be calculated by using the parabolic equation (Equation
1).
mV
mV
ª
º ª
2º
VTEMP mV = 1777.3mV - «10.888
T - 30°C » - «0.00347 2 T - 30°C »
°C
¬
¼ ¬
°C
¼
(1)
The parabolic equation is an approximation of the transfer table and the accuracy of the equation degrades
slightly at the temperature range extremes. Equation 1 can be solved for T resulting in:
T
10 .888
10 .888
2
4 u 0.00347 u 1777 .3 VTEMP mV
2 u ( 0.00347 )
30
(2)
For an even less accurate linear approximation, a line can easily be calculated over the desired temperature
range from the table using the two-point equation (Equation 3):
·
¹
V - V1 =
V2 - V1
T2 - T1
· u (T - T1)
¹
(3)
where
•
•
•
V is in mV,
T is in °C,
T1 and V1 are the coordinates of the lowest temperature,
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•
and T2 and V2 are the coordinates of the highest temperature.
For example, if the user wanted to resolve this equation, over a temperature range of 20°C to 50°C, they would
proceed as follows:
1558 mV - 1885 mV·
u (T - 20oC)
50oC - 20oC
¹
·
¹
V - 1885 mV =
(4)
o
o
V - 1885 mV = (-10.9 mV / C) u (T - 20 C)
(5)
o
V = (-10.9 mV / C) u T + 2103 mV
(6)
Using this method of linear approximation, the transfer function can be approximated for one or more
temperature ranges of interest.
8.4 Device Functional Modes
8.4.1 Mounting and Thermal Conductivity
The LMT86-Q1 can be applied easily in the same way as other integrated-circuit temperature sensors. It can be
glued or cemented to a surface.
To ensure good thermal conductivity, the backside of the LMT86-Q1 die is directly attached to the GND pin. The
temperatures of the lands and traces to the other leads of the LMT86-Q1 will also affect the temperature reading.
Alternatively, the LMT86-Q1 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath
or screwed into a threaded hole in a tank. As with any IC, the LMT86-Q1 and accompanying wiring and circuits
must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate
at cold temperatures where condensation can occur. If moisture creates a short circuit from the output to ground
or VDD, the output from the LMT86-Q1 will not be correct. Printed-circuit coatings are often used to ensure that
moisture cannot corrode the leads or circuit traces.
The thermal resistance junction to ambient (RθJA or θJA) is the parameter used to calculate the rise of a device
junction temperature due to its power dissipation. Use Equation 7 to calculate the rise in the LMT86-Q1 die
temperature:
TJ = TA + TJA ª¬(VDDIS ) + (VDD - VO ) IL º¼
(7)
where
•
•
•
•
TA is the ambient temperature,
IS is the supply current,
ILis the load current on the output,
and VO is the output voltage.
For example, in an application where TA = 30°C, VDD = 5 V, IS = 5.4 µA, VO = 1777 mV junction temp 30.014°C
self-heating error of 0.014°C. Because the junction temperature of the LMT86-Q1 is the actual temperature
being measured, take care to minimize the load current that the LMT86-Q1 is required to drive. The Thermal
Information table shows the thermal resistance of the LMT86-Q1.
8.4.2 Output Noise Considerations
A push-pull output gives the LMT86-Q1 the ability to sink and source significant current. This is beneficial
when, for example, driving dynamic loads like an input stage on an analog-to-digital converter (ADC). In these
applications the source current is required to quickly charge the input capacitor of the ADC. The LMT86-Q1 is
ideal for this and other applications which require strong source or sink current.
The LMT86-Q1 supply-noise gain (the ratio of the AC signal on VOUT to the AC signal on VDD) was measured
during bench tests. Figure 7-8 shows the typical attenuation found in the Typical Characteristics section. A load
capacitor on the output can help to filter noise.
10
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For operation in very noisy environments, some bypass capacitance should be present on the supply within
approximately 5 centimeters of the LMT86-Q1.
8.4.3 Capacitive Loads
The LMT86-Q1 handles capacitive loading well. In an extremely noisy environment, or when driving a switched
sampling input on an ADC, it may be necessary to add some filtering to minimize noise coupling. Without any
precautions, Figure 8-1 shows how the LMT86-Q1 can drive a capacitive load less than or equal to 1100 pF. For
capacitive loads greater than 1100 pF, Figure 8-2 shows how a series resistor may be required on the output.
VDD
LMT86
OPTIONAL
BYPASS
CAPACITANCE
OUT
GND
CLOAD ” 1100 pF
Figure 8-1. LMT86-Q1 No Decoupling Required for Capacitive Loads Less Than 1100 pF
VDD
RS
LMT86
OPTIONAL
BYPASS
CAPACITANCE
OUT
GND
CLOAD > 1100 pF
Figure 8-2. LMT86-Q1 With Series Resistor for Capacitive Loading Greater Than 1100 pF
Table 8-2. Recommended Series Resistor Values
CLOAD
MINIMUM RS
1.1 nF to 99 nF
3 kΩ
100 nF to 999 nF
1.5 kΩ
1 μF
800 Ω
8.4.4 Output Voltage Shift
The LMT86-Q1 device is very linear over temperature and supply voltage range. Due to the intrinsic behavior of
an NMOS/PMOS rail-to-rail buffer, a slight shift in the output can occur when the supply voltage is ramped over
the operating range of the device. The location of the shift is determined by the relative levels of VDD and VOUT.
The shift typically occurs when VDD – VOUT = 1 V.
This slight shift (a few millivolts) takes place over a wide change (approximately 200 mV) in VDD or VOUT.
Because the shift takes place over a wide temperature change of 5°C to 20°C, VOUT is always monotonic. The
accuracy specifications in the Accuracy Characteristics table already include this possible shift.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMT86-Q1 features make it suitable for many general temperature-sensing applications. It can operate
down to 2.2-V supply with 5.4-µA power consumption, making it ideal for battery-powered devices.
9.2 Typical Applications
9.2.1 Connection to an ADC
Simplified Input Circuit of
SAR Analog-to-Digital Converter
Reset
+2.2V to +5.5V
Input
Pin
LMT86
VDD
CBP
RMUX
RSS
Sample
OUT
GND
CMUX
CFILTER
CSAMPLE
Figure 9-1. Suggested Connection to a Sampling Analog-to-Digital Converter Input Stage
9.2.1.1 Design Requirements
Most CMOS ADCs found in microcontrollers and ASICs have a sampled data comparator input structure. When
the ADC charges the sampling cap, it requires instantaneous charge from the output of the analog source such
as the LMT86 temperature sensor and many op amps. This requirement is easily accommodated by the addition
of a capacitor, CFILTER.
9.2.1.2 Detailed Design Procedure
The size of CFILTER depends on the size of the sampling capacitor and the sampling frequency. Because not all
ADCs have identical input stages, the charge requirements will vary. This general ADC application is shown as
an example only.
9.2.1.3 Application Curve
3.0
OUTPUT VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0.0
±50
0
50
100
150
TEMPERATURE (ƒC)
C001
Figure 9-2. Analog Output Transfer Function
12
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9.2.2 Conserving Power Dissipation With Shutdown
VDD
SHUTDOWN
VOUT
LMT86
Any logic
device output
Figure 9-3. Conserving Power Dissipation With Shutdown
9.2.2.1 Design Requirements
Because the power consumption of the LMT86-Q1 is less than 9 µA, it can simply be powered directly from any
logic gate output and therefore not require a specific shutdown pin. The device can even be powered directly
from a microcontroller GPIO. In this way, it can easily be turned off for cases such as battery-powered systems
where power savings are critical.
9.2.2.2 Detailed Design Procedure
Simply connect the VDD pin of the LMT86-Q1 directly to the logic shutdown signal from a microcontroller.
9.2.2.3 Application Curves
Time: 500 µs/div; Top Trace: VDD 1 V/div; Bottom Trace: OUT 1
V/div
Figure 9-4. Output Turnon Response Time Without
a Capacitive Load and VDD = 3.3 V
Time: 500 µs/div; Top Trace: VDD 2 V/div; Bottom Trace: OUT 1
V/div
Figure 9-6. Output Turnon Response Time Without
a Capacitive Load and VDD = 5 V
Time: 500 µs/div; Top Trace: VDD 1 V/div; Bottom Trace: OUT 1
V/div
Figure 9-5. Output Turnon Response Time With a
1.1-nF Capacitive Load and VDD = 3.3 V
Time: 500 µs/div; Top Trace: VDD 2 V/div; Bottom Trace: OUT 1
V/div
Figure 9-7. Output Turnon Response Time With
1.1-nF Capacitive Load and VDD = 5 V
10 Power Supply Recommendations
The low supply current and supply range (2.2 V to 5.5 V) of the LMT86-Q1 allow the device to easily be powered
from many sources. Power supply bypassing is optional and is mainly dependent on the noise on the power
supply used. In noisy systems, it may be necessary to add bypass capacitors to lower the noise that is coupled
to the output of the LMT86-Q1.
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11 Layout
11.1 Layout Guidelines
The LMT86-Q1 is simple to layout. If a power-supply bypass capacitor is used, the Layout Example shows how
to connect the capacitor to the device.
11.2 Layout Example
VIA to ground plane
VIA to power plane
GND
VDD
GND
OUT
0.01µ F
VDD
Figure 11-1. SC70 Package Recommended Layout
14
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMT86QDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-50 to 150
BTA
LMT86QDCKTQ1
ACTIVE
SC70
DCK
5
250
RoHS & Green
SN
Level-1-260C-UNLIM
-50 to 150
BTA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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