LMV1089
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SNAS441H – SEPTEMBER 2008 – REVISED MAY 2010
LMV1089 Dual Input, Far Field Noise Suppression Microphone Amplifier with Automatic
Calibration Capability
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FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
The LMV1089 is a fully analog dual differential input,
differential output, microphone array amplifier
designed to reduce background acoustic noise, while
delivering
superb
speech
clarity
in
voice
communication applications.
1
2
Low Power Consumption
Shutdown Function
No Added Processing Delay
Differential Inputs and Outputs
Automatic Calibration
Adjustable 6 - 48dB Gain
Excellent RF Immunity
Space-Saving 36–Bump DSBGA Package
The LMV1089 preserves near-field voice signals
within 4cm of the microphones while rejecting far-field
acoustic noise greater than 50cm from the
microphones. Up to 20dB of far-field rejection is
possible in a properly configured and calibrated
system.
APPLICATIONS
•
•
•
•
•
Part of the Powerwise™ family of energy efficient
solutions, the LMV1089 consumes only 1.1mA of
supply current providing superior performance over
DSP solutions consuming greater than ten times the
power.
Headset and Boom Microphones
Mobile Handsets and Two-Way Radios
Bluetooth and Other Powered Headsets
Hand-Held Voice Microphones
Equalized Stereo Microphone Preamplifier
KEY SPECIFICATIONS
•
•
•
•
•
•
•
Far Field Noise Suppression
(Electrical), (f = 1kHz) 37 dB
Supply Voltage 2.7 to 5.5 V
Supply Current 1.1 mA (typ)
Standby Current 0.7 µA (typ)
Signal-to-Noise Ratio (A-weighted) 65 dB (typ)
Total Harmonic Distortion + Noise 0.1 % (typ)
PSRR (217Hz) 96 dB (typ)
Far-field noise, > 50 cm
ois
e
Lo ud
The dual microphone inputs and the processed signal
output are differential to provide excellent noise
immunity. The microphones are biased with an
internal low-noise bias supply.
Up to 4 cm
Near-Field Voice
Tra
ffic
N
A quick calibration during the manufacturing test
process of the product containing the LMV1089
compensates the entire microphone system. This
calibration compensates for mismatch in microphone
gain and frequency response, as well as acoustical
path variances. The LMV1089 stores the calibration
coefficients in the on-chip EEPROM. The calibration
is initiated by an I2C command or by a logic pin
control.
LMV1089
Music
Analog
Filter
Crowd Noise
Anno
u n ce
Ma
ch
men
ine
Near-Field Voice
ts
ise
No
Low-cost
omnidirectional
microphones
EEPROM
Far field noise reduced
by up to 20 dB in properly
configured and calibrated
system
Figure 1.
1
2
Pure analog solution
provides superior
performance over DSP
solutions
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
LMV1089
SNAS441H – SEPTEMBER 2008 – REVISED MAY 2010
www.ti.com
Typical Application
VDD
Unprocessed Microphone Outputs
10 nF
1 PF
M2_UNP
M1_UNP
VDD
Mic
Bias
Auxiliary Control
T7
REF
Bias
LPF+
**
1.1 k:
**
1.1 k:
*
Mic2+
Mic2
OUT+
470 nF
Mic2-
Diff
SE
Mic1+
Mic1
+
Analog
Noise Canceling
Processor
470 nF
Diff
470 nF
Mic1-
LPF-
-
Optimized
Audio
Ouput
*
SE
OUT-
470 nF
**
1.1 k:
Control bus
**
1.1 k:
Pre Amp
Gain
(6-36 dB)
Shutdown
2
Calibration
Post Amp
Gain
(6-18 dB)
CAL
GB0 GB1
100 nF
GND
EN
PE
2
I CVDD
SCL
SDA
ADR
GA0 GA1
EEPROM
I C Interface
* The value of the low-pass filter capacitor is application dependent, see the application section for additional information.
** The value the microphone resistors is a standard value often used for electret microphones.
Figure 2. Typical Dual Microphone Far Field noise Cancelling Application
2
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Connection Diagram
A
B
C
D
E
F
6
Mic
Bias
MIC1+
MIC1-
REF
EN
CAL
5
MIC2+
M1_
UNP
GND
M2_
UNP
LPF+
LPF-
4
MIC2-
GND
GA0
GA1
OUT+
OUT-
3
PE
T5
GB0
GND
NC
VDD
2
TM
NC
NC
NC
GB1
I C
VDD
1
NC
NC
NC
ADR
SCL
SDA
2
Figure 3. 36–Bump DSBGA package
Figure 4. DSBGA Package View
Bottom View
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LMV1089
24
MIC2+
NC
T7
GB0
PE
T5
GND
NC
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MIC BIAS
SNAS441H – SEPTEMBER 2008 – REVISED MAY 2010
17
25
16
NC
MIC2-
GND
MIC1+
GA0
MIC1-
ADR
REF
SCL
M1_UNP
GB1
M2_UNP
CAL
32
SDA
9
8
VDD
OUT+
GA1
OUT-
GND
LPF-
LPF+
1
I2CVDD
EN
Figure 5. 32 Lead LQFP package
Figure 6. LQFP Package View
Bottom View
Pin Descriptions
4
Bump Number
Pin Name
Pin Function
Pin Type
A1
NC
No connect
No Connect
A2
T7
Auxiliary Control Manual Calibration = VDD
Auto Calibration = GND
Digital Input
A3
PE
Program Enable EEPROM
Digital Input
A4
MIC2–
microphone 2 negative input
Analog Input
A5
MIC2+
microphone 2 positive input
Analog Input
A6
Mic Bias
Microphone Bias
Analog Output
B1
NC
No Connect
No Connect
B2
NC
No Connect
No Connect
B3
T5
Float (do not connect to GND)
Production Test
B4
GND
amplifier ground
Ground
B5
M1_UNP
microphone 1 unprocessed output
Analog Output
B6
MIC1+
microphone 1 positive input
Analog Input
C1
NC
No Connect
No Connect
C2
NC
No Connect
No Connect
C3
GB0
default Post Amp Gain 0
Digital Input
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Pin Descriptions (continued)
C4
GA0
default Pre Amp Gain 0
Digital Input
C5
GND
amplifier ground
Ground
C6
MIC1–
amplifier ground
Analog Input
D1
ADR
I2C Address select
Digital Input
D2
NC
No Connect
No Connect
D3
GND
amplifier ground
Ground
D4
GA1
default Pre Amp Gain 1
Digital Input
D5
M2_UNP
microphone 2 unprocessed output
Analog Output
D6
REF
reference voltage de-coupling
Analog Reference
E1
SCL
I2C clock
Digital Input
E2
GB1
default Post Amp Gain 1
Digital Input
E3
NC
No Connect
No Connect
E4
OUT+
positive optimized audio output
Analog Output
E5
LPF+
Low Pass Filter for positive output
Analog Input
E6
EN
chip enable
Digital Input
2
F1
SDA
I C data
Digital Input/Output
F2
I2CVDD
I2C power supply
Supply
F3
VDD
power supply
Supply
F4
OUT-
negative optimized audio output
Analog Output
F5
LPF-
Low Pass Filter for negative output
Analog Input
F6
CAL
calibration enable
Digital Input
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
Supply Voltage
6.0V
Storage Temperature
-85°C to +150°C
Power Dissipation (3)
Internally Limited
ESD Rating
(4)
2000V
ESD Rating (5)
200V
Junction Temperature (TJMAX)
150°C
Mounting Temperature
Infrared or Convection (20 sec.)
235°C
Thermal Resistance
θJA (DSBGA)
70°C/W
Soldering Information See AN-1112 (SNVA009) “DSBGA Wafers Level Chip Scale Package.”
(1)
(2)
(3)
(4)
(5)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJC, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in the Absolute Maximum Ratings,
whichever is lower. For the LMV1089, TJMAX = 150°C and the typical θJA for this DSBGA package is 70°C/W and for the LLP package
θJA is 64°C/W Refer to the Thermal Considerations section for more information.
Human body model, applicable std. JESD22-A114C.
Machine model, applicable std. JESD22-A115-A.
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OPERATING RATINGS
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(1)
Supply Voltage
2.7V ≤ VDD ≤ 5.5V
I2CVDD
Supply Voltage (2)
1.7V ≤ I2CVDD ≤ 5.5V
Temperature Range
−40°C to 85°C
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°C
(1)
(2)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
The voltage at I2CVDD must not exceed the voltage on VDD.
ELECTRICAL CHARACTERISTICS 3.3V
(1)
Unless otherwise specified, all limits specified for TJ = 25°C, VDD = 3.3V, VIN = 18mVP-P, f = 1kHz, EN = VDD, pass through
mode (2), Pre Amp gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF, CREF = 10nF
Symbol
(4)
Units
(Limits)
63
dB
65
dB
eN
Input Referred Noise level
A-weighted
VIN
Maximum Input Signal
THD+N < 1%, Pre Amp Gain = 6dB
910
850
mVP-P (min)
Maximum AC Output Voltage
f = 1kHz, Differential Out+, OutTHD+N < 1%
1.2
1.1
VRMS (min)
DC Level at Outputs
Out+, Out-
800
Total Harmonic Distortion + Noise
Differential Out+ and Out-
ZIN
ZOUT
ZLOAD
6
Limits
f = 1kHz, VIN = 18mVP-P, A-Weighted
voice band (300 – 3400Hz)
THD+N
(4)
Typical (3)
f = 1kHz, VIN = 18mVP-P
VOUT
(2)
(3)
LMV1089
Conditions
Signal-to-Noise Ratio
SNR
(1)
Parameter
μVRMS
5
0.1
mV
0.2
% (max)
Input Impedance
142
kΩ
Output Impedance
300
Ω
Load Impedance (Out+, Out-)
RLOAD
CLOAD
AM
Microphone Preamplifier Gain Range
AMR
Microphone Preamplifier Gain
Adjustment Resolution
f = 1kHz
AP
Post Amplifier Gain Range
Pass Through Mode and Summing
Mode
APR
Post Amplifier Gain Resolution
ACR
Gain Compensation Range
10
100
kΩ (min)
pF (max)
1.7
2.3
dB (min)
dB (max)
6 – 36
2
6 – 18
3
f = 300Hz
f = 1kHz
f = 3kHz
AMD
Maximum Gain Matching Difference
After Calibration
XTalk
Crosstalk Attenuation between Mic1 and
Measured at M1_UNP and M2_UNP
Mic2
TCAL
Calibration Duration
FFNSE
Far Field Noise Suppression Electrical
f = 1kHz (See TEST METHODS)
f = 300Hz (See TEST METHODS)
SNRIE
Signal-to-Noise Ratio Improvement
Electrical
f = 1kHz (See TEST METHODS)
f = 300Hz (See TEST METHODS)
dB
dB
2.6
3.4
dB (min)
dB (max)
±3
dB
0.5
0.25
0.5
dB
dB
dB
52
41
dB (min)
790
ms (max)
32
37
20
22
dBV(min)
dBV (min)
24
28
14
15
dBV (min)
dBV (min)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The voltage at I2CVDD must not exceed the voltage on VDD.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
Datasheet min/max specification limits are ensured by test, or statistical analysis.
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ELECTRICAL CHARACTERISTICS 3.3V (1) (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, VDD = 3.3V, VIN = 18mVP-P, f = 1kHz, EN = VDD, pass through
mode (2), Pre Amp gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF, CREF = 10nF
Input Referred, Input AC grounded
PSRR
Power Supply Rejection Ratio
CMRR
Common Mode Rejection Ratio
fRIPPLE = 217Hz (VRIPPLE = 100mVP-P)
96
85
dB (min)
fRIPPLE = 1kHz (VRIPPLE = 100mVP-P)
91
80
dB (min)
f = 1kHz
60
1.85
2.15
V (min)
V (max)
1.2
mA (min)
1.5
mA (max)
VBM
Microphone Bias Supply Voltage
IBIAS = 1mA
2.0
eVBM
Microphone Bias Noise Level
A-Weighted, 10nF cap at VREF pin
10
dB
μVRMS
IBM
Total available Microphone Bias Current
IDDQ
Supply Quiescent Current
VIN = 0V
1.1
IDD
Supply Current
VIN = 25mVP-P both inputs, Noise
cancelling mode
1.1
ISD
Shut Down Current
EN pin = GND
0.7
1
μA (max)
Supply Current during Calibration and
Programming
Calibrating or Programming EEPROM
30
45
mA (max)
25
IDDCP
2
IDDI C
2
I C supply current
2
I C Idle Mode
mA
100
nA (max)
TON
Turn On Time
40
ms (max)
TOFF
Turn Off Time
60
ms (max)
ELECTRICAL CHARACTERISTICS 5.0V (1)
Unless otherwise specified, all limits specified for TJ = 25°C, VDD = 5V, VIN = 18mVP-P, EN = VDD, pass through mode (2), Pre
Amp gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.
Symbol
Parameter
Conditions
63
dB
f = 1kHz, VIN = 18mVP-P, A-Weighted
voice band (300 – 3400Hz)
65
dB
eN
Input Referred Noise level
A-weighted
5
μVRMS
VIN
Maximum Input Signal
f = 1kHz, THD+N < 1%
918
850
mVP-P (min)
Maximum AC Output Voltage
f = 1kHz, THD+N < 1%
between differential output
1.2
1.1
VRMS (min)
0.2
% (max)
DC Output Voltage
THD+N
ZIN
ZOUT
(4)
Units
(Limits)
f = 1kHz, VIN = 18mVP-P
VOUT
(2)
(3)
Limit (4)
Signal-to-Noise Ratio
SNR
(1)
LMV1089
Typical (3)
Total Harmonic Distortion + Noise
800
f = 1kHz VIN = 18mVP-P
0.1
mV
Input Impedance
142
kΩ
Output Impedance
300
Ω
AM
Microphone Preamplifier Gain Range
AMR
Microphone Preamplifier Gain
Adjustment Resolution
f = 1kHz
6 – 36
f = 1kHz
AP
Post Amplifier Gain Range
f = 1kHz Pass Through Mode and
Summing Mode
APR
Post Amplifier Gain Adjustment
Resolution
f = 1kHz
3
ACR
Gain Compensation Range
f = 1kHz
±3
2
dB
1.7
2.3
6 – 18
dB (min)
dB (max)
dB
2.6
3.4
dB (min)
dB (max)
dB
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The voltage at I2CVDD must not exceed the voltage on VDD.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
Datasheet min/max specification limits are ensured by test, or statistical analysis.
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ELECTRICAL CHARACTERISTICS 5.0V(1) (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, VDD = 5V, VIN = 18mVP-P, EN = VDD, pass through mode(2), Pre
Amp gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.
Symbol
Parameter
AMD
Maximum Gain Matching Difference
After Calibration
TCAL
Calibration Duration
LMV1089
Conditions
Typical (3)
f = 300Hz
f = 2kHz
f = 3kHz
Limit (4)
0.5
0.25
0.5
Units
(Limits)
dB
dB
dB
790
ms (max)
FFNSE
Far Field Noise Suppression Electrical
f = 1kHz (See TEST METHODS)
f = 300Hz (See TEST METHODS)
32
37
20
22
dBV
dBV
SNRIE
Signal-to-Noise Ratio Improvement
Electrical
f = 1kHz (See TEST METHODS)
f = 300Hz (See TEST METHODS)
24
28
14
15
dBV
dBV
PSRR
Power Supply Rejection Ratio
fRIPPLE = 217Hz (VRIPPLE = 100mVP-P)
96
85
dB (min)
fRIPPLE = 1kHz (VRIPPLE = 100mVP-P)
91
80
dB (min)
Input Referred, Input AC grounded
CMRR
Common Mode Rejection Ratio
f = 1kHz
62
VBM
Microphone Bias Supply Voltage
IBIAS = 1mA
2.0
V
eVBM
Microphone Bias Noise Level
A-Weighted
10
μVRMS
IBM
Total Available Microphone Bias Current
IDDQ
Supply Quiescent Current
VIN = 0V
1.1
IDDCP
Supply Current during Calibration and
Programming
Calibrating or Programming EEPROM
30
mA (max)
IDD
Supply Current
VIN = 25mVP-P both inputs, Noise
cancelling mode
1.1
mA (max)
ISD
Shut Down Current
EN pin = GND
1.6
μA
TON
Turn On Time
40
ms (max)
TOFF
Turn Off Time
60
ms (max)
DIGITAL INTERFACE CHARACTERISTICS
Symbol
(2)
(3)
(4)
8
Parameter
VIH
Logic High Input Level
VIL
Logic Low Input Level
tsCAL
CAL Setup Time
thCAL
CAL Hold time until calibration is
finished
tsPEC
PE Setup Time
thPEC
PE Hold until calibration is finished
1.2
mA (min)
1.5
mA (max)
(1) (2)
Unless otherwise specified, all limits specified for TJ = 25°C, I2CVDD within the Operating Rating
(1)
dB
(2)
LMV1089
Conditions
Typical
(3)
Limit
(4)
0.75xI2CVDD
EN, TM, SCL, SDA, ADR, CAL, PE
GA0, GA1, GB0, GB1
0.6xVDD
0.25xI2CVDD
EN, TM, SCL, SDA, ADR, CAL, PE
GA0, GA1, GB0
0.4xVDD
2
Units
(Limits)
V (min)
V (max)
ms
790
ms (min)
790
ms (min)
2
ms
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The voltage at I2CVDD must not exceed the voltage on VDD.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
Datasheet min/max specification limits are ensured by test, or statistical analysis.
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TEST METHODS
LMV1089
Mic2+
Osc2
LPF
470 nF
Mic2-
OUT+
AC Voltmeter
470 nF
Mic1+
Osc1
470 nF
Mic1-
OUT-
470 nF
Figure 7. FFNSE, NFSLE, SNRIE Test Circuit
FAR FIELD NOISE SUPPRESSION (FFNSE)
For optimum noise suppression the far field noise should be in a broadside array configuration from the two
microphones (see Figure 34). Which means the far field sound source is equidistance from the two microphones.
This configuration allows the amplitude of the far field signal to be equal at the two microphone inputs, however a
slight phase difference may still exist. To simulate a real world application a slight phase delay was added to the
FFNSE test. The block diagram from Figure 7 is used with the following procedure to measure the FFNSE.
1. A sine wave with equal frequency and amplitude (25mVP-P) is applied to Mic1 and Mic2. Using a signal
generator, the phase of Mic 2 is delayed by 1.1° when compared with Mic1.
2. Measure the output level in dBV (X)
3. Mute the signal from Mic2
4. Measure the output level in dBV (Y)
5. FFNSE = Y - X dB
NEAR FIELD SPEECH LOSS (NFSLE)
For optimum near field speech preservation, the sound source should be in an endfire array configuration from
the two microphones (see Figure 34). In this configuration the speech signal at the microphone closest to the
sound source will have greater amplitude than the microphone further away. Additionally the signal at
microphone further away will experience a phase lag when compared with the closer microphone. To simulate
this, phase delay as well as amplitude shift was added to the NFSLE test. The schematic from Figure 7 is used
with the following procedure to measure the NFSLE.
1. A 25mVP-P and 17.25mVP-P (0.69*25mVP-P) sine wave is applied to Mic1 and Mic2 respectively. Once again,
a signal generator is used to delay the phase of Mic2 by 15.9° when compared with Mic1.
2. Measure the output level in dBV (X)
3. Mute the signal from Mic2
4. Measure the output level in dBV (Y)
5. NFSLE = Y - X dB
SINGLE TO NOISE RATIO IMPROVEMENT ELECTRICAL (SNRIE)
The SNRIE is the ratio of FFNSE to NFSLE and is defined as:
SNRIE = FFNSE - NFSLE
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, TJ = 25°C, VDD = 3.3V, Input Voltage = 18mVP-P, f =1 kHz, pass through mode (The voltage at
I2CVDD must not exceed the voltage on VDD), Pre Amp gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.
THD+N
vs
Frequency, Mic2 = AC GND, Mic1 = 36mVP-P
Noise Canceling Mode
100
100
10
10
THD+N (%)
THD+N (%)
THD+N
vs
Frequency, Mic1 = AC GND, Mic2 = 36mVP-P
Noise Canceling Mode
1
0.1
0.1
0.01
0.01
0.001
10
1
100
1000
10000
0.001
10
100000
100000
THD+N
vs
Frequency, Mic1 = 36mVP-P
Mic1 Pass Through Mode
THD+N
vs
Frequency, Mic2 = 36mVP-P
Mic2 Pass Through Mode
100
10
10
THD+N (%)
THD+N (%)
10000
Figure 9.
1
0.1
1
0.1
0.01
0.01
100
1000
10000
100000
0.001
10
100
1000
10000
100000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11.
THD+N
vs
Input Voltage, Mic1 = AC GND, f = 1kHz
Mic2 Noise Canceling Mode
THD+N
vs
Input Voltage, Mic2 = AC GND, f = 1kHz
Mic1 Noise Canceling Mode
100
100
10
10
THD+N (%)
THD+N (%)
Figure 10.
1
0.1
0.01
0.001
10
1000
Figure 8.
100
0.001
10
100
FREQUENCY (Hz)
FREQUENCY (Hz)
1
0.1
0.01
0.1
0.01
0.001
1
0.01
0.1
INPUT VOLTAGE (VP-P)
INPUT VOLTAGE (VP-P)
Figure 12.
Figure 13.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, TJ = 25°C, VDD = 3.3V, Input Voltage = 18mVP-P, f =1 kHz, pass through mode (The voltage at
I2CVDD must not exceed the voltage on VDD), Pre Amp gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.
THD+N
vs
Input Voltage, f = 1kHz
Mic2 Pass Through Mode
100
100
10
10
THD+N (%)
THD+N (%)
THD+N
vs
Input Voltage, f = 1kHz
Mic1 Pass Through Mode
1
0.1
1
0.1
0.01
0.001
0.01
0.1
0.01
0.001
1
0.01
0.1
1
INPUT VOLTAGE (VP-P)
Figure 14.
Figure 15.
PSRR
vs
Frequency, Pre Amp Gain = 20dB, Post Amp Gain = 6dB
VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND
Mic1 Pass Through Mode
PSRR
vs
Frequency, Pre Amp Gain = 20dB, Post Amp Gain = 6dB
VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND
Mic2 Pass Through Mode
0
0
-20
-20
-40
-40
PSRR (dB)
PSRR (dB)
INPUT VOLTAGE (VP-P)
-60
-60
-80
-80
-100
-100
-120
10
100
1000
10000
100000
-120
10
FREQUENCY (Hz)
100
1000
10000
100000
FREQUENCY (Hz)
Figure 16.
Figure 17.
PSRR
vs
Frequency, Pre Amp Gain = 20dB, Post Amp Gain = 6dB
VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND
Noise Canceling Mode
Far Field Noise Suppression Electrical
vs
Frequency
40
0
35
-20
30
FFNSE (dB)
PSRR (dB)
-40
-60
25
20
15
-80
10
-100
-120
10
5
100
1000
10000
100000
0
100
300
1k
2k
4k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18.
Figure 19.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, TJ = 25°C, VDD = 3.3V, Input Voltage = 18mVP-P, f =1 kHz, pass through mode (The voltage at
I2CVDD must not exceed the voltage on VDD), Pre Amp gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.
Signal-to-Noise Ratio Electrical
vs
Frequency
35
30
SNRIE (dB)
25
20
15
10
5
0
100
300
1k
2k
4k
10k
FREQUENCY (Hz)
Figure 20.
12
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APPLICATION DATA
INTRODUCTION
The LMV1089 is a fully analog single chip solution to reduce the far field noise picked up by microphones in a
communication system. A simplified block diagram is provided in Figure 21.
Post Amp Gain
(6-18 dB)
Preamp Gain
(6-36 dB)
Mic1
OUT+
Analog
Noise
Cancelling
Processor
Optimized
Audio
Ouput
OUT-
Mic2
Figure 21. Simplified Block Diagram of the LMV1089
The output signal of the microphones is first amplified by a pre-amplifier stage with an adjustable gain of 6dB to
36dB. The signal is then processed by the noise cancelling processor. The noise cancelling processor matches
the gain and frequency responses of the microphones and the acoustic characteristics of the enclosure using
coefficients derived during the auto-calibration step and the stored in EEPROM. The resulting noise-suppressed
signal is then amplified by the 6dB to 18dB gain-adjustable post-amplifier. For optimum noise and EMI immunity,
the microphones have a differential connection to the LMV1089 and the output of the LMV1089 is also
differential. The adjustable gain functions can be controlled via I2C and four control pins. Both methods are
described later in the application section.
Power Supply Circuits
A low drop-out (LDO) voltage regulator in the LMV1089 allows the device to be independent of supply voltage
variations.
The Power On Reset (POR) circuitry in the LMV1089 requires the supply voltage to rise from 0V to VDD in less
than 100ms.
The Mic Bias output is provided as a low noise supply source for the electret microphones. The noise voltage on
the Mic Bias microphone supply output pin depends on the noise voltage on the internal the reference node. The
de-coupling capacitor on the VREF pin determines the noise voltage on this internal reference. This capacitor
should be larger than 1nF; having a larger capacitor value will result in a lower noise voltage on the Mic Bias
output.
Most of the logic levels for the digital control interface are relative to I2CVDD voltage. This eases interfacing to the
micro controller of the application containing the LMV1089. The supply voltage on the I2CVDD pin must never
exceed the voltage on the VDD pin.
Only the four pins that determine the default power up gain (as described in SETTING ADJUSTABLE GAIN)
have logic levels relative to VDD.
Shutdown Function
As part of the Powerwise™ family, the LMV1089 consumes only 1.1mA of current. In many applications the part
does not need to be continuously operational. To further reduce the power consumption in the inactive period,
the LMV1089 provides two individual microphone power down functions. When either one of the shutdown
functions is activated the part will go into shutdown mode consuming only a few μA of supply current.
SHUTDOWN VIA HARDWARE PIN
The hardware shutdown function is operated via the EN pin. In normal operation the EN pin must be at a 'high'
level (VDD). Whenever a 'low' level (GND) is applied to the EN pin the part will go into shutdown mode disabling
all internal circuits.
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SHUTDOWN VIA I2C
The LMV1089 offers an additional shutdown function by reprogramming an I2C register (see Table 5). The
LMV1089 will only consume power in a mode where it can perform its normal functions. So at least one of the
microphone amplifier circuits must be enabled ('1'). Writing '0' to the both bit 4 and bit 5 of the I2C 'A' register
(address 0x01h) of the LMV1089 will force the part into shutdown mode, even if the EN pin is 'High', the only part
that remains active in this state is the I2C, which consumes neglectible power when compared to the standby
current.
Adjustable Gain
The LMV1089 has two gain stages where the gain can be adjusted to meet the requirements for the application.
There is a preamplifier and a post amplifier that can be varied independent of each other. In most applications
the gain will be set via the I2C interface, see Table 5.
SETTING ADJUSTABLE GAIN
The LMV1089 provides four pins to set the default gain settings during power up of the device, which is
convenient for applications without a micro controller . The default gain of the preamplifier is controlled by the
GA0 and GA1 pins and can be set by wiring those pins to either VDD or GND. In this way, one of the four
possible values in the 12dB to 36dB range (see Table 1) can be chosen. The default post amplifier gain is set in
the same way by connecting the GB0 and GB1 pins to either VDD or GND to select a gain between 6dB and
15dB (see Table 2). Setting the gain of the preamplifier and post amplifier via the I2C interface (see Table 5) will
override this default gain.
The default gain is only set during power up of the device. Toggling the logic level of the enable pin (EN) will not
change the current gain setting of the part. Any gain setting done via the I2C interface will remain valid during
activation of the function.
Table 1. Default preamplifier gain
(1)
GA1
GA0
Gain
0
0
12dB
0
1
1
0
28dB
1
1
36dB
(1)
20dB
Default value used for performance measurements
Table 2. Default post amplifier gain
(1)
GB1
GB0
0
0
Gain
0
1
9dB
1
0
12dB
1
1
15dB
6dB
(1)
Default value used for performance measurements
Gain Balance and Gain Budget
In systems where input signals have a high dynamic range, critical noise levels or where the dynamic range of
the output voltage is also limited, careful gain balancing is essential for the best performance. Too low of a gain
setting in the preamplifier can result in higher noise levels while too high of a gain setting in the preamplifier will
result in clipping and saturation in the noise cancelling processor and output stages.
The gain ranges and maximum signal levels for the different functional blocks are shown in Figure 22. Two
examples are given as a guideline on how to select proper gain settings.
14
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Pre Amp
Gain
(6-36 dB)
Post Amp
Gain
(6-18 dB)
Gain
(Max. 9 dB)
OUT+
Analog
Noise
Cancelling
Processor
Mic1
or
Mic2
Maximum
AC Input
Voltage
