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LMV116, LMV118
SNOSA87C – OCTOBER 2003 – REVISED OCTOBER 2016
LMV11x Low-Voltage, 45-MHz, Rail-To-Rail Output Operational Amplifiers
With Shutdown Option
1 Features
•
•
•
•
•
•
•
•
•
•
•
1
3 Description
The LMV116 (single) rail-to-rail output voltage
feedback amplifiers offer high-speed (45 MHz), and
low-voltage operation (2.7 V) in addition to micropower shutdown capability (LMV118).
−3-dB BW 45 MHz
Supply Voltage Range 2.7 V to 12 V
Slew Rate 40 V/μs
Supply Current 600 μA
Power Down Supply Current 15 μA
Output Short Circuit Current 32 mA
Linear Output Current ±20 mA
Input Common Mode Voltage −0.3 V to 1.7 V
Output Voltage Swing 20 mV from Rails
Input Voltage Noise 40 nV/√Hz
Input Current Noise 0.75 pA/√Hz
Output voltage range extends to within 20 mV of
either supply rail, allowing wide dynamic range
especially in low voltage applications. Even with low
supply current of 600 μA, output current capability is
kept at a respectable ±20 mA for driving heavier
loads. Important device parameters such as BW, slew
rate, and output current are kept relatively
independent of the operating supply voltage by a
combination of process enhancements and design
architecture.
For portable applications, the LMV118 provides
shutdown capability while keeping the turnoff current
to 15 μA. Both turnon and turnoff characteristics are
well behaved with minimal output fluctuations during
transitions, thus the device can be used in powersaving mode, as well as multiplexing applications.
Miniature packages (5-pin and 6-pin SOT-23) are
further means to ease the adoption of these lowpower, high-speed devices in applications where
board area is at a premium.
2 Applications
•
•
•
•
•
•
High-Speed Clock Buffer/Driver
Active Filters
High-Speed Portable Devices
Multiplexing Applications (LMV118)
Current Sense Amplifier
High-Speed Transducer Amplifier
Device Information(1)
PART NUMBER
LMV116
LMV118
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)
2.90 mm × 1.60 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
2.7V
100k:
15.36MHz
SINE WAVE
R1
+
LMV116/
LMV118
C1
0.1PF
47k:
OUTPUT
-
R2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV116, LMV118
SNOSA87C – OCTOBER 2003 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: 2.7 V ................................
Electrical Characteristics: 5 V ...................................
Electrical Characteristics: ±5 V .................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application: 2.7-V Single Supply 2:1 MUX 15
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Related Documentation.........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2013) to Revision C
Page
•
Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information
tables, Functional Block Diagram, Feature Description, Device Functional Modes, Application and Implementation,
Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and
Orderable Information sections .............................................................................................................................................. 1
•
Changed RθJA from 265°C/W to 182.7°C/W ........................................................................................................................... 4
Changes from Revision A (May 2013) to Revision B
•
2
Page
Changed layout of National Semiconductor data sheet to TI format.................................................................................... 17
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SNOSA87C – OCTOBER 2003 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
SOT-23 Package
5-Pin DBV
Top View
SOT-23 Package
6-Pin DBV
Top View
5
1
OUTPUT
V
+
6
1
OUTPUT
5
V
-
2
V
-
2
+
+
SD
-
-
+
+IN
V
4
3
+IN
-IN
4
3
-IN
Pin Functions
PIN
NAME
I/O
DESCRIPTION
LMV116
LMV118
+IN
3
3
Input
Non-inverting input
–IN
4
4
Input
Inverting input
OUTPUT
1
1
Output
SD
—
5
Input
V+
5
6
Power
Positive (highest) power supply
V–
2
2
Power
Negative (lowest) power supply
Output
Shutdown input. Active high, must be tied to V– with resistor for normal
operation.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Supply voltage (V+ - V−)
−
V −0.8
Voltage at INPUT and OUTPUT pins
Junction temperature (5)
Soldering information
(2)
(3)
(4)
(5)
V
+
V
(4)
150
°C
Infrared or convection (20 seconds)
235
°C
Wave soldering lead temperature (10 seconds)
260
°C
150
°C
Storage temperature, Tstg
(1)
UNIT
12.6
V + 0.8
See (3),
Output short-circuit duration
MAX
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
Output short circuit duration is infinite for VS < 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5
ms.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA) / RθJA . All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Machine model
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V−)
Temperature
(1)
(1)
NOM
MAX
UNIT
2.5
12
V
−40
85
°C
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA)/ RθJA . All numbers apply for packages soldered directly onto a PC board.
6.4 Thermal Information
THERMAL METRIC (1)
LMV116
LMV118
DBV (SOT-23)
DBV (SOT-23)
UNIT
5 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
182.7
182.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
139.9
139.9
°C/W
RθJB
Junction-to-board thermal resistance
41.4
41.4
°C/W
ψJT
Junction-to-top characterization parameter
28.5
28.5
°C/W
ψJB
Junction-to-board characterization parameter
40.9
40.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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SNOSA87C – OCTOBER 2003 – REVISED OCTOBER 2016
6.5 Electrical Characteristics: 2.7 V
Unless otherwise specified, all limits apply for TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = VO = V+ / 2, and RF = 2 kΩ, and
RL = 1 kΩ to V+ / 2.
PARAMETER
TEST CONDITIONS
MIN (1)
0 V ≤ VCM ≤ 1.7 V
VOS
Input offset voltage
0 V ≤ VCM ≤ 1.7 V
–40°C to 85°C
TC VOS
Input offset average drift
See (3)
See
(4)
TYP (2)
MAX (1)
±1
±5
UNIT
mV
±6
±5
−2
μV/C
−0.4
IB
Input bias current
IOS
Input offset current
CMRR
Common mode rejection ratio
VCM stepped from 0 V to 1.55 V
73
88
PSRR
Power supply rejection ratio
V+ = 2.7 V to 3.7 V or V− = 0 V to −1 V
72
85
dB
RIN
Common mode input resistance
3
MΩ
CIN
Common mode input capacitance
2
pF
CMVR
Input common-mode voltage
range
AVOL
Large signal voltage gain
Output swing high
VO
Output swing low
ISC
Output short-circuit current
See (4), –40°C to 85°C
1
CMRR ≥ 50 dB
−0.3
CMRR ≥ 50 dB, –40°C to 85°C
–0.1
VO = 0.35 V to 2.35 V
73
VO = 0.35 V to 2.35 V, –40°C to 85°C
70
RL = 1 kΩ to V+/2
2.55
RL = 10 kΩ to V+/2
RL = 1 kΩ to V+/2
μA
–2.2
500
nA
dB
1.7
V
87
dB
2.66
V
2.68
150
RL = 10 kΩ to V+/2
40
mV
20
Sourcing to V−
VID = 200 mV (5)
25
35
Sinking to V+
VID = −200 mV (5)
25
32
mA
IOUT
Output current
IS
Supply current
SR
Slew rate
BW
−3 dB BW
en
Input-referred voltage noise
in
Input-referred current noise
ton
Turnon time (LMV118)
250
ns
toff
Turnoff time (LMV118)
560
ns
THSD
Shutdown threshold (LMV118)
IS ≤ 50 μA
ISD
SHUTDOWN pin input current
(LMV118)
See (4)
(1)
(2)
(3)
(4)
(5)
(6)
(6)
VOUT = 0.5 V from rails
±20
Normal operation
mA
600
900
Shutdown mode (LMV118)
15
50
AV = +1, VO = 1 VPP
40
V/μs
AV = +1, VOUT = 200 mVPP
45
MHz
f = 100 kHz
40
f = 1 kHz
60
f = 100 kHz
f = 1 kHz
nV/√Hz
0.75
pA/√Hz
1.2
1.95
μA
2.3
−20
V
μA
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Positive current corresponds to current flowing into the device.
Short-circuit test is a momentary test. See Absolute Maximum Ratings, note 4.
Slew rate is the average of the rising and falling slew rates.
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6.6 Electrical Characteristics: 5 V
Unless otherwise specified, all limits apply for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RF = 2 kΩ, and RL = 1 kΩ
to V+/2.
PARAMETER
TEST CONDITIONS
MIN (1)
0 V ≤ VCM ≤ 1.7 V
VOS
Input offset voltage
0 V ≤ VCM ≤ 1.7 V
–40°C to 85°C
TC VOS
Input offset average drift
See (3)
IB
Input bias current
IOS
Input offset current
CMRR
Common mode rejection ratio
TYP (2)
MAX (1)
±1
±5
±6
±5
See (4)
−2
See (4), –40°C to 85°C
−
+
V = 5 V to 6 V or V = 0 V to −1 V
μA
–2.2
77
85
72
mV
μV/C
−0.4
1
VCM stepped from 0 V to 3.8 V
UNIT
500
nA
dB
PSRR
Power supply rejection ratio
95
dB
RIN
Common mode input resistance
3
MΩ
CIN
Common mode input capacitance
2
pF
CMVR
Input common-mode voltage
range
AVOL
Large signal voltage gain
Output swing high
VO
Output swing low
ISC
Output short-circuit current
IOUT
Output current
CMRR ≥ 50 dB
−0.3
CMRR ≥ 50 dB, –40°C to 85°C
–0.1
VO = 1.5 V to 3.5 V
73
VO = 1.5 V to 3.5 V, –40°C to 85°C
70
RL = 1 kΩ to V+/2
4.8
RL = 10 kΩ to V+/2
RL = 1 kΩ to V+/2
4
87
200
+
RL = 10 kΩ to V /2
50
Sourcing to V−
VID = 200 mV (5)
35
45
Sinking to V+
VID = –200 mV (5)
35
43
mA
VOUT = 0.5 V from rails
±20
Normal operation
600
900
Shutdown mode (LMV118)
10
50
AV = +1, VO = 1 VPP
40
V/μs
AV = +1, VOUT = 200 mVPP
45
MHz
f = 100 kHz
40
f = 1 kHz
60
Slew rate
BW
−3 dB BW
en
Input-referred voltage noise
in
Input-referred current noise
ton
Turnon time (LMV118)
210
toff
Turnoff time (LMV118)
500
THSD
Shutdown threshold (LMV118)
IS ≤ 50 μA
SHUTDOWN pin input current
(LMV118)
(4)
6
mV
20
SR
(1)
(2)
(3)
(4)
(5)
(6)
V
4.98
Supply current
ISD
dB
4.95
IS
(6)
V
f = 100 kHz
f = 1 kHz
See
mA
nV/√Hz
0.75
pA/√Hz
1.2
4.25
−20
μA
ns
ns
4.6
V
μA
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
Positive current corresponds to current flowing into the device.
Short-circuit test is a momentary test. See Absolute Maximum Ratings, note 4.
Slew rate is the average of the rising and falling slew rates.
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6.7 Electrical Characteristics: ±5 V
Unless otherwise specified, all limits apply for TJ = 25°C, V+ = 5 V, V− = –5 V, VCM = VO = 0 V, and RF = 2 kΩ, and RL = 1 kΩ
to V+/2.
PARAMETER
TEST CONDITIONS
MIN (1)
0 V ≤ VCM ≤ 1.7 V
VOS
Input offset voltage
0 V ≤ VCM ≤ 1.7 V
–40°C to 85°C
TC VOS
Input offset average drift
See (3)
IB
Input bias current
IOS
Input offset current
CMRR
Common mode rejection ratio
TYP (2)
MAX (1)
±1
±5
mV
±6
±5
See (4)
−2
See (4), –40°C to 85°C
−
V = 5 V to 6 V or V = 0 V to −1 V
μV/C
−0.4
μA
–2.2
3
VCM stepped from 0 V to 3.8 V
+
UNIT
78
104
72
500
nA
dB
PSRR
Power supply rejection ratio
95
dB
RIN
Common mode input resistance
3
MΩ
CIN
Common mode input capacitance
2
pF
CMVR
Input common-mode voltage range
AVOL
Large signal voltage gain
Output swing high
VO
Output swing low
ISC
Output short-circuit current
IOUT
Output current
CMRR ≥ 50 dB
−5.3
CMRR ≥ 50 dB, –40°C to 85°C
–5.1
VO = 1.5 V to 3.5 V
74
VO = 1.5 V to 3.5 V, –40°C to 85°C
71
RL = 1 kΩ to V+/2
4.7
RL = 10 kΩ to V+/2
RL = 1 kΩ to V+/2
4
85
V
4.97
–4.7
+
RL = 10 kΩ to V /2
–4.92
V
–4.98
Sourcing to V−
VID = 200 mV (5)
40
57
Sinking to V+
VID = −200 mV (5)
40
54
mA
VOUT = 0.5 V from rails
±20
Normal operation
600
900
Shutdown mode (LMV118)
15
50
AV = 1, VO = 1 VPP
35
V/μs
AV = 1, VOUT = 200 mVPP
45
MHz
f = 100 kHz
40
f = 1 kHz
60
Supply current
SR
Slew rate
BW
−3 dB BW
en
Input-referred voltage noise
in
Input-referred current noise
ton
Turnon time (LMV118)
200
toff
Turnoff time (LMV118)
700
THSD
Shutdown threshold (LMV118)
IS ≤ 50 μA
4.25
ISD
SHUTDOWN pin input current
(LMV118)
See (4)
−20
(1)
(2)
(3)
(4)
(5)
(6)
dB
4.92
IS
(6)
V
f = 100 kHz
f = 1 kHz
mA
μA
nV/√Hz
0.75
pA/√Hz
1.2
ns
ns
4.6
V
μA
Typical values represent the most likely parametric norm.
Offset voltage average drift determined by dividing the change in VOS. All limits are specified by testing or statistical analysis.
at temperature extremes into the total temperature change.
Positive current corresponds to current flowing into the device.
Short-circuit test is a momentary test. See Absolute Maximum Ratings, note 4.
Slew rate is the average of the rising and falling slew rates.
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6.8 Typical Characteristics
At TJ = 25°C. Unless otherwise specified.
1.4
0.9
85°C
1.2
SUPPLY CURRENT (mA)
0.8
0.7
IS (mA)
25°C
0.6
-40°C
0.5
1
85°C
0.8
25°C
0.6
0.4
-40°C
0.4
0.2
0
0.3
3
1
5
7
9
11
12
-6
-4
-2
VS (V)
Figure 1. Supply Current vs Supply Voltage
2
4
6
Figure 2. Supply Current vs VCM
70
90
60
80
VS = 5V
PHASE
50
100
40
70
85°C
20
10
60
40
20
-40°C
0
PHASE (°)
85°C
30
CMRR (dB)
80
GAIN
GAIN (dB)
0
VCM (V)
60
50
40
0
30
-40°C
-20
VS = ±2.5V
20
RL = 2k
100k
1M
10M
10
1k
100M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3. Gain and Phase vs Frequency
Figure 4. CMRR vs Frequency
1000
110
100
90
+PSRR
en (nV/ Hz)
PSRR (dB)
80
70
60
50
-PSRR
VOLTAGE
100
40
30
20
VS = ±5V
10
100
1k
10k
100k
1M
10M
10
10
Figure 5. PSRR vs Frequency
8
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Input Voltage Noise vs Frequency
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Typical Characteristics (continued)
At TJ = 25°C. Unless otherwise specified.
10.00
AV = +2
GAIN
AV = +1
0
CURRENT
1.00
AV = +10
-4
0
PHASE
50
PHASE (°)
GAIN (dB)
in (pA/ Hz)
-2
100
AV = +5
VS = ±5V
RL = 1k:
0.10
10
100
10k
1k
1M
10M
FREQUENCY (Hz)
100k
100k
FREQUENCY (Hz)
Figure 7. Input Current Noise vs Frequency
GAIN
200M
Figure 8. Closed-Loop Frequency Response for Various
Temperature
85°C
0
25°C
-4
PHASE (°)
GAIN (dB)
-2
0
PHASE
50
AV = +1
100
VS = ±5V
-40°C
VS = ±2.5V
RL = 1K
RL = 1k:
VOUT = 200mVPP
100k
VOUT = 1VPP
100M 200M
10M
1M
40 ns/DIV
0.2 V/DIV
FREQUENCY (Hz)
Figure 10. Large Signal Step Response
Figure 9. Frequency Response For Various (AV)
1.2
1.4
VS = 5V
85°C
25°C
1.3
1.1
1
VOS (mV)
VOS (mV)
85°C
1.2
25°C
-40°C
0.9
1.1
-40°C
1.0
0.9
0.8
0.8
0.7
VS = 2.7V
0.7
0.6
0
0.5
1
1.5
0
2
VCM (V)
1
2
3
4
5
VCM (V)
Figure 11. Offset Voltage vs Common Mode Voltage
(a Typical Unit)
Figure 12. Offset Voltage vs Common Mode Voltage (a
Typical Unit)
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Typical Characteristics (continued)
At TJ = 25°C. Unless otherwise specified.
-0.15
1.4
VS = ±5V
25°C
1.3
-0.17
INPUT BIAS CURRENT (PA)
85°C
1.2
VOS (mV)
1.1
-40°C
1
0.9
0.8
0.7
-0.19
-40°C
-0.21
25°C
-0.23
-0.25
85°C
-0.27
-0.29
0.6
0.5
-0.31
-5
-2
-3.5
-0.5
1
2.5
4
0
2
4
VCM (V)
Figure 13. Offset Voltage vs Common Mode Range
(a Typical Unit)
12
85°C
30
-0.16
-0.18
25
25°C
-0.20
ISINK (mA)
INPUT BIAS CURRENT (PA)
10
35
-0.14
85°C
-0.22
-0.24
-0.26
20
25°C
-40°C
15
10
-40°C
-0.28
5
-0.30
0
-0.32
VS = 2.7V
-5
-0.34
-3
-5
-1
1
3
5
-0.2
0
0.2
0.6
0.8
1
1.2
1.4
Figure 16. Sink Current vs VOUT
Figure 15. Input Bias Current vs VCM
40
45
85°C
85°C
40
35
35
30
30
25°C
ISOURCE (mA)
-40°C
25°C
25
20
15
10
25
-40°C
20
15
10
5
5
0
0.4
VOUT (V)
VCM (V)
ISINK (mA)
8
Figure 14. Input Bias Current vs Supply Voltage
-0.12
0
VS = 5V
-5
VS = 2.7V
-5
-0.5
0
0.5
1
1.5
2
2.5
3
VOUT (V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VOUT (V)
Figure 17. Sink Current vs VOUT
10
6
SUPPLY VOLTAGE (V)
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Figure 18. Souce Current vs VOUT
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Typical Characteristics (continued)
At TJ = 25°C. Unless otherwise specified.
50
85°C
45
ISOURCE (mA)
40
35
25°C
30
-40°C
25
20
15
10
5
0
VS = 5V
-5
0
0.5
1
1.5
2
2.5
3
VOUT (V)
Figure 19. Source Current vs VOUT
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7 Detailed Description
7.1 Overview
The LMV116 and LMV118 are based on TI’s proprietary VIP10 dielectrically isolated bipolar process.
The LMV116 and LMV118 architecture features the following:
• Complementary bipolar devices with exceptionally high ft (approximately 8 GHz) even under low supply
voltage (2.7 V) and low collector bias current.
• Common emitter push-pull output stage capable of 20-mA output current (at 0.5 V from the supply rails) while
consuming only 600 μA of total supply current. This architecture allows output to reach within milli-volts of
either supply rail at light loads.
• Consistent performance from any supply voltage (2.7 V to 10 V) with little variation with supply voltage for the
most important specifications (for example, BW, SR, IOUT, etc.)
7.2 Functional Block Diagram
V+
Power Clamp
Reference
+IN
-IN
Input Clamp
Input Stage
Output Stage
OUTPUT
V-
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7.3 Feature Description
The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifier
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AVOL (+IN – –IN)
where
•
12
AVOL is the open-loop gain of the amplifier, typically around 85 dB.
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7.4 Device Functional Modes
7.4.1 Quasi-Saturated State
When the output swing approaches either supply rail, the output transistor enters a quasi-saturated state. A
subtle effect of this operational region is that there is an increase in supply current in this state (up to 1 mA). The
onset of quasi-saturation region is a function of output loading (current) and varies from 100 mV at no load to
about 1 V when output is delivering 20 mA, as measured from supplies. Both input common mode voltage and
output voltage level affect the supply current (see Typical Characteristics for plot).
7.4.2 Micro-Power Shutdown
The LMV118 can be shut down to save power and reduce its supply current to less than the 50 μA specified by
applying a voltage to the SD pin. The SD pin is active high and needs to be tied to V− for normal operation. This
input is low current (< 20-μA, 4-pF equivalent capacitance) and a resistor to V− (≤ 20 kΩ) results in normal
operation. Shutdown is specified when SD pin is 0.4 V or less from V+ at any operating supply voltage and
temperature.
In the shutdown mode, essentially all internal device biasing is turned off in order to minimize supply current flow,
and the output goes into Hi-Z (high impedance) mode. Complete device turnon and turnoff times vary
considerably relative to the output loading conditions, output voltage, and input impedance, but is generally
limited to less than 1 μs (see Electrical Characteristics: 2.7 V, Electrical Characteristics: 5 V, and Electrical
Characteristics: ±5 V)
During shutdown, the input stage has an equivalent circuit as shown in Figure 20.
INVERTING
INPUT
RS
200-400:
D4
D1
D3
D2
NON-INVERTING
INPUT
Figure 20. Input Stage Shutdown Equivalent Circuit
As can be seen from Figure 20, in shutdown there may be current flow through the internal diodes shown,
caused by input potential, if present. This current may flow through the external feedback resistor and result in an
apparent output signal. In most shutdown applications the presence of this output is inconsequential. However, if
the output is forced by another device such as in a multiplexer, the other device must conduct the current
described in order to maintain the output potential.
To keep the output at or near ground during shutdown when there is no other device to hold the output low, a
switch (transistor) could be used to shunt the output to ground. Figure 21 shows a circuit where a NPN bipolar is
used to keep the output near ground (approximately 80 mV):
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Device Functional Modes (continued)
5V
-
VOUT
LMV118
VIN
+
SD
V
-
SHUTDOWN
INPUT
Q1
RS
10k
Figure 21. Active Pulldown Schematic
Figure 22 shows the output waveform.
VOUT
VS = 5V
AV = +1
VIN = 3.5VPP
SD
2 V/DIV
2.00 µs/DIV
Figure 22. Output Held Low by Active Pulldown Circuit
If bipolar transistor power dissipation is not tolerable, the switch can be done by an N-channel enhancementmode MOSFET.
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV11x rail-to-rail output voltage feedback amplifiers offer high-speed (45 MHz) operation with low input
voltage (2.7 V). Output voltage range extends to within 20 mV of either supply rail, allowing wide dynamic range
especially in low voltage applications. Even with low supply current of 600 μA, output current capability is kept at
a respectable ±20 mA. For portable applications, the LMV118 provides shutdown capability while keeping the
turnoff current to 15 μA. Both turnon and turnoff characteristics are well behaved with minimal output fluctuations
during transitions which enables the use of LMV118 in multiplexing applications.
8.2 Typical Application: 2.7-V Single Supply 2:1 MUX
The schematic shown in Figure 23 functions as a 2:1 MUX operating on a single 2.7-V power supply, by utilizing
the shutdown feature of the LMV118. Select input signal is connected to the shutdown pin of the first LMV118
through 74HC04 inverter. This signal is connected to the shutdown pin of the second LMV118 through another
inverter. With this setup one of the LMV118 operational amplifiers is always in shutdown mode while the other is
in active mode.
1/5
74HC04
1/5
74HC04
SELECT
INPUT
2k
2k
2.7V
-
SHUTDOWN
LMV118
+
INPUT A
RL
2.7V
SHUTDOWN
+
INPUT B
LMV118
-
2k
2k
Figure 23. 2:1 MUX Operating Off a 2.7-V Single Supply
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Typical Application: 2.7-V Single Supply 2:1 MUX (continued)
8.2.1 Design Requirements
For typical operational-amplifier applications, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Supply voltage
2.7 V
Linear output current
±20 mA (typical)
PSRR
85 dB (typical)
8.2.2 Detailed Design Procedure
It is important to carefully select the values of the external resistors. Choosing large valued external resistors
affects the closed-loop behavior of the stage because of the interaction of these resistors with parasitic
capacitances. These capacitors could be inherent to the device or a by-product of the board layout and
component placement. Either way, keeping the resistor values lower diminishes this interaction. On the other
hand, choosing very low-value resistors could load down nodes and contribute to higher overall power
dissipation.
8.2.3 Application Curve
Figure 24 shows the MUX output when selecting between a 1-MHz sine and a 250-kHz triangular waveform.
As can be seen in Figure 24, the output is well behaved, and there are no spikes or glitches due to the switching.
Switching times are approximately around 500 ns based on the time when the output is considered valid.
VOUT
SELECT
1 V/DIV
1 µs/DIV
Figure 24. 2:1 MUX Output
9 Power Supply Recommendations
The LMV11x is specified for operation from 2.7 V to 12 V (±1.35 V to ±6 V) over a –40°C to +85°C temperature
range. For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines it is
suggested that 100-nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
16
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10 Layout
10.1 Layout Guidelines
Generally, a good high-frequency layout keeps power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground cause frequency response peaking and
possible circuit oscillations (see OA-15 Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers
for more information).
TI suggests the following evaluation boards as a guide for high-frequency layout and as an aid in device testing
and characterization:
DEVICE
PACKAGE
EVALUATION BOARD P/N
LMV116
SOT-23-5
CLC730068
LMV118
SOT-23-6
CLC730116
10.2 Layout Example
Supply
voltage
R1
OUTPUT
1
OUTPUT
V+
5
-IN
4
Via to GND plane
C1
INPUT
2
V-
3
+IN
R2
Figure 25. LMV116/LMV118 Layout
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11 Device and Documentation Support
11.1 Related Documentation
For additional information, see the following:
OA-15 Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers
11.2 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMV116
Click here
Click here
Click here
Click here
Click here
LMV118
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMV116MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
AC1A
LMV116MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
AC1A
LMV118MF/NOPB
ACTIVE
SOT-23
DBV
6
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
AD1A
LMV118MFX/NOPB
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
AD1A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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