LMV321AUQDBVRQ1

LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 LMV321A-Q1、LMV358A-Q1、LMV324A-Q1 汽车类、低电压、轨至轨输出运算放 大器 1 特性 3 说明 • 符合面向汽车应用的 AEC-Q100 标准 – 温度等级 1：–40°C 至 +125°C，TA – 器件 HBM ESD 分类等级 2 – 器件 CDM ESD 分类等级 C6 • 低输入失调电压：±1mV • 轨至轨输出 • 单位带宽增益积：1MHz • 低宽带噪声：30nV/√Hz • 低输入偏置电流：10pA • 低静态电流：70µA/通道 • 单位增益稳定 • 内置 RFI 和 EMI 滤波器 • 可在电源电压低至 2.5V 的情况下运行 • 由于具有电阻式开环输出阻抗，因此可在更高的容 性负载下更轻松地实现稳定 • 工作温度范围：–40°C 至 125°C LMV3xxA-Q1 系列包括单通道 (LMV321A-Q1)、双通 道 (LMV358A-Q1) 和 四 通 道 (LMV324A-Q1) 低 压 （2.5V 至 5.5V）汽车类运算放大器，具有轨至轨输出 摆幅功能。这些运算放大器为空间受限、需要低压运行 和高容性负载驱动的应用（例如信息娱乐系统和照明） 提供了一种具有成本效益的方法。LMV3xxA-Q1 系列 的容性负载驱动具有 500pF 的电容，而电阻式开环输 出阻抗使其易于在更高的容性负载下保持稳定。这些运 算放大器专为低工作电压（2.5V 至 5.5V）而设计，性 能规格类似于 LMV3xx-Q1 器件。 LMV3xxA-Q1 系列的稳健设计可简化电路设计。这些 运算放大器具有单位增益稳定性，集成了 RFI 和 EMI 抑制滤波器，并且在过驱情况下不会出现相位反转。 LMV3xxA-Q1 可 采 用 SOIC 、 MSOP 、 SOT-23 和 TSSOP 等业界通用的封装。 封装信息(1) 2 应用 • • • • • • • • • 器件型号 针对 AEC-Q100 1 级应用进行了优化 信息娱乐系统与仪表组 被动安全 车身电子装置和照明 混合动力汽车/电动汽车逆变器和电机控制 车载充电器 (OBC) 和无线充电器 动力总成电流传感器 高级驾驶辅助系统 (ADAS) 单电源、低侧、单向电流感应电路 封装 LMV321A-Q1 LMV358A-Q1 1.60mm × 2.90mm DCK（SC70，5） 1.25mm × 2.00mm D（SOIC，8） 3.91mm × 4.90mm DGK（VSSOP，8） 3.00mm × 3.00mm D（SOIC，14） DYY（SOT-23， 14） RG 8.65mm × 3.91mm PW（TSSOP，14） 4.40mm × 5.00mm LMV324A-Q1 (1) 封装尺寸（标称值） DBV（SOT-23，5) 4.20mm × 1.90mm 如需了解所有可用封装，请参阅数据表末尾的可订购产品附 录。 RF R1 VOUT VIN C1 f-3 dB = ( RF VOUT = 1+ RG VIN (( 1 1 + sR1C1 1 2pR1C1 ( 单极低通滤波器 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 Table of Contents 1 特性................................................................................... 1 2 应用................................................................................... 1 3 说明................................................................................... 1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information: LMV321A-Q1............................ 6 6.5 Thermal Information: LMV358A-Q1............................ 6 6.6 Thermal Information: LMV324A-Q1............................ 6 6.7 Electrical Characteristics.............................................7 6.8 Typical Characteristics................................................ 8 7 Detailed Description......................................................14 7.1 Overview................................................................... 14 7.2 Functional Block Diagram......................................... 14 7.3 Feature Description...................................................15 7.4 Device Functional Modes..........................................15 8 Application and Implementation.................................. 16 8.1 Application Information............................................. 16 8.2 Typical Application.................................................... 16 9 Power Supply Recommendations................................21 9.1 Input and ESD Protection......................................... 21 10 Layout...........................................................................22 10.1 Layout Guidelines................................................... 22 10.2 Layout Example...................................................... 22 11 Device and Documentation Support..........................23 11.1 Documentation Support.......................................... 23 11.2 Receiving Notification of Documentation Updates.. 23 11.3 支持资源..................................................................23 11.4 Trademarks............................................................. 23 11.5 静电放电警告...........................................................23 11.6 术语表..................................................................... 23 12 Mechanical, Packaging, and Orderable Information.................................................................... 23 4 Revision History 注：以前版本的页码可能与当前版本的页码不同 Changes from Revision C (January 2023) to Revision D (April 2023) Page • 将 DBV 封装状态从预发布 更改为正在供货 ...................................................................................................... 1 Changes from Revision B (October 2021) to Revision C (January 2023) Page • 删除了器件信息 表中 SC70 (5) 封装的预发布说明.............................................................................................1 • Changed the formatting of the Pin Configuration and Functions section............................................................3 • Changed values in Thermal Information: LMV321A-Q1 table............................................................................ 6 Changes from Revision A (April 2021) to Revision B (October 2021) Page 在数据表添加了 LMV321A-Q1 GPN...................................................................................................................1 在器件信息 表中添加了 SOT-23 (5) 和 SC70 (5) 封装....................................................................................... 1 删除了器件信息 表中 SOT-23 (14) 和 TSSOP (14) 封装的预发布说明.............................................................. 1 Added LMV321A-Q1 SOT-23 (5), SC70 (5), and LMV321AU-Q1 SOT-23 (5) Packages, to Pin Configuration and Functions section.........................................................................................................................................3 • Added Thermal Information: LMV321A-Q1 table................................................................................................6 • • • • Changes from Revision * (June 2020) to Revision A (April 2021) • • • • • • • 2 Page 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1 删除了器件信息 表中 VSSOP (8) 封装的预览说明............................................................................................. 1 删除了器件信息 表中的 SOT-23 (8)、TSSOP (8)、SOT-23 (5) 和 SC70 (5) 封装.............................................1 Deleted TSSOP (8) Package, from Pin Configuration and Functions section.................................................... 3 Added note (4) to differential input voltage in Absolute Maximum Ratings table................................................5 Added thermal information for DGK package..................................................................................................... 6 Added thermal information for DYY package..................................................................................................... 6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 5 Pin Configuration and Functions OUT 1 V- 2 +IN 3 5 4 V+ -IN 图 5-1. LMV321A-Q1 DBV Package, 5-Pin SOT-23 (Top View) +IN 1 V- 2 -IN 3 5 V+ 4 OUT 图 5-2. LMV321A-Q1 DCK, LMV321AU-Q1 DBV Package, 5-Pin SC70, SOT-23 (Top View) 表 5-1. Pin Functions: LMV321A-Q1 PIN NAME TYPE DBV DCK, DBV (U) –IN 4 3 +IN 3 OUT 1 V– V+ (1) DESCRIPTION (1) I Inverting input 1 I Non-inverting input 4 O Output 2 2 — Negative (lowest) supply or ground (for single-supply operation) 5 5 — Positive (highest) supply I = input, O = output OUT A 1 8 V+ -IN A 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B 图 5-3. LMV358A-Q1 D and DGK Packages, 8-Pin SOIC and VSSOP (Top View) 表 5-2. Pin Functions: LMV358A-Q1 PIN TYPE(1) DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Non-inverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Non-inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V– 4 — Negative (lowest) supply or ground (for single-supply operation) V+ 8 — Positive (highest) supply (1) I = input, O = output Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 14 OUT D 13 -IN D 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C OUT A 1 -IN A 2 +IN A A B D C 图 5-4. LMV324A-Q1 D, PW, and DYY Packages, 14-Pin SOIC, TSSOP, and SOT-23 (Top View) 表 5-3. Pin Functions: LMV324A-Q1 PIN DESCRIPTION NO. –IN A 2 I Inverting input, channel A +IN A 3 I Non-inverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Non-inverting input, channel B –IN C 9 I Inverting input, channel C +IN C 10 I Non-inverting input, channel C –IN D 13 I Inverting input, channel D +IN D 12 I Non-inverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V– 11 — Negative (lowest) supply or ground (for single-supply operation) V+ 4 — Positive (highest) supply (1) 4 TYPE(1) NAME I = input, O = output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6 Specifications 6.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted)(1) Supply voltage, ([V+] – [V–]) Voltage(2) Signal input pins Common-mode MIN MAX UNIT 0 6 V (V–) – 0.5 (V+) + 0.5 V Differential(4) Current(2) (V+) – (V–) + 0.2 V 10 mA –10 Output short-circuit(3) Continuous Operating, TA –55 Operating junction temperature, TJ Storage temperature, Tstg (1) (2) (3) (4) –65 150 °C 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. Short-circuit to ground, one amplifier per package. Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage and quiescent current above the maximum specifications of these parameters. The magnitude of this effect increases as the ambient operating temperature rises. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1) ±2000 Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C5 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 Specification 6.3 Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN VS Supply voltage TA Specified temperature Copyright © 2023 Texas Instruments Incorporated MAX UNIT 2.5 5.5 V –40 125 °C Submit Document Feedback 5 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6.4 Thermal Information: LMV321A-Q1 LMV321A-Q1 THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) 5 PINS 5 PINS UNIT RθJA Junction-to-ambient thermal resistance 232.5 246.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 131.0 157.5 °C/W RθJB Junction-to-board thermal resistance 99.6 95.4 °C/W ψJT Junction-to-top characterization parameter 66.5 68.8 °C/W ψJB Junction-to-board characterization parameter 99.1 95.0 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. 6.5 Thermal Information: LMV358A-Q1 LMV358A-Q1 THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 151.9 196.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 92.0 86.2 °C/W RθJB Junction-to-board thermal resistance 95.4 118.3 °C/W ψJT Junction-to-top characterization parameter 40.2 23.2 °C/W ψJB Junction-to-board characterization parameter 94.7 116.7 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. 6.6 Thermal Information: LMV324A-Q1 LMV324A-Q1 THERMAL METRIC(1) D (SOIC) PW (TSSOP) DYY (SOT-23) 14 PINS 14 PINS 14 PINS 115.1 135.3 154.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 71.2 63.5 86.8 °C/W RθJB Junction-to-board thermal resistance 71.1 78.4 67.9 °C/W ψJT Junction-to-top characterization parameter 29.6 13.6 10.1 °C/W 77.9 67.5 °C/W RθJA ψJB 6 Junction-to-ambient thermal resistance Junction-to-board characterization parameter Submit Document Feedback 70.7 UNIT Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6.7 Electrical Characteristics For VS = (V+) – (V–) = 2.5 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX ±1 ±4 UNIT OFFSET VOLTAGE Vs = 5 V VOS Input offset voltage dVOS/dT VOS vs temperature TA = –40°C to 125°C PSRR Power-supply rejection ratio VS = 2.5 to 5.5 V, VCM = (V–) ±5 Vs = 5 V, TA = –40°C to 125°C 78 mV ±1 µV/°C 100 dB INPUT VOLTAGE RANGE VCM CMRR Common-mode voltage range Common-mode rejection ratio No phase reversal, rail-to-rail input (V–) – 0.1 (V+) – 1 VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V TA = –40°C to 125°C 86 VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V TA = –40°C to 125°C 95 V dB VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V TA = –40°C to 125°C 63 VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V TA = –40°C to 125°C 77 68 INPUT BIAS CURRENT IB Input bias current IOS Input offset current Vs = 5 V ±10 pA ±3 pA ƒ = 0.1 Hz to 10 Hz, Vs = 5 V 5.1 µVPP ƒ = 1 kHz, Vs = 5 V 33 ƒ = 10 kHz, Vs = 5 V 30 ƒ = 1 kHz, Vs = 5 V 25 fA/√ Hz 1.5 pF 5 pF NOISE En Input voltage noise (peak-to-peak) en Input voltage noise density in Input current noise density nV/√ Hz INPUT CAPACITANCE CID Differential CIC Common-mode OPEN-LOOP GAIN 100 VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10 kΩ AOL Open-loop voltage gain 115 98 VS = 2.5 V, (V–) + 0.04 V < VO < (V+) – 0.04 V, RL = 10 kΩ VS = 2.5 V, (V–) + 0.1 V < VO < (V+) – 0.1 V, RL = 2 kΩ 112 VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ 128 dB FREQUENCY RESPONSE GBW Gain-bandwidth product Vs = 5 V φm Phase margin VS = 5.5 V, G = 1 76 1 ° SR Slew rate Vs = 5 V 1.7 V/µs tS Settling time tOR Overload recovery time VS = 5 V, VIN × gain > VS THD+N Total harmonic distortion + noise VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f = 1 kHz, 80-kHz measurement BW VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 20 50 VS = 5.5 V, RL = 2 kΩ 40 75 ISC Short-circuit current Vs = 5.5 V ZO Open-loop output impedance Vs = 5 V, f = 1 MHz To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF 3 To 0.01%, VS = 5 V, 2-V step , G = +1, CL = 100 pF 4 MHz µs 0.9 µs 0.005% OUTPUT mV ±40 mA 1200 Ω POWER SUPPLY VS IQ Specified voltage range Quiescent current per amplifier Power-on time 2.5 (±1.25) IO = 0 mA, VS = 5.5 V 5.5 (±2.75) 70 150 IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C VS = 0 V to 5 V, to 90% IQ level Copyright © 2023 Texas Instruments Incorporated 125 50 V µA µs Submit Document Feedback 7 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6.8 Typical Characteristics at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 6 3.5 IB I B+ IOS 4 IB+ IOS 2 IB and IOS (pA) 2 IB and IOS (pA) IB 3 2.5 0 -2 -4 1.5 1 0.5 0 -0.5 -1 -6 -1.5 -8 -10 -40 -2 -2.5 -20 0 20 40 60 80 Temperature (qC) 100 120 -3 140 -2 -1 0 1 Common-Mode Voltage (V) D006 2 3 D007 图 6-2. IB and IOS vs Common-Mode Voltage 图 6-1. IB and IOS vs Temperature 160 140 100 120 80 100 60 80 40 60 20 40 80 60 40 0 20 0 -40 VS = 5.5 V VS = 2.5 V -20 0 20 40 60 80 Temperature (qC) 100 120 -20 1k 20 Gain Phase 0 10k 140 100k Frequency (Hz) 1M D009 CL = 10 pF D008 图 6-3. Open-Loop Gain vs Temperature 图 6-4. Open-Loop Gain and Phase vs Frequency 80 160 Gain = 1 Gain = 1 Gain = 10 Gain = 100 Gain = 1000 70 140 60 120 50 100 40 Gain (dB) Open-Loop Voltage Gain (dB) Phase (q) 100 Gain (dB) Gain (dB) 120 80 60 30 20 10 40 0 20 0 -3 -10 -2 -1 0 1 Output Voltage (V) 2 3 D010 -20 100 1k 10k 100k Frequency (Hz) 1M D011 CL = 10 pF 图 6-5. Open-Loop Gain vs Output Voltage 图 6-6. Closed-Loop Gain vs Frequency 8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6.8 Typical Characteristics (continued) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 120 3 Power Supply Rejection Ratio (dB) 2.5 2 Output Voltage (V) 1.5 125°C 85°C 1 25°C -40°C 0.5 0 -0.5 -1 85°C -1.5 25°C -40°C 125°C -2 -2.5 0 5 10 15 20 25 30 35 Output Current (mA) 40 45 80 60 40 20 0 100 -3 50 10k Frequency (Hz) 100k 1M D013 图 6-8. PSRR vs Frequency 120 120 Common-Mode Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 1k D012 图 6-7. Output Voltage vs Output Current (Claw) 100 80 60 40 20 0 -40 PSRR+ PSRR 100 -20 0 20 40 60 80 Temperature (qC) 100 120 100 80 60 40 20 0 100 140 D014 VS = 1.8 V to 5.5 V 1k 10k Frequency (Hz) 100k 1M D015 图 6-10. CMRR vs Frequency Amplitude (1 PV/div) 图 6-9. DC PSRR vs Temperature 2.5 V Time (1 s/div) D017 图 6-12. 0.1 Hz to 10 Hz Integrated Voltage Noise VCM = (V–) – 0.1 V to (V+) – 1.4 V 图 6-11. DC CMRR vs Temperature Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6.8 Typical Characteristics (continued) -50 120 100 -60 80 THD + N (dB) Input Voltage Noise Spectral Density (nV/—Hz) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 60 40 -70 -80 -90 20 RL = 2K RL = 10K 0 10 100 1k Frequency (Hz) 10k -100 100 100k 1k Frequency (Hz) D018 图 6-13. Input Voltage Noise Spectral Density 10k D019 VS = 5.5 V, VCM = 2.5 V, G = 1, BW = 80 kHz, VOUT = 0.5 VRMS 图 6-14. THD + N vs Frequency 70 0 G = +1, RL = 2 k: G = +1, RL = 10 k: G = 1, RL = 2 k: G = 1, RL = 10 k: 60 Quiescent Current (PA) THD + N (dB) -20 -40 -60 50 40 30 20 -80 10 -100 0.001 0.01 0.1 Amplitude (V RMS) 1 0 1.5 2 2 2.5 D020 VS = 5.5 V, VCM = 2.5 V, f = 1 kHz, G = 1, BW = 80 kHz 3 3.5 4 Voltage Supply (V) 4.5 5 5.5 D021 图 6-16. Quiescent Current vs Supply Voltage 图 6-15. THD + N vs Amplitude 70 Open-Loop Output Impedance (:) 2000 Quiescent Current (PA) 60 50 40 30 20 10 0 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 图 6-17. Quiescent Current vs Temperature 10 Submit Document Feedback 140 D022 1800 1600 1400 1200 1000 800 600 400 200 0 1k 10k 100k Frequency (Hz) 1M 10M D023 图 6-18. Open-Loop Output Impedance vs Frequency Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6.8 Typical Characteristics (continued) 50 50 45 45 40 40 35 35 Overshoot (%) Overshoot (%) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 30 25 20 30 25 20 15 15 10 10 Overshoot (+) Overshoot (–) 5 Overshoot (+) Overshoot (–) 5 0 0 0 200 400 600 Capacitance Load (pF) 800 1000 0 200 D024 G = 1, VIN = 100 mVpp 400 600 Capacitance Load (pF) 800 1000 D025 G = –1, VIN = 100 mVpp 图 6-19. Small Signal Overshoot vs Capacitive Load 图 6-20. Small Signal Overshoot vs Capacitive Load 90 VOUT VIN 80 Amplitude (1 V/div) Phase Margin (q) 70 60 50 40 30 20 10 0 0 200 400 600 Capacitance Load (pF) 800 Time (100 Ps/div) 1000 D027 D026 G = 1, VIN = 6.5 VPP 图 6-21. Phase Margin vs Capacitive Load 图 6-22. No Phase Reversal VOUT VIN Amplitude (1 V/div) Voltage (20 mV/div) VOUT VIN Time (20 Ps/div) Time (10 Ps/div) D028 G = –10, VIN = 600 mVPP 图 6-23. Overload Recovery D029 G = 1, VIN = 100 mVPP, CL = 10 pF 图 6-24. Small-Signal Step Response Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6.8 Typical Characteristics (continued) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Voltage (1 V/div) Output Voltage (1 mV/div) VOUT VIN Time (10 Ps/div) Time (1 μs/div) D030 D031 G = 1, VIN = 4 VPP, CL = 10 pF G = 1, CL = 100 pF, 2-V step 图 6-25. Large-Signal Step Response 图 6-26. Large-Signal Settling Time (Negative) 80 Short Circuit Current (mA) Output Voltage (1 mV/div) 60 40 20 0 -20 -40 -60 -80 -40 Time (1 Ps/div) D032 G = 1, CL = 100 pF, 2-V step Sinking Sourcing -20 0 20 40 60 Temperature (qC) 80 100 120 D033 图 6-28. Short-Circuit Current vs Temperature 图 6-27. Large-Signal Settling Time (Positive) 6 140 120 5 100 4 EMIRR (dB) Maximum Output Voltage (V) VS = 5.5 V 3 60 2 40 1 20 0 1 10 100 1k 10k 100k Frequency (Hz) 1M 10M 100M 图 6-29. Maximum Output Voltage vs Frequency 12 80 Submit Document Feedback D034 0 10M 100M 1G Frequency (Hz) 10G D035 图 6-30. Electromagnetic Interference Rejection Ratio Referred to Non-inverting Input (EMIRR+) vs Frequency Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 6.8 Typical Characteristics (continued) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 0 Channel Separation (dB) -20 -40 -60 -80 -100 -120 -140 1k 10k 100k Frequency (Hz) 1M 10M D036 图 6-31. Channel Separation Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 7 Detailed Description 7.1 Overview The LMV3xxA-Q1 is a family of low-power, rail-to-rail output op amps. These devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input commonmode voltage range includes the negative rail and allows the LMV3xxA-Q1 family to be used in many singlesupply applications. Rail-to-rail output swing significantly increases dynamic range, especially in low-supply applications, and makes the family of devices an excellent choice for driving sampling analog-to-digital converters (ADCs). 7.2 Functional Block Diagram V+ Reference Current VIN+ VINVBIAS1 Class AB Control Circuitry VO VBIAS2 V(Ground) 14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 7.3 Feature Description 7.3.1 Operating Voltage The LMV3xxA-Q1 family of op amps are for operation from 2.5 V to 5.5 V. In addition, many specifications such as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics section. 7.3.2 Input Common Mode Range The input common-mode voltage range of the LMV3xxA-Q1 family extends 100 mV beyond the negative supply rail and within 1 V below the positive rail for the full supply voltage range of 2.5 V to 5.5 V. This performance is achieved with a P-channel differential pair, as shown in the Functional Block Diagram. Additionally, a complementary N-channel differential pair has been included in parallel to eliminate issues with phase reversal that are common with previous generations of op amps. However, the N-channel pair is not optimized for operation. TI recommends limiting any voltages applied at the inputs to less than VCC – 1 V to make sure that the op amp conforms to the specifications detailed in the Electrical Characteristics table. 7.3.3 Rail-to-Rail Output Designed as a low-power, low-voltage operational amplifier, the LMV3xxA-Q1 family delivers a robust output drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails. 7.3.4 Overload Recovery Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the LMV3xxA-Q1 family is approximately 850 ns. 7.4 Device Functional Modes The LMV3xxA-Q1 family has a single functional mode. The devices are powered on as long as the power-supply voltage is between 2.5 V (±1.25 V) and 5.5 V (±2.75 V). Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 8 Application and Implementation 备注 以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定 器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 8.1 Application Information The LMV3xxA-Q1 family of low-power, rail-to-rail output operational amplifiers is specifically designed for portable applications. The devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are designed for for a wide range of general-purpose applications. The class AB output stage is capable of driving less than or equal to 10‑kΩ loads connected to any point between V+ and V–. The input common-mode voltage range includes the negative rail, and allows the LMV3xxA-Q1 devices to be used in many single-supply applications. 8.2 Typical Application 8.2.1 LMV3xxA-Q1 Low-Side, Current Sensing Application 图 8-1 shows the LMV3xxA-Q1 configured in a low-side current sensing application. VBUS ILOAD ZLOAD 5V + LMV358A-Q1 VSHUNT  VOUT  + RSHUNT 0.1
RF 57.6 k RG 1.2 k 图 8-1. LMV3xxA-Q1 in a Low-Side, Current-Sensing Application 16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 8.2.1.1 Design Requirements The design requirements for this design are: • Load current: 0 A to 1 A • Output voltage: 4.9 V • Maximum shunt voltage: 100 mV 8.2.1.2 Detailed Design Procedure The transfer function of the circuit in 图 8-1 is given in 方程式 1. VOUT  =  ILOAD  ×  RSHUNT  ×  Gain (1) The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is shown using 方程式 2. V RSHUNT  =   ISHUNT_MAX   =   100 mV 1 A   =  100 mΩ (2) LOAD_MAX Using 方程式 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the LMV3xxA-Q1 to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the LMV3xxA-Q1 to produce the necessary output voltage is calculated using 方程式 3. Gain =   VOUT_MAX  −  VOUT_MIN VIN_MAX −  VIN_MIN (3) Using 方程式 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. 方程式 4 sizes the resistors RF and RG, to set the gain of the LMV3xxA-Q1 to 49 V/V. Gain = 1  +   RF  RG (4) Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. 图 8-2 shows the measured transfer function of the circuit shown in 图 8-1. Notice that the gain is only a function of the feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors values are determined by the impedance levels that the designer wants to establish. The impedance level determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no best impedance selection that works for every system, choose an impedance that is an excellent choice for the system parameters. 8.2.1.3 Application Curve 5 Output (V) 4 3 2 1 0 0 0.2 0.4 0.6 ILOAD (A) 0.8 1 C219 图 8-2. Low-Side, Current-Sense Transfer Function Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 8.2.2 Single-Supply Photodiode Amplifier Photodiodes are used in many applications to convert light signals to electrical signals. The current through the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in 图 8-3 is an example of a single-supply photodiode amplifier circuit using the LMV358A-Q1. +3.3 V R1 11.5 k CF 10 pF VREF R2 357 RF 309 k
+3.3 V – VOUT LMV358A-Q1 VREF IIN 0-10 µA CPD 47 pF + RL 10 k 图 8-3. Single-Supply Photodiode Amplifier Circuit 18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 8.2.2.1 Design Requirements The design requirements for this design are: • • • • Supply voltage: 3.3 V Input: 0 µA to 10 µA Output: 0.1 V to 3.2 V Bandwidth: 50 kHz 8.2.2.2 Detailed Design Procedure The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF) is defined in 方程式 5. Where: VOUT = IIN + RF + VREF (5) R   ×  R VREF = V+ ×   R1  +  R2 1 2 (6) Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio calculated in 方程式 7. VREF 0.1 V V+ =   3.3 V   =  0.0303 (7) The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω. The required feedback resistance can be calculated based on the input current and desired output voltage. V   −  VREF −  0.1 V  RF =   OUTI   =   3.2 V    =  310  kV 10 μA A   ≈  309 kΩ IN (8) Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3dB) using 方 程式 9.  CF =   2  ×  π  ×  R1   ×  f F −3 dB 1   =   2  ×  π  ×  309 kΩ  ×  50 kHz   =  10.3 pF ≈ 10 pF (9) The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the capacitance on the INx – pin of the LMV358A-Q1 which is equal to the sum of the photodiode shunt capacitance, (CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as 方程式 10 shows.  CIN =  CPD  +  CCM  +  CD  =  47 pF  +  5 pf  +  1 pF  =  53 pF  (10) The minimum op amp bandwidth is calculated in 方程式 11. C   +  C F  F = BGW  ≥   2  ×  π IN ×  RF  ×  CF2   ≥  324 kHz  (11) The 1-MHz bandwidth of the LMV3xxA-Q1 meets the minimum bandwidth requirement and remains stable in this application configuration. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 8.2.2.3 Application Curves The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in 图 8-4. The measured performance of the photodiode amplifier circuit is shown in 图 8-5. 3 120 2.5 Output Voltage (V) Gain (dB) 100 80 2 1.5 1 60 0.5 40 10 0 100 1k 10k Frequency (Hz) 100k 1M D001 图 8-4. Photodiode Amplifier Circuit AC Gain Results 20 Submit Document Feedback 0 2E-6 4E-6 6E-6 Input Current (A) 8E-6 1E-5 D002 图 8-5. Photodiode Amplifier Circuit DC Results Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 9 Power Supply Recommendations The LMV3xxA-Q1 family is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications apply from –40°C to 125°C. The Typical Characteristics section presents parameters that may exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages larger than 6 V may permanently damage the device; see the Absolute Maximum Ratings table. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout Guidelines section. 9.1 Input and ESD Protection The LMV3xxA-Q1 family incorporates internal ESD protection circuits on all pins. For input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA. 图 9-1 shows how a series input resistor can be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in noisesensitive applications. V+ IOVERLOAD 10-mA maximum Device VOUT VIN 5 kW 图 9-1. Input Current Protection Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: • Noise can propagate into analog circuitry through the power connections of the board and propagate to the power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a lowimpedance path to ground. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as opposed to running the traces in parallel with the noisy trace. • Place the external components as close to the device as possible, as shown in 图 10-2. Keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce leakage currents from nearby traces that are at different potentials. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. 10.2 Layout Example + VIN 1 + VIN 2 VOUT 1 RG VOUT 2 RG RF RF 图 10-1. Schematic Representation for Figure 10-2 Place components close to device and to each other to reduce parasitic errors . OUT 1 VS+ OUT1 Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . GND V+ RF OUT 2 GND IN1 ± OUT2 IN1 + IN2 ± RF RG VIN 1 GND RG V± Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . GND VS± IN2 + VIN 2 Keep input traces short and run the input traces as far away from the supply lines as possible . Ground (GND) plane on another layer 图 10-2. Layout Example 22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 LMV321A-Q1, LMV324A-Q1, LMV358A-Q1 www.ti.com.cn ZHCSKP5D – JUNE 2020 – REVISED APRIL 2023 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: • Texas Instruments, EMI Rejection Ratio of Operational Amplifiers 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 支持资源 TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解 答或提出自己的问题可获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。 11.4 Trademarks TI E2E™ is a trademark of Texas Instruments. 所有商标均为其各自所有者的财产。 11.5 静电放电警告 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理 和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参 数更改都可能会导致器件与其发布的规格不相符。 11.6 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMV321A-Q1 LMV324A-Q1 LMV358A-Q1 English Data Sheet: SLOSE67 PACKAGE OPTION ADDENDUM www.ti.com 17-Jun-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LMV321AQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2S3F Samples LMV321AQDCKRQ1 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1N1 Samples LMV321AUQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2T7H Samples LMV324AQDRQ1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM324Q Samples LMV324AQDYYRQ1 ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM324Q Samples LMV324AQPWRQ1 ACTIVE TSSOP PW 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM324A Samples LMV358AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 27FT Samples LMV358AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L358AQ Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of