LMV321A, LMV358A, LMV324A
SBOS923H – DECEMBER 2017 – REVISED APRIL 2023
LMV3xxA Low-Voltage Rail-to-Rail Output Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The LMV3xxA family includes single - (LMV321A),
dual - (LMV358A) , and quad-channel (LMV324A)
low-voltage (2.5 V to 5.5 V) operational amplifiers (op
amps) with rail-to-rail output swing capabilities. These
op amps provide a cost-effective solution for spaceconstrained applications such as large appliances,
smoke detectors, and personal electronics where lowvoltage operation and high capacitive-load drive are
required. The capacitive-load drive of the LMV3xxA
family is 500 pF, and the resistive open-loop output
impedance makes stabilization easier with much
higher capacitive loads. These op amps are designed
specifically for low-voltage operation (2.5 V to 5.5 V)
with performance specifications similar to the LMV3xx
devices.
•
Low input offset voltage: ±1 mV
Rail-to-rail output
Unity-gain bandwidth: 1 MHz
Low broadband noise: 30 nV/√ Hz
Low input bias current: 10 pA
Low quiescent current: 70 µA/Ch
Unity-gain stable
Internal RFI and EMI filter
Operational at supply voltages as low as 2.5 V
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
Extended temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
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•
•
•
•
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Smoke detectors
Motion detectors
Wearable devices
Large and small appliances
EPOS
Barcode scanners
Sensor signal conditioning
Power modules
Personal electronics
Active filters
HVAC: heating, ventilating, and air conditioning
Motor control: AC induction
Low-side current sensing
The robust design of the LMV3xxA family simplifies
circuit design. The op amps feature unity-gain
stability, an integrated RFI and EMI rejection filter, and
no-phase reversal in overdrive conditions.
The LMV3xxA family is available in industry-standard
packages such as SOIC, MSOP, SOT-23, and TSSOP
packages.
Package Information
PART NUMBER
LMV321A
LMV358A
LMV324A
(1)
RG
PACKAGE(1)
BODY SIZE (NOM)
DBV (SOT-23, 5)
1.60 mm × 2.90 mm
DCK (SC70, 5)
1.25 mm × 2.00 mm
D (SOIC, 8)
3.91 mm × 4.90 mm
DGK (VSSOP, 8)
3.00 mm × 3.00 mm
PW (TSSOP, 8)
3.00 mm × 4.40 mm
DDF (SOT-23, 8)
3.00 mm × 3.00 mm
D (SOIC, 14)
8.65 mm × 3.91 mm
DYY (SOT-23, 14)
4.20 mm × 1.90 mm
PW (TSSOP, 14)
4.40 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV321A, LMV358A, LMV324A
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SBOS923H – DECEMBER 2017 – REVISED APRIL 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Functions and Configurations.................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: LMV321A.................................. 6
6.5 Thermal Information: LMV358A.................................. 6
6.6 Thermal Information: LMV324A.................................. 6
6.7 Electrical Characteristics.............................................7
6.8 Typical Characteristics................................................ 8
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................15
8 Application and Implementation.................................. 16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 16
9 Power Supply Recommendations................................21
9.1 Input and ESD Protection......................................... 21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Documentation Support.......................................... 23
11.2 Receiving Notification of Documentation Updates.. 23
11.3 Support Resources................................................. 23
11.4 Trademarks............................................................. 23
11.5 Electrostatic Discharge Caution.............................. 23
11.6 Glossary.................................................................. 23
12 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (February 2022) to Revision H (April 2023)
Page
• Updated test condition of Electrical Characteristics table from "VS = (V+) – (V–) = 2.5 V to 5.5 V (±0.9 V to
±2.75 V)" to "VS = (V+) – (V–) = 2.5 V to 5.5 V (±1.25 V to ±2.75 V)"................................................................ 7
• Updated Typical Characteristics section.............................................................................................................8
Changes from Revision F (January 2020) to Revision G (February 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ............... 1
• Added SOT-23 (DYY) package to Description section....................................................................................... 1
• Added SOT-23 (DYY) package information to Pin Configuration and Functions section................................... 3
• Added SOT-23 (DYY) package to Thermal Information: LMV324A ...................................................................6
Changes from Revision E (September 2019) to Revision F (January 2020)
Page
• Added SOT-23 (U) package information to Pin Configuration and Functions section........................................ 3
2
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SBOS923H – DECEMBER 2017 – REVISED APRIL 2023
5 Pin Functions and Configurations
OUT
+IN
V-
V-
+IN
-IN
Figure 5-1. LMV321A DBV Package, 5-Pin SOT-23
(Top View)
Figure 5-2. LMV321A DCK Package, 5-Pin SOT-23,
SC70 (Top View)
Table 5-1. Pin Functions: LMV321A
PIN
DBV
DCK, DBV
(U)
TYPE(1)
–IN
4
3
I
Inverting input
+IN
3
1
I
Noninverting input
OUT
1
4
O
Output
V–
2
2
—
Negative (lowest) supply or ground (for single-supply operation)
V+
5
5
—
Positive (highest) supply
NAME
(1)
DESCRIPTION
I = input, O = output
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Figure 5-3. LMV358A D, DDF, DGK, or PW Packages, 8-Pin SOIC, VSSOP, or TSSOP (Top View)
Table 5-2. Pin Functions: LMV358A
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) supply or ground (for single-supply operation)
V+
8
—
Positive (highest) supply
(1)
I = input, O = output
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14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
-IN A
2
+IN A
A
B
D
C
Figure 5-4. LMV324A D, DYY, PW Packages, 14-Pin SOIC, SOT-23, TSSOP (Top View)
Table 5-3. Pin Functions: LMV324A
PIN
DESCRIPTION
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN C
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative (lowest) supply or ground (for single-supply operation)
V+
4
—
Positive (highest) supply
(1)
4
TYPE(1)
NAME
I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
Supply voltage, ([V+] – [V–])
Common-mode
Voltage(2)
Signal input pins
MIN
MAX
UNIT
0
6
V
(V–) – 0.5
Differential
Current(2)
(V+) + 0.5
V
(V+) – (V–) + 0.2
V
10
mA
–10
Output short-circuit(3)
Continuous
Operating, TA
–55
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage
2.5
5.5
UNIT
V
TA
Specified temperature
–40
125
°C
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6.4 Thermal Information: LMV321A
LMV321A
THERMAL
METRIC(1)
DBV (SOT-23)
DCK (SC70)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
232.8
239.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
153.8
148.5
°C/W
RθJB
Junction-to-board thermal resistance
100.9
82.3
°C/W
ψJT
Junction-to-top characterization parameter
77.2
54.5
°C/W
ψJB
Junction-to-board characterization parameter
100.4
81.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Thermal Information: LMV358A
LMV358A
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
D (SOIC)
DGK (VSSOP)
PW (TSSOP)
DDF (SOT-23)
UNIT
8 PINS
8 PINS
8 PINS
8 PINS
147.4
201.2
205.8
183.7
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
94.3
85.7
106.7
112.5
°C/W
RθJB
Junction-to-board thermal resistance
89.5
122.9
133.9
98.2
°C/W
ψJT
Junction-to-top characterization parameter
47.3
21.2
34.4
18.8
°C/W
ψJB
Junction-to-board characterization parameter
89
121.4
132.6
97.6
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.6 Thermal Information: LMV324A
LMV324A
THERMAL METRIC(1)
D (SOIC)
DYY (SOT-23)
PW (TSSOP)
14 PINS
14 PINS
8 PINS
102.1
154.3
148.3
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
56.8
86.8
68.1
°C/W
RθJB
Junction-to-board thermal resistance
58.5
67.9
92.7
°C/W
ψJT
Junction-to-top characterization parameter
20.5
10.1
16.9
°C/W
ψJB
Junction-to-board characterization parameter
58.1
67.5
91.8
°C/W
RθJA
6
Junction-to-ambient thermal resistance
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.5 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS /
2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1
±4
UNIT
OFFSET VOLTAGE
Vs = 5 V
VOS
Input offset voltage
dVOS/dT
VOS vs temperature
TA = –40°C to 125°C
PSRR
Power-supply rejection ratio
VS = 2.5 to 5.5 V, VCM = (V–)
Vs = 5 V, TA = –40°C to 125°C
±5
78
mV
±1
µV/°C
100
dB
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode
voltage range
Common-mode
rejection ratio
No phase reversal, rail-to-rail input
(V–) – 0.1
(V+) – 1
VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
86
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
95
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V
TA = –40°C to 125°C
V
dB
63
VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V
TA = –40°C to 125°C
77
68
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
Vs = 5 V
±10
pA
±3
pA
ƒ = 0.1 Hz to 10 Hz, Vs = 5 V
5.1
µVPP
ƒ = 1 kHz, Vs = 5 V
33
ƒ = 10 kHz, Vs = 5 V
30
ƒ = 1 kHz, Vs = 5 V
25
fA/√ Hz
1.5
pF
5
pF
NOISE
En
Input voltage noise
(peak-to-peak)
en
Input voltage noise density
in
Input current noise density
nV/√ Hz
INPUT CAPACITANCE
CID
Differential
CIC
Common-mode
OPEN-LOOP GAIN
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10 kΩ
AOL
Open-loop voltage gain
100
VS = 2.5 V, (V–) + 0.04 V < VO < (V+) – 0.04 V, RL = 10 kΩ
115
98
VS = 2.5 V, (V–) + 0.1 V < VO < (V+) – 0.1 V, RL = 2 kΩ
112
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ
128
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
Vs = 5 V
φm
Phase margin
VS = 5.5 V, G = 1
76
1
°
SR
Slew rate
Vs = 5 V
1.7
V/µs
tS
Settling time
tOR
Overload recovery time
VS = 5 V, VIN × gain > VS
THD+N
Total harmonic distortion
+ noise
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f = 1 kHz,
80-kHz measurement BW
VO
Voltage output swing
from supply rails
VS = 5.5 V, RL = 10 kΩ
20
50
VS = 5.5 V, RL = 2 kΩ
40
75
ISC
Short-circuit current
Vs = 5.5 V
ZO
Open-loop output impedance
Vs = 5 V, f = 1 MHz
To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
3
To 0.01%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
4
MHz
µs
0.9
µs
0.005%
OUTPUT
mV
±40
mA
1200
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
Power-on time
2.5 (±1.25)
IO = 0 mA, VS = 5.5 V
5.5 (±2.75)
70
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
VS = 0 V to 5 V, to 90% IQ level
125
150
50
V
µA
µs
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6.8 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
6
3.5
IB
I B+
IOS
4
IB+
IOS
2
IB and IOS (pA)
2
IB and IOS (pA)
IB
3
2.5
0
-2
-4
1.5
1
0.5
0
-0.5
-1
-6
-1.5
-8
-2
-10
-40
-2.5
-20
0
20
40
60
80
Temperature (qC)
100
120
-3
140
-2
-1
0
1
Common-Mode Voltage (V)
D006
2
3
D007
Figure 6-2. IB and IOS vs Common-Mode Voltage
Figure 6-1. IB and IOS vs Temperature
160
140
100
120
80
100
60
80
40
60
20
40
80
60
40
0
20
VS = 5.5 V
VS = 2.5 V
0
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
20
Gain
Phase
-20
1k
0
10k
140
100k
Frequency (Hz)
1M
D009
CL = 10 pF
D008
Figure 6-3. Open-Loop Gain vs Temperature
Figure 6-4. Open-Loop Gain and Phase vs Frequency
80
160
Gain = 1
Gain = 1
Gain = 10
Gain = 100
Gain = 1000
70
140
60
120
50
100
40
Gain (dB)
Open-Loop Voltage Gain (dB)
Phase (q)
100
Gain (dB)
Gain (dB)
120
80
60
30
20
10
40
0
20
-10
0
-3
-2
-1
0
1
Output Voltage (V)
2
3
-20
100
1k
D010
Figure 6-5. Open-Loop Gain vs Output Voltage
10k
100k
Frequency (Hz)
1M
D011
CL = 10 pF
Figure 6-6. Closed-Loop Gain vs Frequency
8
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6.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
120
3
Power Supply Rejection Ratio (dB)
2.5
2
Output Voltage (V)
1.5
125°C
85°C
1
25°C
-40°C
0.5
0
-0.5
-1
85°C
-1.5
25°C
-40°C
125°C
-2
PSRR+
PSRR
100
80
60
40
20
-2.5
0
100
-3
0
5
10
15
20
25
30
35
Output Current (mA)
40
45
50
120
100k
1M
D013
120
Common-Mode Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
10k
Frequency (Hz)
Figure 6-8. PSRR vs Frequency
Figure 6-7. Output Voltage vs Output Current (Claw)
100
80
60
40
20
0
-40
1k
D012
-20
0
20
40
60
80
Temperature (qC)
100
120
100
80
60
40
20
0
100
140
1k
D014
10k
Frequency (Hz)
100k
1M
D015
Figure 6-10. CMRR vs Frequency
VS = 1.25 V to 5.5 V
Amplitude (1 PV/div)
Figure 6-9. DC PSRR vs Temperature
2.5 V
Time (1 s/div)
D017
Figure 6-12. 0.1 Hz to 10 Hz Integrated Voltage Noise
VCM = (V–) – 0.1 V to (V+) – 1.4 V
Figure 6-11. DC CMRR vs Temperature
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6.8 Typical Characteristics
-50
120
100
-60
80
THD + N (dB)
Input Voltage Noise Spectral Density (nV/—Hz)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
60
40
-70
-80
-90
20
RL = 2K
RL = 10K
0
10
100
1k
Frequency (Hz)
10k
-100
100
100k
1k
Frequency (Hz)
D018
Figure 6-13. Input Voltage Noise Spectral Density
10k
D019
VS = 5.5 V, VCM = 2.5 V, G = 1, BW = 80 kHz, VOUT = 0.5
VRMS
Figure 6-14. THD + N vs Frequency
70
0
G = +1, RL = 2 k:
G = +1, RL = 10 k:
G = 1, RL = 2 k:
G = 1, RL = 10 k:
60
Quiescent Current (PA)
THD + N (dB)
-20
-40
-60
50
40
30
20
-80
10
-100
0.001
0.01
0.1
Amplitude (V RMS)
1
0
1.5
2
2
2.5
D020
3
3.5
4
Voltage Supply (V)
4.5
5
5.5
D021
Figure 6-16. Quiescent Current vs Supply Voltage
VS = 5.5 V, VCM = 2.5 V, f = 1 kHz, G = 1, BW = 80 kHz
Figure 6-15. THD + N vs Amplitude
70
Open-Loop Output Impedance (:)
2000
Quiescent Current (PA)
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
Figure 6-17. Quiescent Current vs Temperature
10
140
D022
1800
1600
1400
1200
1000
800
600
400
200
0
1k
10k
100k
Frequency (Hz)
1M
10M
D023
Figure 6-18. Open-Loop Output Impedance vs Frequency
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6.8 Typical Characteristics
50
50
45
45
40
40
35
35
Overshoot (%)
Overshoot (%)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
30
25
20
30
25
20
15
15
10
10
Overshoot (+)
Overshoot (–)
5
Overshoot (+)
Overshoot (–)
5
0
0
0
200
400
600
Capacitance Load (pF)
800
0
1000
200
400
600
Capacitance Load (pF)
D024
800
1000
D025
G = –1, VIN = 100 mVpp
G = 1, VIN = 100 mVpp
Figure 6-19. Small Signal Overshoot vs Capacitive Load
Figure 6-20. Small Signal Overshoot vs Capacitive Load
90
VOUT
VIN
80
Amplitude (1 V/div)
Phase Margin (q)
70
60
50
40
30
20
10
0
0
200
400
600
Capacitance Load (pF)
800
Time (100 Ps/div)
1000
D027
D026
G = 1, VIN = 6.5 VPP
Figure 6-21. Phase Margin vs Capacitive Load
Figure 6-22. No Phase Reversal
VOUT
VIN
Amplitude (1 V/div)
Voltage (20 mV/div)
VOUT
VIN
Time (20 Ps/div)
Time (10 Ps/div)
D028
G = –10, VIN = 600 mVPP
Figure 6-23. Overload Recovery
D029
G = 1, VIN = 100 mVPP, CL = 10 pF
Figure 6-24. Small-Signal Step Response
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6.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Voltage (1 V/div)
Output Voltage (1 mV/div)
VOUT
VIN
Time (1 μs/div)
Time (10 Ps/div)
D031
D030
G = 1, CL = 100 pF, 2-V step
G = 1, VIN = 4 VPP, CL = 10 pF
Figure 6-26. Large-Signal Settling Time (Negative)
Figure 6-25. Large-Signal Step Response
80
Short Circuit Current (mA)
Output Voltage (1 mV/div)
60
40
20
0
-20
-40
-60
-80
-40
Time (1 Ps/div)
Sinking
Sourcing
-20
0
20
40
60
Temperature (qC)
D032
G = 1, CL = 100 pF, 2-V step
80
100
120
D033
Figure 6-28. Short-Circuit Current vs Temperature
Figure 6-27. Large-Signal Settling Time (Positive)
6
140
120
5
100
4
EMIRR (dB)
Maximum Output Voltage (V)
VS = 5.5 V
3
60
2
40
1
20
0
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D034
Figure 6-29. Maximum Output Voltage vs Frequency
12
80
0
10M
100M
1G
Frequency (Hz)
10G
D035
Figure 6-30. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
0
Channel Separation (dB)
-20
-40
-60
-80
-100
-120
-140
1k
10k
100k
Frequency (Hz)
1M
10M
D036
Figure 6-31. Channel Separation
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7 Detailed Description
7.1 Overview
The LMV3xxA is a family of low-power, rail-to-rail output op amps. These devices operate from 2.5 V to
5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input
common-mode voltage range includes the negative rail and allows the LMV3xxA family to be used in many
single-supply applications. Rail-to-rail output swing significantly increases dynamic range, especially in lowsupply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
14
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7.3 Feature Description
7.3.1 Operating Voltage
The LMV3xxA family of op amps are for operate from 2.5 V to 5.5 V. In addition, many specifications such
as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C.
Parameters that vary significantly with operating voltages or temperature are shown in Section 6.8.
7.3.2 Input Common Mode Range
The input common-mode voltage range of the LMV3xxA family extends 100 mV beyond the negative supply rail
and within 1 V below the positive rail for the full supply voltage range of 2.5 V to 5.5 V. This performance
is achieved with a P-channel differential pair, as shown in the Functional Block Diagram. Additionally, a
complementary N-channel differential pair has been included in parallel to eliminate issues with phase reversal
that are common with previous generations of op amps. However, the N-channel pair is not optimized for
operation. TI recommends limiting any voltages applied at the inputs to less than VCC – 1 V to ensure that the op
amp conforms to the specifications detailed in the Electrical Characteristics table.
7.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the LMV3xxA family delivers a robust output
drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
7.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the LMV3xxA family is approximately 850 ns.
7.4 Device Functional Modes
The LMV3xxA family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 2.5 V (±1.25 V) and 5.5 V (±2.75 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The LMV3xxA family of low-power, rail-to-rail output operational amplifiers is specifically designed for portable
applications. The devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of
general-purpose applications. The class AB output stage is capable of driving less than or equal to 10‑kΩ loads
connected to any point between V+ and V–. The input common-mode voltage range includes the negative rail,
and allows the LMV3xxA devices to be used in many single-supply applications.
8.2 Typical Application
8.2.1 LMV3xxA Low-Side, Current Sensing Application
Figure 8-1 shows the LMV3xxA configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5V
+
LMV358A
RSHUNT
0.1 Ÿ
VSHUNT
í
VOUT
í
+
RF
57.6 NŸ
RG
1.2 NŸ
Figure 8-1. LMV3xxA in a Low-Side, Current-Sensing Application
16
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8.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1.
VOUT = ILOAD × RSHUNT × Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
shown using Equation 2.
V
RSHUNT = ISHUNT_MAX = 100 mV
1 A = 100 mΩ
(2)
LOAD_MAX
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the LMV3xxA to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the
LMV3xxA to produce the necessary output voltage is calculated using Equation 3.
Gain =
VOUT_MAX − VOUT_MIN
VIN_MAX − VIN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the LMV3xxA to 49 V/V.
Gain = 1 +
RF
RG
(4)
Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 8-2 shows the
measured transfer function of the circuit shown in Figure 8-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.
8.2.1.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
1
C219
Figure 8-2. Low-Side, Current-Sense Transfer Function
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8.2.2 Single-Supply Photodiode Amplifier
Photodiodes are used in many applications to convert light signals to electrical signals. The current through
the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred
picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert
the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in Figure 8-3 is
an example of a single-supply photodiode amplifier circuit using the LMV358A.
+3.3 V
R1
11.5 NŸ
CF
10 pF
R2
357 Ÿ
RF
309 NŸ
VREF
+3.3 V
±
VOUT
LMV358A
VREF
IIN
0-10 µA
+
CPD
47 pF
RL
10 k
Figure 8-3. Single-Supply Photodiode Amplifier Circuit
18
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8.2.2.1 Design Requirements
The design requirements for this design are:
•
•
•
•
Supply voltage: 3.3 V
Input: 0 µA to 10 µA
Output: 0.1 V to 3.2 V
Bandwidth: 50 kHz
8.2.2.2 Detailed Design Procedure
The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF)
is defined in Equation 5.
Where:
VOUT = IIN × RF + VREF
(5)
R × R
VREF = V+ × R1 + R2
1
2
(6)
Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio
calculated in Equation 7.
VREF
0.1 V
V+ = 3.3 V = 0.0303
(7)
The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω.
The required feedback resistance can be calculated based on the input current and desired output voltage.
V
− VREF
− 0.1 V
RF = OUTI
= 3.2 V
= 310 kV
10 µA
A ≈ 309 kΩ
IN
(8)
Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3dB) using
Equation 9.
CF = 2 × π × R 1 × f
F
−3 dB
1
= 2 × π × 309 kΩ
× 50 kHz = 10.3 pF ≈ 10 pF
(9)
The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the
capacitance on the INx– pin of the LMV358A which is equal to the sum of the photodiode shunt capacitance,
(CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10
shows.
CIN = CPD + CCM + CD = 47 pF + 5 pF + 1 pF = 53 pF
(10)
The minimum op amp bandwidth is calculated in Equation 11.
C
+ C
F
f = BGW ≥ 2 × π IN
× RF × CF2 ≥ 324 kHz
(11)
The 1-MHz bandwidth of the LMV3xxA meets the minimum bandwidth requirement and remains stable in this
application configuration.
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8.2.2.3 Application Curves
The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in Figure 8-4. The
measured performance of the photodiode amplifier circuit is shown in Figure 8-5.
3
120
2.5
Output Voltage (V)
Gain (dB)
100
80
2
1.5
1
60
0.5
40
10
0
100
1k
10k
Frequency (Hz)
100k
1M
Figure 8-4. Photodiode Amplifier Circuit AC Gain
Results
20
0
2E-6
D001
4E-6
6E-6
Input Current (A)
8E-6
1E-5
D002
Figure 8-5. Photodiode Amplifier Circuit DC
Results
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9 Power Supply Recommendations
The LMV3xxA family is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications
apply from –40°C to 125°C. Section 6.8 presents parameters that may exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see Section 6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Section 10.1.
9.1 Input and ESD Protection
The LMV3xxA family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA. Figure 9-1 shows how a series input resistor can be added to the driven input to limit the input current.
The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in
noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 9-1. Input Current Protection
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power connections of the board and propagate to the
power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a
low-impedance path to ground.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as
opposed to running the traces in parallel with the noisy trace.
Place the external components as close to the device as possible, as shown in Figure 10-2. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN 1
+
VIN 2
VOUT 1
RG
VOUT 2
RG
RF
RF
Figure 10-1. Schematic Representation
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
Ground (GND) plane on another layer
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Figure 10-2. Layout Example
22
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LMV321AIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1OIF
Samples
LMV321AIDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1C2
Samples
LMV321AUIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1WOF
Samples
LMV324AIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LMV324
Samples
LMV324AIDYYR
ACTIVE
SOT-23-THIN
DYY
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM324I
Samples
LMV324AIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
LMV324A
Samples
LMV358AIDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
358A
Samples
LMV358AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1MAX
Samples
LMV358AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1MAX
Samples
LMV358AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
MV358A
Samples
LMV358AIPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
LMV358
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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