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LMV341, LMV342, LMV344
SLOS447I – SEPTEMBER 2004 – REVISED MAY 2016
LMV34x Rail-to-Rail Output CMOS Operational Amplifiers
With Shutdown
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The LMV34x devices are single, dual, and quad
CMOS operational amplifiers, respectively, with low
voltage, low power, and rail-to-rail output swing
capabilities. The PMOS input stage offers an ultra-low
input bias current of 1 pA (typical) and an offset
voltage of 0.25 mV (typical). The single-supply
amplifier is designed specifically for low-voltage
(2.7 V to 5 V) operation, with a wide common-mode
input voltage range that typically extends from –0.2 V
to 0.8 V from the positive supply rail. The LMV341
(single) also offers a shutdown (SHDN) pin that can
be used to disable the device. In shutdown mode, the
supply current is reduced to 33 nA (typical).
Additional features of the family are a 20-nV/√Hz
voltage noise at 10 kHz, 1-MHz unity-gain bandwidth,
1-V/μs slew rate, and 100-μA current consumption
per channel.
1
•
2.7-V and 5-V Performance
Rail-to-Rail Output Swing
Input Bias Current:1 pA (Typical)
Input Offset Voltage: 0.25 mV (Typical)
Low Supply Current: 100 μA (Typical)
Low Shutdown Current: 45 pA (Typical)
Gain Bandwidth of 1 MHz (Typical)
Slew Rate: 1 V/μs (Typical)
Turnon Time From Shutdown: 5 μs (Typical)
Input Referred Voltage Noise (at 10 kHz):
20 nV/√Hz
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (HBM)
– 750-V Charged-device model (CDM)
2 Applications
•
•
•
•
•
•
•
•
•
Cordless and Cellular Phones
Consumer Electronics (Laptops, PDAs)
Audio Preamplifiers for Voice
Portable, Battery-Powered Electronic Equipment
Supply-Current Monitoring
Battery Monitoring
Buffers
Filters
Drivers
Offered in both the SOT-23 and smaller SC70
packages, the LMV341 is suitable for the most spaceconstraint applications. The LMV342 dual device is
offered in the standard SOIC and VSSOP packages.
An extended industrial temperature range from –40°C
to 125°C makes these devices suitable in a wide
variety of commercial and industrial environments.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMV341IDCK
SC70 (6)
2.00 mm × 1.25 mm
LMV341IDBV
SOT-23 (6)
2.90 mm ×1.60 mm
LMV342ID
SOIC (8)
4.90 mm × 3.91 mm
LMV342IDGK
VSSOP (8)
3.00 mm × 3.00 mm
LMV344ID
SOIC (14)
8.65 mm × 3.91 mm
LMV344IPW
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Sample-and-Hold Circuit
V+
V+
−
−
+
VI
VO
+
C = 200 pF
Sample
Clock
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV341, LMV342, LMV344
SLOS447I – SEPTEMBER 2004 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
5
5
5
5
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: V+ = 2.7 V ........................
Electrical Characteristics: V+ = 5 V ...........................
Shutdown Characteristics: V+ = 2.7 V.......................
Shutdown Characteristics: V+ = 5 V..........................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Examples................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (June 2012) to Revision I
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed Ordering Information table .................................................................................................................................... 1
2
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Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: LMV341 LMV342 LMV344
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SLOS447I – SEPTEMBER 2004 – REVISED MAY 2016
5 Pin Configuration and Functions
DBV or DCK Package
6-Pin SOT-23 or SC70
Top View
IN+
1
6
V !
+
GND
2
5
¯¯¯¯¯
SHDN
IN–
3
4
OUT
Pin Functions: LMV341
PIN
NAME
SOT-23, SC70
I/O
DESCRIPTION
IN+
1
I
Noninverting input on channel 1
IN–
3
I
Inverting input on channel 1
OUT
4
O
Output on channel 1
GND
2
—
Ground
SHDN
5
I
Shutdown active low
V+
6
—
Positive power supply
D or DGK Package
8-Pin SOIC or VSSOP
Top View
1OUT
1
8
V
+
1IN–
2
7
2OUT
1IN+
3
6
2IN–
GND
4
5
2IN+
Pin Functions: LMV342
PIN
NAME
SOIC, VSSOP
I/O
DESCRIPTION
1IN+
3
I
Noninverting input on channel 1
1IN–
2
I
Inverting input on channel 1
1OUT
1
O
Output on channel 1
2IN+
5
I
Noninverting input on channel 2
2IN–
6
I
Inverting input on channel 2
2OUT
7
O
Output on channel 2
GND
4
—
Ground
V+
8
—
Positive power supply
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D or PW Package
14-Pin SOIC or TSSOP
Top View
1OUT
1
14
4OUT
1IN–
2
13
4IN–
1IN+
3
12
4IN+
V
+
4
11
GND
2IN+
5
10
3IN+
2IN–
6
9
3IN–
2OUT
7
8
3OUT
Pin Functions: LMV344
PIN
NAME
I/O
SOIC, TSSOP
DESCRIPTION
1IN+
3
I
Noninverting input on channel 1
1IN–
2
I
Inverting input on channel 1
1OUT
1
O
Output on channel 1
2IN+
5
I
Noninverting input on channel 2
2IN–
6
I
Inverting input on channel 2
2OUT
7
O
Output on channel 2
3IN+
10
I
Noninverting input on channel 3
3IN–
9
I
Inverting input on channel 3
3OUT
8
O
Output on channel 3
4IN+
12
I
Noninverting input on channel 4
4IN–
13
I
Inverting input on channel 4
4OUT
14
O
Output on channel 4
GND
11
—
Ground
V+
4
—
Positive power supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
(2)
V+
Supply voltage
VID
Differential input voltage (3)
VI
Input voltage (either input)
VO
Output voltage
TJ
Operating virtual junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
4
–0.3
MAX
UNIT
5.5
V
±5.5
V
–0.3
5.5
V
–0.3
VCC + 0.3
V
150
°C
150
°C
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values (except differential voltages) are with respect to the network GND.
Differential voltages are at IN+ with respect to IN−.
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SLOS447I – SEPTEMBER 2004 – REVISED MAY 2016
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
V+
Supply voltage (single-supply operation)
2.5
5.5
UNIT
V
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
LMV342
THERMAL METRIC (1)
LMV344
D (SOIC)
LMV342
LMV344
DBV
(SOT-23)
LMV341
DCK
(SC70)
DGK
(VSSOP)
PW
(TSSOP)
UNIT
8 PINS
14 PINS
6 PINS
6 PINS
8 PINS
14 PINS
123.9
88.7
193.4
196.8
192.3
118
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
70.2
49
145.6
82.4
78.2
46.9
°C/W
RθJB
Junction-to-board thermal resistance
64.1
43
44.1
95.2
112.6
59.7
°C/W
ψJT
Junction-to-top characterization parameter
25
16.9
34.1
1.8
15.2
5.1
°C/W
ψJB
Junction-to-board characterization parameter
63.6
42.7
43.4
93.2
111.2
59.1
°C/W
RθJA
(1)
(2)
(3)
Junction-to-ambient thermal resistance (2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.5 Electrical Characteristics: V+ = 2.7 V
V+ = 2.7 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Average temperature coefficient of
input offset voltage
IIB
Input bias current
TEST CONDITIONS
TA
MIN
25°C
0.25
Full range
Full range
Input offset current
1
–40°C to 125°C
3
6.6
25°C
56
0 ≤ VICR ≤ 1.6 V
Full range
50
25°C
65
Full range
60
kSVR
Supply-voltage rejection ratio
2.7 V ≤ V+ ≤ 5 V
VICR
Common-mode input voltage
range
Lower range, CMRR ≥ 50 dB
25°C
Upper range, CMRR ≥ 50 dB
25°C
1.7
1.9
113
RL = 2 kΩ to 1.35 V
(1)
(2)
25°C
78
Full range
70
25°C
72
Full range
64
pA
nA
dB
82
–0.2
mV
fA
80
Common-mode rejection ratio
Large-signal voltage gain (2)
120
250
25°C
UNIT
μV/°C
–40°C to 85°C
CMRR
AV
4
1.7
0 ≤ VICR ≤ 1.7 V
RL = 10 kΩ to 1.35 V
MAX
4.5
25°C
IIO
TYP (1)
dB
0
103
V
dB
Typical values represent the most likely parametric norm.
GND + 0.2 V ≤ VO ≤ V+ – 0.2 V
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Electrical Characteristics: V+ = 2.7 V (continued)
V+ = 2.7 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low level
RL = 2 kΩ to 1.35 V
High level
Output swing
(delta from supply rails)
VO
Low level
RL = 10 kΩ to 1.35 V
High level
ICC
Output short-circuit current
MIN
25°C
TYP (1)
MAX
24
60
Full range
26
Full range
5
Full range
5.3
30
100
170
Full range
LMV344
25°C
Sinking
(3)
30
mV
40
25°C
LMV341,
LMV342
60
95
25°C
40
Full range
Sourcing
UNIT
95
25°C
25°C
Supply current (per channel)
IOS
TA
230
20
32
18
24
15
24
μA
mA
SR
Slew rate
RL = 10 kΩ
25°C
1
V/μs
GBM
Unity-gain bandwidth
RL = 10 kΩ, CL = 200 pF
25°C
1
MHz
Φm
Phase margin
RL = 100 kΩ
25°C
72
°
Gm
Gain margin
RL = 100 kΩ
25°C
20
dB
Vn
Equivalent input noise voltage
f = 1 kHz
25°C
40
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.001
pA/√Hz
THD
Total harmonic distortion
f = 1 kHz, AV = 1,
RL = 600 Ω, VI = 1 VPP
25°C
0.017%
(3)
Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates.
6.6 Electrical Characteristics: V+ = 5 V
V+ = 5 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Average temperature coefficient of
input offset voltage
IIB
Input bias current
IIO
Input offset current
TEST CONDITIONS
TA
MIN
25°C
TYP (1)
MAX
0.25
4
Full range
4.5
Full range
25°C
1
5
25°C
0 ≤ VICR ≤ 4 V
6.6
25°C
56
Full range
50
25°C
65
Full range
60
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio
2.7 V ≤ V+ ≤ 5 V
VICR
Common-mode input
voltage range
Lower range, CMRR ≥ 50 dB
25°C
Upper range, CMRR ≥ 50 dB
25°C
4
4.2
116
RL = 10 kΩ to 2.5 V
AV
Large-signal voltage gain (2)
RL = 2 kΩ to 2.5 V
(1)
(2)
6
25°C
78
Full range
70
25°C
72
Full range
64
107
nA
dB
82
–0.2
pA
fA
86
CMRR
0 ≤ VICR ≤ 3.9 V
200
375
–40°C to 125°C
mV
μV/°C
1.9
–40°C to 85°C
UNIT
dB
0
V
dB
Typical values represent the most likely parametric norm.
GND + 0.2 V ≤ VO ≤ V+ – 0.2 V
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Electrical Characteristics: V+ = 5 V (continued)
V+ = 5 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low level
RL = 2 kΩ to 2.5 V
High level
Output swing
(delta from supply rails)
VO
Low level
RL = 10 kΩ to 2.5 V
High level
ICC
MIN
25°C
TYP (1)
MAX
32
60
Full range
34
Full range
Output short-circuit current
7
Full range
7
30
107
200
Full range
40
μA
260
25°C
Sinking
(3)
mV
30
40
25°C
LMV341,
LMV342
LMV344
60
95
25°C
Full range
Sourcing
UNIT
95
25°C
25°C
Supply current (per channel)
IOS
TA
85
113
85
113
50
75
mA
SR
Slew rate
RL = 10 kΩ
25°C
1
V/μs
GBM
Unity-gain bandwidth
RL = 10 kΩ, CL = 200 pF
25°C
1
MHz
Φm
Phase margin
RL = 100 kΩ
25°C
70
°
Gm
Gain margin
RL = 100 kΩ
25°C
20
dB
Vn
Equivalent input noise voltage
f = 1 kHz
25°C
39
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.001
pA/√Hz
THD
Total harmonic distortion
f = 1 kHz, AV = 1,
RL = 600 Ω, VI = 1 VPP
25°C
0.012%
(3)
Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates.
6.7 Shutdown Characteristics: V+ = 2.7 V
V+ = 2.7 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ICC(SHDN)
Supply current in shutdown mode
t(on)
Amplifier turnon time
VSD
VSD = 0 V
TA
MIN
25°C
Recommended shutdown pin voltage range
Shutdown mode
MAX
1000
nA
1.5
μA
Full range
25°C
ON mode
TYP
0.045
25°C
UNIT
μs
5
2.4
2.7
0
0.8
V
6.8 Shutdown Characteristics: V+ = 5 V
V+ = 5 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ICC(SHDN)
Supply current in shutdown mode
t(on)
Amplifier turnon time
VSD
VSD = 0 V
TA
MIN
25°C
Recommended shutdown pin voltage range
Shutdown mode
MAX
1
Full range
1.5
25°C
ON mode
TYP
0.033
25°C
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UNIT
μA
μs
5
4.5
5
0
0.8
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6.9 Typical Characteristics
130
1000
V+ = 5 V
120
IIB − Input Bias Current − pA
ICC − Supply Current − µA
110
125°C
100
90
85°C
80
25°C
70
60
−40°C
50
100
10
1
40
30
1.5
2
2.5
3
3.5
4
4.5
0.1
−40 −20
5
VCC − Supply Voltage − V
7
RL = 2 kΩ
VO − Output Swing From Supply Voltage − mV
VO − Output Swing From Supply Voltage − mV
35
30
Negative Swing
25
20
Positive Swing
15
10
2
2.5
3
3.5
4
4.5
RL = 10 kΩ
6.5
6
5
4.5
4
Positive Swing
3.5
3
5
Negative Swing
5.5
1.5
2
2.5
3
3.5
4
4.5
5
VCC − Supply Voltage − V
VCC − Supply Voltage − V
Figure 3. Output Voltage Swing vs Supply Voltage
Figure 4. Output Voltage Swing vs Supply Voltage
1000
1000
V+ = 5 V
V+ = 2.7 V
IS − Source Current − mA
IS − Source Current − mA
−40°C
25°C
10
85°C
1
125°C
10
25°C
85°C
1
125°C
0.1
0.1
0.01
0.001
−40°C
100
100
0.01
0.1
1
10
VO − Output Voltage Referenced to V+ (V)
Figure 5. Source Current vs Output Voltage
8
140
Figure 2. Input Bias Current vs Temperature
Figure 1. Supply Current vs Supply Voltage
1.5
0
20
40
60
80 100 120
TA − Free-Air Temperature − °C
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0.01
0.001
0.01
0.1
1
10
VO − Output Voltage Referenced to V+ (V)
Figure 6. Source Current vs Output Voltage
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Typical Characteristics (continued)
1000
V+ = 2.7 V
V+ = 5 V
100
100
−40°C
−40°C
IS − Sink Current − mA
IS − Sink Current − mA
1000
10
25°C
85°C
1
125°C
0.1
10
25°C
85°C
1
125°C
0.1
0.01
0.001
0.01
0.1
1
0.01
0.001
10
VO − Output Voltage Referenced to V− (V)
Figure 7. Sink Current vs Output Voltage
1
0.5
0.5
0
0
VIO − Offset Voltage − mV
VIO − Offset Voltage − mV
V+ = 2.7 V
−0.5
−1
125°C
85°C
−2
0.1
1
10
Figure 8. Sink Current vs Output Voltage
1
−1.5
0.01
VO − Output Voltage Referenced to V− (V)
25°C
V+ = 5 V
−0.5
−1
125°C
85°C
−1.5
25°C
−2
−40°C
−40°C
−2.5
−2.5
−3
−0.2
0.8
1.8
−3
−0.2
2.8
VIC − Common-Mode Voltage − V
0.8
1.8
2.8
3.8
4.8
VIC − Common-Mode Voltage − V
Figure 9. Offset Voltage vs Common-Mode Voltage
Figure 10. Offset Voltage vs Common-Mode Voltage
300
300
V+ /GND = ±1.35 V
V+ /GND = ±2.5 V
VI − Input Voltage − mV
VI − Input Voltage − µV
200
RL = 2 kΩ
100
0
RL = 10 kΩ
200
0
−100
−200
−200
−2
−1
0
1
2
3
RL = 2 kΩ
100
−100
−300
−3
5.8
−300
−1.5
RL = 10 kΩ
−1
Figure 11. Input Voltage vs Output Voltage
−0.5
0
0.5
1
1.5
VO − Output Voltage − V
VO − Output Voltage − V
Figure 12. Input Voltage vs Output Voltage
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Typical Characteristics (continued)
2.5
1.9
RL = 10 kΩ
AV = 1
VI = 2 VPP
V+ = 2.7 V
2.3
Falling Edge
1.7
SR − Slew Rate − V/µs
SR − Slew Rate − V/µs
2.1
1.5
1.3
Rising Edge
1.1
0.9
0.5
1.5
2
Falling Edge
1.7
1.5
1.3
Rising Edge
1.1
0.9
RL = 10 kΩ
AV = 1
VI = 0.8 VPP for V+ < 2.7 V
VI = 2 VPP for V+ > 2.7 V
0.7
1.9
0.7
2.5
3
3.5
4
VCC − Supply Voltage − V
4.5
0.5
−40 −20
5
Figure 13. Slew Rate vs Supply Voltage
Figure 14. Slew Rate vs Temperature
2.5
100
RL = 10 kΩ
AV = 1
VI = 2 VPP
V+ = 5 V
2.3
90
1.9
70
Falling Edge
1.7
1.5
1.3
Rising Edge
60
50
2.7 V
40
1.1
30
0.9
20
0.7
10
0.5
−40 −20
5V
80
Gain − dB
SR − Slew Rate − V/µs
2.1
VI = V+ /2
RL = 5 kΩ
0
100
1k
0
20 40
60
80 100 120 140
TA – Free-Air Temperature – °C
Figure 15. Slew Rate vs Temperature
100
Figure 16. CMRR vs Frequency
VI − Input Voltage Noise − nV/ Hz
70
Gain − dB
1M
200
−PSRR (2.7 V)
80
−PSRR (5 V)
50
+PSRR (5 V)
40
30
20
10
0
100
1k
180
160
140
120
100
80
5V
2.7 V
60
40
20
RL = 5 kΩ
0
10k
100k
f − Frequency − Hz
1M
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10M
10
100
1k
10k
f − Frequency − Hz
Figure 17. PSRR vs Frequency
10
10k
100k
f − Frequency − Hz
220
+PSRR (2.7 V)
90
60
0
20
40
60
80 100 120 140
TA – Free-Air Temperature – °C
Figure 18. Input Voltage Noise vs Frequency
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10
RL = 600 Ω
VO = 1 VPP for V+ = 2.7 V
VO = 2.5 VPP for V+ = 5 V
1
5V
AV = 10
2.7 V
AV = 10
2.7 V
AV = 1
0.01
5V
AV = 1
0.001
0.0001
10
100
1k
10k
f − Frequency − Hz
100k
Figure 19. Total Harmonic Distortion + Noise vs Frequency
140
120
100
120
100
80
100
Gain − dB
120
−40°C
Gain
60
80
−40°C
25°C
60
40
125°C
20
−20
40
25°C
125°C
0
Phase Margin − Deg
Gain − dB
140
V+ = 5 V
RL = 2 kΩ
Phase
10k
100k
1M
2.7 V
AV = 10
0.1
5V
AV = 1
0.01
0.001
0.01
0.1
1
VO − Output Voltage − VPP
120
100
80
RL = 600 Ω
60
RL = 100 kΩ
V+ = 5 V
Closed-Loop
Gain = 60 dB
RL = 100 kΩ
40
RL = 2 kΩ
0
10k
100k
10M
RL = 2 kΩ
RL = 100 kΩ
80
60
40
RL = 100 kΩ
CL = 0 pF
100
60
80
40
CL = 500 pF
Gain
CL = 1000 pF
60
20
0
40
CL = 0 pF
20
40
20
RL = 600 Ω
100k
f − Frequency − Hz
1M
0
10M
(RL = 600 Ω, 2 kΩ, 100 kΩ)
Figure 23. Gain and Phase Margin vs Frequency
CL = 500 pF
−20
CL = 1000 pF
−40
−20
−40
0
RL = 2 kΩ
80
CL = 100 pF
Gain − dB
Gain
100
Phase
V+ = 5 V
RL = 600 Ω
Closed-Loop Gain = 60 dB
120
Phase Margin − Deg
Gain − dB
100
RL = 600 Ω
10k
1M
140
120
1k
20
RL = 600 Ω
(RL = 600 Ω, 2 kΩ, 100 kΩ)
Figure 22. Gain and Phase Margin vs Frequency
140
80
−20
60
40
f − Frequency − Hz
100
0
80
RL = 2 kΩ
Gain
1k
160
20
140
−20
10M
140
60
160
Phase
f − Frequency − Hz
Phase
10
V+ = 2.7 V
Closed-Loop
Gain = 60 dB
0
(TA = –40°C, 25°C, 125°C)
Figure 21. Gain and Phase Margin vs Frequency
120
2.7 V
AV = 1
20
20
0
1k
1
Figure 20. Total Harmonic Distortion + Noise vs Output
Voltage
160
140
5V
AV = 10
Phase Margin − Deg
0.1
f = 10 kHz
RL = 600 Ω
Phase Margin − Deg
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
Typical Characteristics (continued)
1k
10k
100k
f − Frequency − Hz
1M
−60
CL = 100 pF
10M
−80
(CL = 0 pF, 100 pF, 500 pF, 1000 pF)
Figure 24. Gain and Phase Margin vs Frequency
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Typical Characteristics (continued)
0.1
Input
0.1
TA = −40°C
RL = 2 kΩ
V+/GND = ±2.5 V
−0.05
−0.1
0.05
−0.15
0
VI − Input Voltage − V
VO − Output Voltage − V
0
0.15
VO − Output Voltage − V
0.05
0.2
−0.2
−0.05
2
6
Input
5
1
4
0
−1
3
2
TA = −40°C
RL = 2 kΩ
V+/GND = ±2.5 V
1
−3
0
−4
−5
−1
Output
−0.1
4 µs/div
Output
−0.25
−6
−2
Figure 25. Small-Signal Noninverting Response
4 µs/div
Figure 26. Large-Signal Noninverting Response
0.1
0.25
−2
VI − Input Voltage − V
0.25
2
6
TA = 25°C
RL = 2 kΩ
V+/GND = ±2.5 V
−0.05
−0.1
0.05
−0.15
0
VO − Output Voltage − V
0
0.15
VI − Input Voltage − V
VO − Output Voltage − V
1
4
0
0.05
0.2
0.1
5
2
−1
TA = 25°C
RL = 2 kΩ
V+/GND = ±2.5 V
−2
1
−3
0
−4
−1
−0.2
−0.05
3
VI − Input Voltage − V
Input
Input
−5
Output
Output
−2
−0.25
−6
4 µs/div
4 µs/div
Figure 28. Large-Signal Noninverting Response
Figure 27. Small-Signal Noninverting Response
0.1
0.25
2
6
Input
Input
0.1
TA = 125°C
RL = 2 kΩ
V+/GND = ±2.5 V
5
1
0
4
0
−0.05
−0.1
0.05
−0.15
0
−0.05
−0.2
VO − Output Voltage − V
0.15
0.05
VI − Input Voltage − V
VO − Output Voltage − V
0.2
−1
3
2
TA = 125°C
RL = 2 kΩ
V+/GND = ±2.5 V
1
−3
0
−4
−5
−1
Output
Output
−0.1
4 µs/div
−0.25
Figure 29. Small-Signal Noninverting Response
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−2
VI − Input Voltage − V
−0.1
−2
4 µs/div
−6
Figure 30. Large-Signal Noninverting Response
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Typical Characteristics (continued)
0.1
0.25
6
−0.1
−0.15
0
−0.2
−0.05
1
4
0
3
2
−1
TA = −40°C
RL = 2 kΩ
V+/GND = ±2.5 V
−2
1
−3
0
−4
−1
−5
Output
Output
−0.25
−2
4 µs/div
4 µs/div
Figure 32. Large-Signal Inverting Response
Figure 31. Small-Signal Inverting Response
6
0.1
0.25
TA = 25°C
RL = 2 kΩ
V+/GND = ±2.5 V
−0.05
−0.1
0.05
−0.15
0
−0.2
−0.05
VO − Output Voltage − V
0
0.15
VI − Input Voltage − V
0.05
0.2
VO − Output Voltage − V
2
Input
Input
0.1
5
1
4
0
3
2
−1
TA = 25°C
RL = 2 kΩ
V+/GND = ±2.5 V
−2
1
−3
0
−4
−1
−5
Output
Output
−0.25
−0.1
−2
−6
4 ms/div
4 µs/div
Figure 33. Small-Signal Inverting Response
Figure 34. Large-Signal Inverting Response
0.1
0.25
Input
0
0.15
TA = 125°C
RL = 2 kΩ
V+/GND = ±2.5 V
−0.05
−0.1
0.05
−0.15
0
−0.2
−0.05
VO − Output Voltage − V
0.05
VI − Input Voltage − V
VO − Output Voltage − V
2
6
Input
0.2
0.1
−6
VI − Input Voltage − V
−0.1
5
1
4
0
−1
3
2
TA = 125°C
RL = 2 kΩ
V+/GND = ±2.5 V
−2
1
−3
0
−4
VI − Input Voltage − V
0.05
5
VI − Input Voltage − V
−0.05
TA = −40°C
RL = 2 kΩ
V+/GND = ±2.5 V
VO − Output Voltage − V
VO − Output Voltage − V
0
0.15
VI − Input Voltage − V
0.05
0.2
0.1
2
Input
Input
−5
−1
Output
Output
−0.25
−0.1
−6
−2
4 µs/div
4 µs/div
Figure 35. Small-Signal Inverting Response
Figure 36. Large-Signal Inverting Response
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7 Detailed Description
7.1 Overview
The LMV34x devices are precision operational amplifiers with CMOS inputs for very low input bias current.
Output is rail-to-rail and input common-mode includes ground. LMV341 has a shutdown mode for very low supply
current.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 PMOS Input Stage
PMOS Input Stage supports a lower input range that includes ground. Upper range limit is V+ – 1 V.
7.3.2 CMOS Output Stage
The CMOS drain output topology allows rail-to-rail output swing.
7.3.3 Shutdown
LMV341 includes a shutdown pin. During shutdown, ICC is nearly zero and the output becomes high impedance.
The typical turnon time coming out of shutdown is 5 µs.
7.4 Device Functional Modes
The LMV34x devices have two modes of operation:
• Normal operation when SHDN pin is at V+ level or the SHDN pin is not present
• Shutdown mode when SHDN is at GND level; ICC is very low and output is high impedance.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
LMV34x devices have rail-to-rail output and input range from ground to VCC – 1 V. CMOS inputs provide very
low input current. Shutdown capability is an option in dual amplifier version. Operation from 2.5-V to 5.5-V is
possible.
8.2 Typical Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes
negative voltages positive.
RF
RI
Vsup+
VOUT
+
VIN
VsupCopyright © 2016, Texas Instruments Incorporated
Figure 37. Application Schematic
8.2.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ± 2 V is sufficient to
accommodate this application. The supplies can power up in any order; however, neither supply can be of
opposite polarity relative to ground at any time; otherwise, a large current can flow though the input ESD diodes.
To limit current in such an occurrence, TI highly recommends adding a series resistor to the grounded input.
Vsup+ must be more positive than Vsup– at all times; otherwise, a large reverse supply current may flow.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 1 and Equation 2.
(1)
(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩ range is desirable
because the amplifier circuit uses currents in the mA range. This ensures the part does not draw too much
current. For this example, choose 10 kΩ for RI, which means 36 kΩ is used for RF. This was determined by
Equation 3.
(3)
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Typical Application (continued)
8.2.3 Application Curve
2
VIN
1.5
VOUT
1
Volts
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 38. Input and Output Voltages of the Inverting Amplifier
9 Power Supply Recommendations
CAUTION
Supply voltages larger than 5.5 V for a single supply can permanently damage the
device (see the Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, and pay attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Examples.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Examples
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
VS+
NC
NC
IN1í
VCC+
IN1+
OUT
VCCí
NC
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 39. Operational Amplifier Layout for Noninverting Configuration
VIN
RIN
RG
+
VOUT
RF
Figure 40. Operational Amplifier Schematic for Noninverting Configuration
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMV341
Click here
Click here
Click here
Click here
Click here
LMV342
Click here
Click here
Click here
Click here
Click here
LMV344
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV341IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(RC9A, RC9E, RC9S)
LMV341IDBVRE4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(RC9A, RC9E, RC9S)
LMV341IDBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(RC9A, RC9E, RC9S)
LMV341IDCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(R4A, R4E)
LMV341IDCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(R4A, R4E)
LMV342ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
MV342I
LMV342IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
RPA
LMV342IDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
RPA
LMV342IDGKT
PREVIEW
VSSOP
DGK
8
250
TBD
Call TI
Call TI
-40 to 125
LMV342IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
MV342I
LMV342IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
MV342I
LMV344ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LMV344I
LMV344IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LMV344I
LMV344IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LMV344I
LMV344IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
MV344I
LMV344IPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
MV344I
LMV344IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
MV344I
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
LMV344IPWRG4
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
14
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
MV344I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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