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LMV7231
SNOSB45F – FEBRUARY 2010 – REVISED JANUARY 2016
LMV7231 Hex Window Comparator With 1.5% Precision and 400-mV Reference
1 Features
3 Description
•
The LMV7231 device is a 1.5% accurate Hex
Window Comparator which can be used to monitor
power supply voltages or any other analog output,
such as an analog temperature sensor or currentsense amplifier. The device uses an internal 400-mV
reference for the comparator trip value. The
comparator set points can be set through external
resistor dividers. The LMV7231 has 6 outputs (CO1
to CO6) that signal an undervoltage or overvoltage
event for each power supply input. An output (AO) is
also provided to signal when any of the power supply
inputs have an overvoltage or undervoltage event.
This ability to signal an undervoltage or overvoltage
event for the individual power supply inputs, in
addition to an output to signal such an event on any
of the power supply inputs, adds unparalleled system
protection capability.
1
•
•
•
•
•
•
•
•
•
•
(For VS = 3.3 V ±10%, Typical Unless Otherwise
Noted)
Undervoltage and Overvoltage Detection
High Accuracy Voltage Reference: 400 mV
Threshold Accuracy: ±1.5% (Maximum)
Wide Supply Voltage Range 2.2 V to 5.5 V
Input and Output Voltage Range Above V+
Internal Hysteresis: 6 mV
Propagation Delay: 2.6 µs to 5.6 µs
Supply Current 7.7 µA Per Channel
24-Lead WQFN Package
Temperature Range: –40°C to +125°C
2 Applications
•
•
•
•
•
The 2.2-V to 5.5-V power supply voltage range, low
supply current, and input or output voltage range
above V+ make the LMV7231 ideal for a wide range
of power supply monitoring applications. Operation is
ensured over the –40°C to +125°C temperature
range. The device is available in a 24-pin WQFN
package.
Power Supply Voltage Monitoring
Battery Monitoring
Handheld Instruments
Relay Driving
Industrial Control Systems
Device Information(1)
PART NUMBER
LMV7231
PACKAGE
WQFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Typical Application
V+
Monitored Voltage #1
COPOL
Channel 1
+
-
+IN1
Monitored Voltage #6
*
*
+
-
-IN1
REF
OV1 UV1
CO1
COPOL
CO6
Channel 6
+IN6
Controller
(FPGA)
-IN6
REF
REF
+400mV
LMV7231
OV6 UV6
OV1
OV2
OV3
OV4
OV5
OV6
UV1
UV2
UV3
UV4
UV5
UV6
AOSEL
AO
*
* Open Drain
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV7231
SNOSB45F – FEBRUARY 2010 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
3.3-V Electrical Characteristics .................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 17
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings and Thermal Information
tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
Changes from Revision D (March 2013) to Revision E
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 17
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SNOSB45F – FEBRUARY 2010 – REVISED JANUARY 2016
5 Pin Configuration and Functions
CO5
CO4
CO3
CO2
CO1
V+
RTW Package
24-Pin WQFN
Top View
-IN1
CO6
+IN1
AO
-IN2
AOSEL
LMV7231
+IN2
COPOL
+IN6
-IN6
+IN5
-IN5
RESERVED
-IN4
GND
+IN3
+IN4
-IN3
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
–IN1
Analog Input
Negative input for window comparator 1
2
+IN1
Analog Input
Positive input for window comparator 1
3
–IN2
Analog Input
Negative input for window comparator 2
4
+IN2
Analog Input
Positive input for window comparator 2
5
–IN3
Analog Input
Negative input for window comparator 3
6
+IN3
Analog Input
Positive input for window comparator 3
7
–IN4
Analog Input
Negative input for window comparator 4
8
+IN4
Analog Input
Positive input for window comparator 4
9
–IN5
Analog Input
Negative input for window comparator 5
10
+IN5
Analog Input
Positive input for window comparator 5
11
–IN6
Analog Input
Negative input for window comparator 6
12
+IN6
Analog Input
Positive input for window comparator 6
13
RESERVED
Digital Input
Connect to GND
14
GND
Power
15
COPOL
Digital Input
The state of this pin determines whether the CO1-CO6 pins are active “HIGH” or “LOW”. When tied LOW the
CO1-CO6 outputs go LOW to indicate an out-of-window comparison.
16
AOSEL
Digital Input
The state of this pin determines whether the AO pin is active on an overvoltage or undervoltage event. When
tied LOW the AO output is active upon an overvoltage event.
17
AO
Open-Drain NMOS
Digital Output
This output is the ANDED combination of either the overvoltage comparator outputs or the undervoltage
comparator outputs and is controlled by the state of the AOSEL. AO pin is active-low.
18
CO6
Open-Drain NMOS
Digital Output
Window comparator 6 NMOS open-drain output
19
CO5
Open-Drain NMOS
Digital Output
Window comparator 5 NMOS open-drain output
20
CO4
Open-Drain NMOS
Digital Output
Window comparator 4 NMOS open-drain output
21
CO3
Open-Drain NMOS
Digital Output
Window comparator 3 NMOS open-drain output
22
CO2
Open-Drain NMOS
Digital Output
Window comparator 2 NMOS open-drain output
23
CO1
Open-Drain NMOS
Digital Output
Window comparator 1 NMOS open-drain output
24
DAP
V+
Power
DAP
Thermal Pad
Ground reference pin for the power supply voltage
Power supply pin
Die Attach Paddle (DAP). Connect to GND.
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1) (2) (3)
.
MIN
Supply voltage
GND − 0.3
Voltage at input / output pin
Output current
Total package current
Junction temperature
(4)
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
MAX
UNIT
6
V
6
V
10
mA
50
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
For soldering specifications, see Absolute Maximum Ratings for Soldering (SNOA549).
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
±2000
Machine model
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions
Supply voltage
Junction temperature
(1)
4
(1)
MIN
MAX
2.2
5.5
UNIT
V
–40
125
°C
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
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6.4 Thermal Information
LMV7231
THERMAL METRIC (1)
RTW (WQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
37.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40.2
°C/W
RθJB
Junction-to-board thermal resistance
16.1
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
16.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 3.3-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 3.3 V ±10%, GND = 0 V, and RL > 1 MΩ.
PARAMETER
TEST CONDITION
MIN (1)
TYP (2)
MAX (1)
394
400
406
VTHR
Threshold: input rising
RL = 10 kΩ
VTHF
Threshold: input falling
RL = 10 kΩ
VHYST
Hysteresis (VTHR − VTHF)
RL = 10 kΩ
3.9
6.0
8.8
–5
0.05
5
Input bias current
VIN = V+, GND, and
5.5 V
VOL
Output low voltage
IL = 5 mA
IOFF
Output leakage current
VOUT = V+, 5.5 V and
40 mV of overdrive
tPDHL1
High-to-low propagation
delay (+IN falling)
10 mV of overdrive
High-to-low propagation
delay (-IN rising)
10 mV of overdrive
Low-to-high propagation
delay (+IN rising)
10 mV of overdrive
tPDLH2
Low-to-high propagation
delay (-IN falling)
10 mV of overdrive
tr
Output rise time
CL= 10 pF, RL= 10 kΩ
tf
Output fall time
CL = 100 pF, RL = 10
kΩ
IIN(1)
Digital input logic 1 leakage
current
TA = –10°C to +70°C
IIN(0)
Digital input logic 0 leakage
current
TA = –10°C to +70°C
VIH
Digital input logic 1 voltage
TA = –10°C to +70°C
VIL
Digital input logic 0 voltage
TA = –10°C to +70°C
tPDLH1
IS
Power supply current
VTHPSS
VTH power supply
sensitivity (3)
(1)
(2)
(3)
391.4
TA = –10°C to +70°C
383.8
386
IBIAS
tPDHL2
TA = –10°C to +70°C
TA = –10°C to +70°C
408.6
394
401
403.2
–15
15
160
TA = –10°C to +70°C
200
250
0.4
TA = –10°C to +70°C
1
2.6
6
5.4
10
5.6
10
2.8
6
0.25
0.3
0.2
1
0.2
No loading (outputs
high)
1
0.7 × V+
46
V+ ramp rate = 1.1 ms
V+ step = 4.5 V to 2.5 V
60
84
V+ ramp rate = 1.1 ms
V+ step = 2.5 V to 4.5 V
mV
mV
nA
mV
μA
μs
μs
μs
μs
μs
μA
μA
V
0.3 × V+
TA = –10°C to +70°C
mV
μs
0.5
TA = –10°C to +70°C
UNIT
400
–400
V
μA
μV
μV
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
VTH power supply sensitivity is defined as the temporary shift in the internal voltage reference due to a step on the V+ pin.
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6.6 Typical Characteristics
40
40
35
35
Relavtive Frequency (%)
Relative Frequency (%)
V+ = 3.3 V and TA =25°C unless otherwise noted.
30
25
20
15
10
30
25
20
15
10
5
5
0
396 397 398 399 400 401 402 403 404
0
396 397 398 399 400 401 402 403 404
Input Rising Threshold (mV)
Input Rising Threshold (mV)
Figure 2. −IN Input Rising Threshold Distribution
40
40
35
35
30
30
Relative Frequency (%)
Relative Frequency (%)
Figure 1. +IN Input Rising Threshold Distribution
25
20
15
10
25
20
15
10
5
5
0
390 391 392 393 394 395 396 397 398
0
390 391 392 393 394 395 396 397 398
Input Falling Threshold (mV)
Input Falling Threshold (mV)
Figure 4. −IN Input Falling Threshold Distribution
50
50
45
45
40
40
Relative Frequency (%)
Relative Frequency (%)
Figure 3. +IN Input Falling Threshold Distribution
35
30
25
20
15
35
30
25
20
15
10
10
5
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
Hysteresis (mV)
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
Hysteresis (mV)
Figure 5. +IN Hysteresis Distribution
6
0
4.0
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Figure 6. −IN Hysteresis Distribution
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Typical Characteristics (continued)
405
405
404
404
Input Rising Threshold Voltage (mV)
Input Rising Threshold Voltage (mV)
V+ = 3.3 V and TA =25°C unless otherwise noted.
403
402
401
+IN
400
399
398
-IN
397
396
395
-40 -20
403
402
401
+IN
400
399
398
-IN
397
396
395
0
20
40
60
2
80 100 120
3
Temperature (°C)
400
Input Falling Threshold Voltage (mV)
Input Falling Threshold Voltage (mV)
399
398
397
396
395
-IN
394
393
392
+IN
391
0
20
40
60
399
398
397
396
395
394
392
+IN
391
390
2
80 100 120
-IN
393
3
Figure 9. Input Falling Threshold Voltage vs Temperature
10
9
9
Hysteresis (mV)
7
6
5
-IN
3
7
6
5
3
2
1
1
20
40
60
80 100 120
Temperature (°C)
-IN
4
2
0
6
+IN
8
+IN
4
5
Figure 10. Input Falling Threshold Voltage vs Supply
Voltage
10
8
4
Supply Voltage (V)
Temperature (°C)
Hysteresis (mV)
6
Figure 8. Input Rising Threshold Voltage vs Supply Voltage
400
0
-40 -20
5
Supply Voltage (V)
Figure 7. Input Rising Threshold Voltage vs Temperature
390
-40 -20
4
0
2
3
4
5
6
Supply Voltage (V)
Figure 11. Hysteresis vs Temperature
Figure 12. Hysteresis vs Supply Voltage
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
60
50
125°C
TA = 25°C
49
50
48
40
Supply Current (PA)
Supply Current (éA)
85°C
25°C
30
-40°C
20
47
46
5.5V
45
44
3.3V
43
42
10
41
0
1
2
3
4
5
2.2V
40
0
6
1
2
Supply Voltage (V)
Supply Current (PA)
Supply Current (PA)
53
5.5V
3.3V
35
34
33
2.2V
2
3
4
5
6
7
8
9
2.2V
48
46
1
3.3V
49
31
45
0
10
1
2
3
4
5
6
7
8
9
10
Output Sink Current (mA)
Figure 15. Supply Current vs Output Sink Current
Figure 16. Supply Current vs Output Sink Current
60
5
TA = 125°C
-40°C
+IN, -IN
58
0
5.5V
Bias Currant (nA)
Supply Current (PA)
10
50
Output Sink Current (mA)
56
3.3V
55
54
53
85°C
+IN, -IN
-5
-10
25°C
+IN, -IN
2.2V
52
-15
25°C
+IN, -IN
51
1
2
3
4
5
6
7
8
9
10
Output Sink Current (mA)
-20
-0.3
-0.2
-0.1
Input Voltage (V)
Figure 17. Supply Current vs Output Sink Current
8
9
5.5V
51
47
50
0
8
52
32
57
7
TA = 85°C
54
36
59
6
55
TA = -40°C
38
30
0
5
Figure 14. Supply Current vs Output Sink Current
40
37
4
Output Sink Current (mA)
Figure 13. Supply Current vs Supply Voltage and
Temperature
39
3
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Figure 18. Bias Current vs Input Voltage
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
0.4
2.0
125°C -IN
1.6
Bias Current (nA)
Bias Current (nA)
0.3
25°C -IN
0.2
-40°C -IN
0.1
25°C +IN
125°C +IN
1.2
0.8
85°C -IN
0.4
-40°C +IN
0.0
0.0
0.6
1.2
1.8
2.4
3.0
0.0
0.0
3.6
85°C +IN
0.6
1.2
Input Voltage (V)
Figure 19. Bias Current vs Input Voltage
TA = 25°C
TA = 85°C
Output Voltage Low (mV)
Output Voltage Low (mV)
250
V+ = 3.3V
200
150
100
4
6
400
V+ = 3.3V
300
200
100
V+ = 5.5V
2
V+ = 2.2V
500
300
50
V+ = 5.5V
8
0
0
10
2
Ouput Sink Current (mA)
4
6
8
10
Output Sink Current (mA)
Figure 21. Output Voltage Low vs Output Sink Current
Figure 22. Output Voltage Low vs Output Sink Current
350
700
TA = -40°C
TA = 125°C
300
600
V+ = 2.2V
Output Voltage Low (mV)
Output Voltage Low (mV)
3.6
Figure 20. Bias Current vs Input Voltage
V+ = 2.2V
250
200
V+ = 3.3V
150
100
50
V+ = 2.2V
500
400
V+ = 3.3V
300
200
100
V+ = 5.5V
V+ = 5.5V
0
0
3.0
600
350
0
0
2.4
Input Voltage (V)
450
400
1.8
2
4
6
8
0
0
10
2
4
6
8
10
Output Sink Current (mA)
Output Sink Current (mA)
Figure 23. Output Voltage Low vs Output Sink Current
Figure 24. Output Voltage Low vs Output Sink Current
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
100
70
V+ = 3.3V
Output Short Circuit Current (mA)
Output Short Circuit Current (mA)
TA = 25°C
80
V+ = 5.5V
60
40
V+ = 3.3V
20
60
-40°C
25°C
50
40
30
85°C
20
125°C
10
V+ = 2.2V
0
0
1
2
4
5
0
0
6
1
1
Output Voltage (V)
Figure 26. Output Short Circuit Current vs Output Voltage
1e2
20
HL -IN
0
0
V+ = 3.3V
CL = 10 pF
HL +IN
LH -IN
RISE
TA = 25°C
1e1
LH +IN
Rise and Fall Time (PA)
Propagation Delay (és)
40
10
3
Output Voltage (V)
Figure 25. Output Short Circuit Current vs Output Voltage
30
2
1
1e-1
FALL
1e-2
1e-3
1e-1
10 20 30 40 50 60 70 80 90 100
1
1e1
1e2
1e3
Input Overdrive (mV)
Output Pull-Up Resistor (k:)
Figure 27. Propagation Delay vs Input Overdrive
VOUT when
+IN = V+
-IN = VIN
2V/DIV
DC
tPDHL1
tPDLH1
tPDLH2
tPDHL2
VIN
10 mV/DIV
AC
10
RL = 10 k:
CL = 10 pF
Output Leakage Current (pA)
VOUT when
+IN = VIN
-IN = GND
2V/DIV
DC
Figure 28. Rise and Fall Times vs Output Pullup Resistor
V+ = 3.3V
25°C
1
-40°C
0.1
0.01
10 mV OF OVERDRIVE
0
4 Ps/DIV
1
2
4
5
6
Output Voltage (V)
Figure 29. Propagation Delay
10
Figure 30. Output Leakage Current vs Output Voltage
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
Output Leakage Current (nA)
125°C
V+ = 3.3 V
10
1
85°C
0.1
0.01
0
1
2
4
5
6
Output Voltage (V)
Figure 31. Output Leakage Current vs Output Voltage
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7 Detailed Description
7.1 Overview
The LMV7231 is Hex Window Comparator which can be used to monitor power supply voltages and other critical
system voltage levels.
The LMV7231 contains 6 identical window comparators where the upper and lower trip points are set through
external resistor dividers. Each input of the comparator is compared to a internal 1.5% accurate 400-mV
reference voltage (VREF).
The 6 window comparator outputs (CO1-CO6) signal an undervoltage or overvoltage event for each power
supply input. The COPOL pin sets the inside or outside of the window indication.
A combined OR'ed output (AO) is also provided to signal when any of the power supply inputs have an
overvoltage or undervoltage event. AOSEL sets the logic polarity to create a power-good or error signal.
7.2 Functional Block Diagram
COPOL
*
+ IN1
+
B
-
*
+
-
+ IN2
+
A
*
OV1
-IN2
-
+IN3
+
CO3
*
B
*
UV2
+
CO2
*
Ref
- IN1
CO1
*
UV1
CO4
*
*
A
OV 2
B
UV 3
A
OV 3
CO5
*
*
CO6
*
+
-IN3
OV1
-
AOSEL
OV 2
+IN4
+
B
UV4
-
OV 3
OV 4
OV 5
OV6
+
- IN4
-
+IN5
+
A
AO
OV4
*
UV1
UV2
B
UV5
UV3
* Open
Drain
UV4
-
UV5
+
-IN5
-
+IN6
+
A
OV 5
B
UV6
A
OV6
UV6
+
- IN6
12
-
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7.3 Feature Description
The LMV7231 Hex Window Comparator with 1.5% precision can accurately monitor up to 6 power rails or
batteries at one time. The input and output voltages of the device can exceed the supply voltage, V+, of the
comparator, and can be up to the maximum ratings listed in the Absolute Maximum Ratings without causing
damage or performance degradation. The typical microcontroller input pin with crowbar diode ESD protection
circuitry does not allow the input to go above V+, and thus its usefulness is limited in power supply supervision
applications.
7.3.1 Input and Output Voltage Range Above V+
The supply independent inputs of the window comparator blocks allow the LMV7231 to be tolerant of system
faults. For example, if the power is suddenly removed from the LMV7231 due to a system malfunction while a
voltage still exists on the input, it is not an issue as long as the monitored input voltage does not exceed the
absolute maximum ratings. Another example where this feature comes in handy is a battery-sense application
such as the one in Figure 32. The boards may be sitting on the shelf unbiased with V+ grounded, and yet have a
fully charged battery onboard. If the comparator measuring the battery had crowbar diodes, the diode from –IN to
V+ would turn on, sourcing current from the battery, eventually draining the battery. However, when using the
LMV7231 no current, except the low input bias current of the device, flows into the chip, and the battery charge
is preserved.
V+ = 3.3V
R1
499k
R2
1M
+
-
VBATT
VOUT
R3
3.01k
Figure 32. Battery-Sense Application
The output pin voltages of the device can also exceed the supply voltage, V+, of the comparator. This provides
extra flexibility and enables designs which pull up the outputs to higher voltage levels to meet system
requirements. For example, it is possible to run the LMV7231 at its minimum operating voltage, V+ = 2.2 V, but
to bias a blue LED, pull up the output listed in the Absolute Maximum Ratings, with a forward voltage of VF = 4 V.
In a power supply supervision application, the hardwired LMV7231 is a sound solution compared to the
microcontroller with software alternative for several reasons. First, start-up is faster. During start-up, code loading
time, oscillator ramp time, and reset time do not need to be accounted for. Second, operation is quick. The
LMV7231 has a maximum propagation delay and is not affected by sampling and conversion delays related to
reading data, calculating data, and setting flags. Third, the device has less overhead. The LMV7231 does not
require an expensive power-consuming microcontroller nor is it dependent on controller code which could get
damaged or crash.
7.4 Device Functional Modes
7.4.1 +IN1 through +IN6 Input Pins
These inputs set the upper threshold voltage of the channel window comparator. The input voltage is compared
to the internal 400-mV reference. These inputs are capable of input voltages up to the Absolute Maximum
Ratings (6 V), independent of the V+ supply voltage.
7.4.2 –IN1 through –IN6 Input Pins
These inputs set the lower threshold voltage of the channel window comparator. The input voltage is compared
to the internal 400-mV reference. These inputs are capable of input voltages up to the Absolute Maximum
Ratings (6 V), independent of the V+ supply voltage.
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Device Functional Modes (continued)
7.4.3 CO1 through C06 Output Pins
These are the open-drain outputs of the individual comparators. A pullup resistor is required or several outputs
may be logic OR'ed together with a common pullup resistor. The polarity is determined by the COPOL input pin
setting.
7.4.4 COPOL Input Pin
The state of this comparator output polarity select input pin determines whether the CO1-CO6 pins are activehigh or active-low. When tied LOW, the CO1-CO6 outputs go LOW to indicate an out-of-window comparison.
When tied HIGH, the outputs go LOW to indicate a within-window comparison.
7.4.5 AO Output Pin
This output is the AND'ed combination of either the overvoltage comparator outputs or the undervoltage
comparator outputs and is controlled by the state of the AOSEL. The AO pin is active-low.
7.4.6 AOSEL Input Pin
The state of this AND output level select pin determines whether the AO pin is active on an overvoltage or
undervoltage event. When tied LOW the AO output is active upon an overvoltage event.
7.4.7 Three-Resistor Voltage Divider Selection
The LMV7231 trip points can be set by external resistor dividers as shown in Figure 33.
V+
VIN
0.1 PF
COPOL
R1
Ch. 1
+
-
+IN1
*
*
R2
10k
CO1
VOUT
+
-
-IN1
R3
REF
COPOL
OV1 UV1
Ch. 6
+IN6
CO6
-IN6
REF
REF
REF
LMV7231
OV6 UV6
AOSEL
OV1
OV2
OV3
OV4
OV5
OV6
AO
*
UV1
UV2
UV3
UV4
UV5
UV6
GND
10k
* Open
Drain
RESERVED
Figure 33. External Resistor Dividers
Each trip point, overvoltage (VOV) and undervoltage (VUV), can be optimized for a falling supply (VTHF), or a rising
supply (VTHR).
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Device Functional Modes (continued)
Therefore, there are 22 = 4 different optimization cases:
1. Exiting the voltage detection window (Figure 34)
2. Rising into and out of the window (Figure 35)
3. Entering the window (Figure 36)
4. Falling into and out of the window (Figure 37)
VUV
VUV
VOV
VOV
VOUT
VOUT
VIN
VIN
R3 set
R3 set
R2 = R3((VTHF/VTHR)VOV/VUV ± 1)
R2 = R3(VOV/VUV ± 1)
R1 = R3((1/VTHR)VOV - (VTHF/VTHR)VOV/VUV)
R1 = R3((1/VTHR)VOV - VOV/VUV)
Ex. VOV = 3.465 V, V UV = 3.135 V, that is, V RANGE = 3.3 V ± 5%
Ex. VOV = 3.465 V, V UV = 3.135 V, that is, V RANGE = 3.3 V ± 5%
R3 set to 10 kΩ
R3 set to 10 kΩ
R2 = 10k((0.394/0.4)3.465/3.135 ± 1) ≈ 887 Ω
R2 = 10k((3.465/3.135) ± 1) ≈ 1.05 kΩ
R1 = 10k((1/0.4)3.465 - (0.394/0.4)3.465/3.135) ≈ 75 kΩ
R1 = 10k((1/0.4)3.465 ± 3.465/3.135) ≈ 75 kΩ
Figure 34. Exiting the Voltage Detection Window
VUV
Figure 35. Rising into and out of the Voltage
Detection Window
VOV
VUV
VOUT
VOV
VOUT
VIN
VIN
R3 set
R3 set
R2 = R3((VTHR/VTHF)VOV/VUV ± 1)
R2 = R3(VOV/VUV ± 1)
R1 = R3((1/VTHF)VOV - (VTHR/VTHF)VOV/VUV)
R1 = R3((1/VTHF)VOV - VOV/VUV)
Ex. VOV = 3.465 V, VUV = 3.135 V, that is, V RANGE = 3.3 V ± 5%
Ex. VOV = 3.465 V, VUV = 3.135 V, that is, V RANGE = 3.3 V ± 5%
R3 set to 10 kΩ
R3 set to 10 kΩ
R2 = 10k((0.4/0.394)3.465/3.135 ± 1) ≈ 1.21 kΩ
R2 = 10k((3.465/3.135) ± 1) ≈ 1.05 kΩ
R1 = 10k((1/0.394)3.465 - (0.4/0.394)3.465/3.135) ≈ 76.8 kΩ
R1 = 10k((1/0.394)3.465 ± 3.465/3.135) ≈ 76.8 kΩ
Figure 36. Entering the Voltage Detection Window
Figure 37. Falling into and out of the Voltage
Detection Window
NOTE
For each case, each trip point can be optimized for either a rising or falling signal, but not
both.
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Device Functional Modes (continued)
The governing equations make it such that if the same resistor, R3, and overvoltage-to-undervoltage ratio,
VOV/VUV, is used across the channels, the same nominal current travels through the resistor ladder. As a result,
R2 is also the same across all channels, and only R1 needs to change to set voltage detection window
maximizing reuse of resistor values and minimizing design complexity.
Select the R3 resistor value to be below 100 kΩ so the resistor current through the divider ladder is much greater
than the LMV7231 bias current (15 nA worst case, 50 pA typical). If the current traveling through the resistor
divider is on the same magnitude of the LMV7231 IBIAS, the IBIAS current creates an error in the circuit and
causes trip voltage shifts. The greatest error due to IBIAS is caused when that current passes through the greatest
equivalent resistance, REQ = R1‖(R2+R3), which is detected by the positive input of the window comparator,
+IN.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV7231 is specified for operation from 2.2 V to 5.5 V. Some of the specifications apply from –10°C to
+70°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in the Typical Characteristics and the 3.3-V Electrical Characteristics.
8.2 Typical Application
Figure 38 shows a typical power supply supervision circuit using the LMV7231 and the efficient, easy to use
LM25007 step-down switching regulator.
Input = 9V-42V
R1
115k
VIN
C1
C3
1.0 µF
0.1 µF
VCC
C5
LM25007
ON/OFF
C4
0.1µF
BST
0.01µF L1 100 µH
R6
C6
121k
2200
pF
SW
RON/SD
D1
RCL
R5
200k
VOUT = 5V
R2
3k
C7
0.01 µF
FB
C2
22 µF
RTN
R3
3k
V+ = 3.3V
C8
COPOL
V+
Controller
(FPGA)
0.1 µF
R7
1.15k
Ch. 1
R10
10k
+
-
*
*
CO1
+IN1
R8
10
+
V+
R11
10k
COPOL
UV1 OV1
REF
UV6 OV6
REF
CO6
C9
*optional
-IN1
R9
95.3
Ch. 6
+IN6
-IN6
AOSEL
OV1
OV2
OV3
OV4
OV5
OV6
V+ R12
10k
AO
*
UV1
UV2
UV3
UV4
UV5
UV6
* Open
Drain
RESERVED
REF
REF
LMV7231
GND
Figure 38. Power Supply Supervision
8.2.1 Design Requirements
Table 1 describes the requested design parameters.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Logic Supply Voltage
3.3 V
Monitored Voltage
5V
Monitored Voltage Tolerance
Window
±5% (4.75 V to 5.25 V)
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8.2.2 Detailed Design Procedure
The regulators output voltage is set to 5 V, according to the LM25007 data sheet, SNVS401.
VOUT = 2.5 × (R2 + R3) / R3
VOUT = 2.5 × (3 kΩ + 3 kΩ) / 3 kΩ = 5 V
(1)
(2)
Resistor R6 and capacitors C6, C7 are utilized to minimize output ripple voltage per the AN-1453 LM25007
Evaluation Board, (SNVA152).
The comparator voltage window is set to 5 V ±5%. This requires input voltages of 420 mV and 380 mV, which
calculates to R7 = 1.15 kΩ , R8 = 10 Ω, R9 = 95.3 Ω. See the Three-Resistor Voltage Divider Selection section
for details on how to set the comparator voltage window.
With the components selected, the output ripple voltage on the LM25007 is approximately 30 to 35 mV and is
reduced to about 4 mV at the comparator input, +IN1, by the resistor divider. This ripple voltage can be reduced
multiple ways. First, user can operate the device in continuous conduction mode rather than discontinuous
conduction mode. To do this increase the load current of the device (see SNVS401 for more details). However,
the power rating of the resistors in the resistor ladder must not be exceeded. Second, ripple can be reduced
further with a bypass capacitor, C9, at the resistor divider. If desired, select a 1-µF capacitor to achieve less than
3-mV ripple at +IN1. However, there is a trade-off that adding capacitance at this node lowers the system
response time.
8.2.3 Application Curve
Figure 39 shows the results of sweeping the regulator output voltage through the undervoltage and overvoltage
thresholds. COPOL is set LOW so that the output goes LOW while the regulator voltage is within the ±5%
thresholds.
6.0
COPOL = LOW
5.5
Volts
+5% VOV
5.0
-5% VUV
CO1 Output
Regulator Output
4.5
4.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (Seconds)
C001
Figure 39. Power Supply Supervisor Thresholds
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9 Power Supply Recommendations
Bypass the supply pin, V+, with a 0.1-μF ceramic capacitor placed close to the V+ pin. If transients with rise or
fall times of hundreds of μs and magnitudes of hundreds of mV are expected on the power supply line, an RC
lowpass filter network as shown in Figure 40 is recommended for additional bypassing. If no such bypass
network is used power supply transients can cause the internal voltage reference of the comparator to
temporarily shift potentially resulting in a brief incorrect comparator output. For example, if an RC network with
100-Ω resistance and 10-μF capacitance (1.1-ms rise time) is used the voltage reference temporarily shifts the
amount, VTH power supply sensitivity (VTHPSS), specified in the 3.3-V Electrical Characteristics table.
R1
VSUPPLY 100
C1
10 PF
C2
0.1 PF
V+
LMV7231
Figure 40. Power Supply Bypassing
10 Layout
10.1 Layout Guidelines
Proper grounding and the use of a ground plane helps to ensure the specified performance of the LMV7231.
Minimizing trace lengths, reducing unwanted parasitic capacitance, and using surface-mount components also
helps. Comparators are very sensitive to input noise.
1. Use a printed-circuit-board with a good, unbroken low-inductance ground plane.
2. Place a decoupling capacitor (0.1-µF ceramic surface mount capacitor) as close to V+ pin as possible.
3. On the inputs and the outputs, keep lead lengths and the divider resistors as short possible to avoid noise
pick-up.
The DAP pad is connected to the bottom of the die and is not designed to carry current. The DAP thermal pad
must be connected directly to the GND pin to avoid noise and possible voltage gradients. The primary grounding
pin is the GND pin.
10.2 Layout Example
Figure 41. Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV7231 Evaluation Board, http://www.ti.com/tool/lmv7231eval
11.2 Documentation Support
11.2.1 Related Documentation
• LMV7231 Evaluation Board Manual, SNOU008
• LM25007 42-V, 0.5-A Step-Down Switching Regulator, SNVS401
• AN-1453 LM25007 Evaluation Board, SNVA152
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMV7231SQ/NOPB
ACTIVE
WQFN
RTW
24
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L7231SQ
LMV7231SQE/NOPB
ACTIVE
WQFN
RTW
24
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L7231SQ
LMV7231SQX/NOPB
ACTIVE
WQFN
RTW
24
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L7231SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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