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LMV7239-Q1
SNOSD85 – APRIL 2018
LMV7239-Q1 75-ns, Ultra Low Power, Low Voltage, Rail-to-Rail Input Comparator With
Open-Drain and Push-Pull Output
1 Features
3 Description
•
•
The LMV7239-Q1 is a ultra low power, low voltage,
75-ns comparator. It is ensured to operate over the
full supply voltage range of 2.7 V to 5.5 V. This
device achieves a 75-ns propagation delay while
consuming only 65 µA of supply current at 5 V.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C5 for
the DBV Package
VS = 5 V, TA = 25°C (Typical Values Unless
Otherwise Specified)
Propagation Delay: 75 ns
Low supply Current: 65 µA
Rail-to-Rail Input
Open Drain and Push-Pull Output
Ideal for 2.7-V and 5-V, Single-Supply
Applications
Available in Space-Saving Packages:
– 5-Pin SOT-23
– 5-Pin SC70
2 Applications
•
•
•
•
•
•
The LMV7239-Q1 has a greater than rail-to-rail
common-mode voltage range. The input common
mode voltage range extends 200 mV below ground
and 200 mV above supply, allowing both ground and
supply sensing.
The LMV7239-Q1 features a push-pull output stage.
This feature allows operation without the need of an
external pullup resistor.
The LMV7239-Q1 is available in the 5-pin SC70 and
5-pin SOT-23 packages, which are ideal for systems
where small size and low power is critical.
Device Information(1)
PART NUMBER
LMV7239-Q1
Supply Current vs. Supply Voltage
SC70 (5)
2.00 mm × 1.25 mm
Propagation Delay vs. Overdrive
PROPAGATION DELAY (ns)
SUPPLY CURRENT ( A)
2.90 mm × 1.60 mm
90
-40°C
25°C
85°C
125°C
100
BODY SIZE (NOM)
SOT-23 (5)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Portable and Battery-Powered Systems
Set Top Boxes
High-Speed Differential Line Receiver
Window Comparators
Zero-Crossing Detectors
High-Speed Sampling Circuits
120
PACKAGES
80
60
40
20
0
VS= 5V
CLOAD=15pF
85
Rising Edge
80
75
Falling Edge
70
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
20
40
60
80
INPUT OVERDRIVE (mV)
100
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV7239-Q1
SNOSD85 – APRIL 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics, 2.7 V ...............................
Electrical Characteristics, 5 V ..................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ................................................ 15
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
April 2018
2
REVISION
NOTES
*
Initial release. Moved the automotive device
from the SNOS532 to a standalone data sheet
and updated the input offset voltage parameter
in the Electrical Characteristics, 2.7 V and
Electrical Characteristics, 5 V tables
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5 Pin Configuration and Functions
DBV and DGK Package
5-Pin SC70 and SOT-23
Top View
VOUT
1
V±
2
Non-Inverting
Input
3
5
V+
4
Inverting
Input
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
VOUT
O
Output
2
V-
P
Negative Supply
3
IN+
I
Noninverting Input
4
IN-
I
Inverting Input
5
V+
P
Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
Differential Input Voltage
MAX
UNIT
± Supply Voltage
V
Output Short Circuit Duration
See
Supply Voltage (V+ - V−)
(2)
6
V
SOLDERING INFORMATION
Infrared or Convection (20 sec)
235
°C
Wave Soldering (10 sec)
260 (lead temp)
°C
Voltage at Input/Output Pins
(V+) +0.3, (V−) −0.3
V
±10
mA
150
°C
150
°C
Current at Input Pin
(3)
Storage Temperature, Tstg
–65
Junction Temperature,TJ
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely
affect reliability.
Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011 (1)
DBV package only
±750
Machine model (MM)
(1)
UNIT
±1000
V
±100
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
MIN
Supply Voltages (V+ - V−)
Temperature Range
(1)
(1)
MAX
UNIT
2.7
5.5
V
–40
125
°C
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
LMV7239-Q1
THERMAL METRIC
RθJA
(1)
4
(1)
Junction-to-ambient thermal resistance
DGK (SC70)
DBV (SOT-23)
5 PINS
5 PINS
478
265
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics, 2.7 V
Unless otherwise specified, all limits ensured for TA = 25°C, VCM = V+/2, V+ = 2.7 V, V− = 0 V−.
PARAMETER
TEST CONDITIONS
VOS
Input Offset Voltage
IB
Input Bias Current
IOS
Input Offset Current
CMRR
Common-Mode Rejection
Ratio
0 V < VCM < 2.7 V (3)
PSRR
Power Supply Rejection Ratio
V+ = 2.7 V to 5 V
VCM
Input Common-Mode Voltage
Range
At temp extremes
IS
tPD
Output Swing Low
Supply Current
Propagation Delay
TYP (2)
MAX (1)
–6
±0.8
+6
–8
30
400
600
5
At temp extremes
CMRR > 50 dB
200
400
52
62
65
85
V− −0.1 −0.2 to 2.9
At temp extremes
UNIT
mV
+8
At temp extremes
IL = −4 mA,
VID = −500 mV
VO
MIN (1)
V−
At temp extremes
dB
V+ +0.1
15
No load
52
At temp extremes
V
350
450
IL = −0.4 mA,
VID = −500 mV
nA
dB
V+
230
nA
85
100
mV
µA
Overdrive = 20 mV
CLOAD = 15 pF
96
ns
Overdrive = 50 mV
CLOAD = 15 pF
87
ns
Overdrive = 100 mV
CLOAD = 15 pF
85
ns
tr
Output Rise Time
LMV7239/LMV7239Q
10% to 90%
1.7
ns
tf
Output Fall Time
90% to 10%
1.7
ns
(1)
(2)
(3)
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
CMRR is not linear over the common mode range. Limits are guaranteed over the worst case from 0 to VCC/2 or VCC/2 to VCC.
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6.6 Electrical Characteristics, 5 V
Unless otherwise specified, all limits ensured for TA = 25°C, VCM = V+/2, V+ = 5 V, V− = 0 V.
PARAMETER
TEST CONDITIONS
VOS
Input Offset Voltage
IB
Input Bias Current
IOS
Input Offset Current
CMRR
Common-Mode Rejection
Ratio
0 V < VCM < 5 V
PSRR
Power Supply Rejection Ratio
V+ = 2.7 V to 5 V
VCM
Input Common-Mode Voltage
Range
tPD
tf
(1)
(2)
6
Propagation Delay
Output Fall Time
±1
+6
+8
30
400
At temp extremes
600
5
200
At temp extremes
400
52
85
V −0.1
−0.2 to
5.2
CMRR > 50dB
At temp extremes
No load
V−
UNIT
mV
nA
nA
dB
67
65
−
Output Swing Low
Supply Current
–6
MAX (1)
–8
dB
+
V +0.1
V
V+
230
At temp extremes
IL = −0.4 mA,
VID = −500 mV
IS
TYP (2)
At temp extremes
IL = −4 mA,
VID = −500 mV
VO
MIN (1)
350
450
mV
10
65
At temp extremes
95
110
µA
Overdrive = 20 mV
CLOAD = 15 pF
89
ns
Overdrive = 50 mV
CLOAD = 15 pF
82
ns
Overdrive = 100 mV
CLOAD = 15 pF
75
ns
90% to 10%
1.2
ns
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
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6.7 Typical Characteristics
(Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C).
120
100
SUPPLY CURRENT ( A)
100
-40°C
25°C
85°C
125°C
VS = 5V
10
ISOURCE (mA)
80
60
1
40
20
.1
.01
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
Figure 1. Supply Current vs. Supply Voltage
10
1
Figure 2. Sourcing Current vs. Output Voltage
100
100
VS = 2.7V
VS = 5V
10
10
ISINK (mA)
ISOURCE (mA)
.1
OUTPUT VOLTAGE REFERENCED TO V+ (V)
1
1
.1
.01
.1
1
.1
.01
10
OUTPUT VOLTAGE REFERENCED TO V+ (V)
.1
1
10
OUTPUT VOLTAGE REFERENCED TO GND (V)
Figure 3. Sourcing Current vs. Output Voltage
Figure 4. Sinking Current vs. Output Voltage
50
100
40
INPUT BIAS CURRENT (nA)
VS = 2.7V
ISINK (mA)
10
1
VS = 5V
30
IBIAS+
20
10
0
-10
IBIAS-
-20
-30
-40
.1
.01
.1
1
10
-50
-0.2
OUTPUT VOLTAGE REFERENCED TO GND (V)
1
2
3
4
5
VIN (V)
Figure 5. Sinking Current vs. Output Voltage
Figure 6. Input Bias Current vs. Input Voltage
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Typical Characteristics (continued)
(Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C).
160
VS = 2.7V
50
40
30
PROPAGATION DELAY (ns)
INPUT BIAS CURRENT (nA)
70
60
IBIAS+
20
10
0
-10
-20
-30
-40
IBIAS-
140
130
Falling Edge
120
110
100
90
-50
-60
Rising Edge
80
0
2
1
2.7
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
VIN (V)
Figure 7. Input Bias Current vs. Input Voltage
Figure 8. Propagation Delay vs. Temperature
140
106
VS=5V
VOD=20mV
CLOAD=15pF
130
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
VS=2.7V
VOD=20mV
CLOAD=15pF
150
120
Falling Edge
110
100
90
VS= 2.7V
VOD=20mV
104
102
Falling Edge
100
98
96
Rising Edge
Rising Edge
80
94
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 9. Propagation Delay vs. Temperature
0
100
VS= 5V
VOD=20mV
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
100
Figure 10. Propagation Delay vs. Capacitive Load
96
94
Falling Edge
92
90
VS= 2.7V
CLOAD=15pF
95
Rising Edge
90
85
Rising Edge
Falling Edge
88
80
0
20
40
60
80
CAPACITANCE (pF)
100
Figure 11. Propagation Delay vs. Capacitive Load
8
20
40
60
80
CAPACITANCE (pF)
20
30 40 50 60 70 80 90 100
INPUT OVERDRIVE (mV)
Figure 12. Propagation Delay vs. Input Overdrive
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Typical Characteristics (continued)
(Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C).
120
VS= 5V
CLOAD=15pF
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
90
85
Rising Edge
80
75
Falling Edge
VS= 2.7V
VOD=20mV
CLOAD=15pF
115
110
105
100
70
95
90
85
Rising Edge
Falling Edge
80
20
40
60
80
INPUT OVERDRIVE (mV)
100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
INPUT COMMON MODE VOLTAGE (V)
Figure 13. Propagation Delay vs. Input Overdrive
Figure 14. Propagation Delay vs. Common-Mode Voltage
PROPAGATION DELAY (ns)
110
VS= 5V
VOD=20mV
CLOAD=15pF
100
Falling Edge
Rising Edge
90
80
0
1
2
3
4
5
INPUT COMMON MODE VOLTAGE (V)
Figure 15. Propagation Delay vs. Common-Mode Voltage
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7 Detailed Description
7.1 Overview
The LMV7239-Q1 is an ultra low power, low voltage, 75-ns comparator. They are ensured to operate over the full
supply voltage range of 2.7 V to 5.5 V. These devices achieve a 75-ns propagation delay while consuming only
65 µA of supply current at 5 V.
The LMV7239-Q1 has a greater than rail-to-rail common-mode voltage range. The input common-mode voltage
range extends 200 mV below ground and 200 mV above supply, allowing both ground and supply sensing.
7.2 Functional Block Diagram
Figure 16. Simplified Schematic
7.3 Feature Description
7.3.1 Input Stage
The LMV7239-Q1 is a rail-to-rail input and output. The typical input common-mode voltage range of −0.2 V below
the ground to 0.2 V above the supply. The LMV7239-Q1 uses a complimentary PNP and NPN input stage in
which the PNP stage senses common-mode voltage near V− and the NPN stage senses common-mode voltage
near V+. If either of the input signals falls below the negative common mode limit, the parasitic PN junction
formed by the substrate and the base of the PNP will turn on resulting in an increase of input bias current.
If one of the inputs goes above the positive common mode limit, the output will still maintain the correct logic
level as long as the other input stays within the common mode range. However, the propagation delay will
increase. When both inputs are outside the common-mode voltage range, current saturation occurs in the input
stage, and the output becomes unpredictable.
The propagation delay does not increase significantly with large differential input voltages. However, large
differential voltages greater than the supply voltage should be avoided to prevent damage to the input stage.
7.3.2 Output Stage: LMV7239-Q1
The LMV7239-Q1 has a push-pull output. When the output switches, there is a low resistance path between VCC
and ground, causing high output sinking or sourcing current during the transition.
10
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Feature Description (continued)
Figure 17. LMV7239-Q1 Push-Pull Output Stage
7.4 Device Functional Modes
7.4.1 Capacitive and Resistive Loads
The propagation delay is not affected by capacitive loads at the output of the LPV7239 or LMV7239-Q1.
However, resistive loads slightly effect the propagation delay on the falling edge depending on the load
resistance value.
7.4.2 Noise
Most comparators have rather low gain. This allows the output to spend time between high and low when the
input signal changes slowly. The result is the output may oscillate between high and low when the differential
input is near zero. The high gain of this comparator eliminates this problem. Less than 1 μV of change on the
input will drive the output from one rail to the other rail. If the input signal is noisy, the output cannot ignore the
noise unless some hysteresis is provided by positive feedback. (See Hysteresis.)
7.4.3 Hysteresis
To improve propagation delay when low overdrive is needed hysteresis can be added.
7.4.3.1 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage
V+ of the comparator as shown in Figure 18. When VIN at the inverting input is less than VA, the voltage at the
noninverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as
high as V+). The three network resistors can be represented as R1//R3 in series with R2.
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Device Functional Modes (continued)
Figure 18. Inverting Comparator With Hysteresis
The lower input trip voltage VA1 is defined as:
VA1 = VCCR2 / [(R1 // R3) + R2)]
(1)
When VIN is greater than VA, the output voltage is low or very close to ground. In this case the three network
resistors can be presented as R2 // R3 in series with R1.
The upper trip voltage VA2 is defined as:
VA2 = VCC (R2 // R3) / [(R1 ) + (R2 // R3)]
(2)
The total hysteresis provided by the network is defined as ΔVA = VA1 - VA2.
VCCR1R2
'VA
R1R2 R1R3 R2R3
(3)
7.4.3.2 Non-Inverting Comparator With Hysteresis
A noninverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input. When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up
to VIN1 where VIN1 is calculated by:
VREF (R1 R2 )
'VIN1
R2
(4)
As soon as VO switches to VCC, VA steps to a value greater than VREF which is given by:
(VCC VIN1 )R1
VA VIN
R1 R2
(5)
To make the comparator switch back to its low state, VIN must equal VREF before VA will again equal VREF. VIN2
can be calculated by:
12
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Device Functional Modes (continued)
VIN2
VREF (R1 R2 ) VCC R1
R2
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2.
ΔVIN = VCCR1 / R2
(7)
VCC
-
VREF
VA
VIN
VO
+
R1
RL
R2
Figure 19. Noninverting Comparator With Hysteresis
Figure 20. Noninverting Comparator Thresholds
7.4.4 Zero Crossing Detector
In a zero crossing detector circuit, the inverting input is connected to ground and the noninverting input is
connected to a 100 mVPP AC signal. As the signal at the noninverting input crosses 0V, the comparator’s output
changes state.
Figure 21. Simple Zero Crossing Detector
7.4.4.1 Zero Crossing Detector With Hysteresis
To improve switching times and centering the input threshold to ground a small amount of positive feedback is
added to the circuit. Voltage divider R4 and R5 establishes a reference voltage, V1, at the positive input. By
making the series resistance, R1 plus R2 equal to R5, the switching condition, V1 = V2, will be satisfied when VIN
= 0.
The positive feedback resistor, R6, is made very large with respect to R5 || R6 = 2000 R5). The resultant
hysteresis established by this network is very small (ΔV1 < 10 mV) but it is sufficient to insure rapid output
voltage transitions.
Diode D1 is used to ensure that the inverting input terminal of the comparator never goes below approximately
−100 mV. As the input terminal goes negative, D1 will forward bias, clamping the node between R1 and R2 to
approximately −700 mV. This sets up a voltage divider with R2 and R3 preventing V2 from going below ground.
The maximum negative input overdrive is limited by the current handling ability of D1.
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Device Functional Modes (continued)
VCC
R3
R1
R4
R2
-
VIN
V2
D1
VO
V1
+
R6
R5
Figure 22. Zero Crossing Detector With Hysteresis
7.4.5 Threshold Detector
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on
the noninverting input passes the VREF threshold, the comparator’s output changes state. It is important to use a
stable reference voltage to ensure a consistent switching point.
Figure 23. Threshold Detector
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV7239-Q1 is a single supply comparator with 75 ns of propagation delay and only 65 µA of supply
current.
8.2 Typical Applications
8.2.1 Square Wave Oscillator
R4
C1
VC
VO
+
R1
+
VA
R3
V
+
R2
V
0
Figure 24. Square Wave Oscillator
8.2.1.1 Design Requirements
A typical application for a comparator is as a square wave oscillator. The circuit in Figure 24 generates a square
wave whose period is set by the RC time constant of the capacitor C1 and resistor R4.
8.2.1.2 Detailed Design Procedure
The maximum frequency is limited by the large signal propagation delay of the comparator and by the capacitive
loading at the output, which limits the output slew rate.
Figure 25. Square Wave Oscillator Timing Thresholds
Consider the output of Figure 24 to be high to analyze the circuit. That implies that the inverted input (VC) is
lower than the noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC
increases until it is equal to the noninverting input. The value of VA at this point is:
VCC ˜ R2
VA1
R2 R1 R R3
(8)
If R1 = R2 = R3, then V A1 = 2 Vcc/3
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Typical Applications (continued)
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is:
VCC (R2 R R3 )
VA2
R1 (R2 R R3 )
(9)
If R1 = R2 = R3, then VA2 = VCC/3.
The capacitor C1 now discharges through R4, and the voltage VC decreases until it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1·ln2. Hence the formula for the frequency is:
F = 1/(2·R4·C1·ln2)
(10)
The LMV7239 should be used for a symmetrical output. The LMV7235 will require a pullup resistor on the output
to function, and will have a slightly asymmetrical output due to the reduced sourcing current.
8.2.1.3 Application Curves
Figure 26 shows the simulated results of an oscillator using the following values:
1.
2.
3.
4.
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 100 pF, CL = 20 pF
V+ = 5 V, V– = GND
CSTRAY (not shown) from Va to GND = 10 pF
6
VOUT
5
Va
VOUT (V)
4
3
2
1
Vc
0
-1
0
10
20
30
TIME (µs)
40
50
C001
Figure 26. Square Wave Oscillator Output Waveform
8.2.2 Crystal Oscillator
A simple crystal oscillator using the LMV7239-Q1 is shown in Figure 27. Resistors R1 and R2 set the bias point at
the comparator’s noninverting input. Resistors, R3 and R4 and capacitor C1 set the inverting input node at an
appropriate DC average level based on the output. The crystal’s path provides resonant positive feedback and
stable oscillation occurs. The output duty cycle for this circuit is roughly 50%, but it is affected by resistor
tolerances and to a lesser extent by the comparator
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Typical Applications (continued)
VCC
100K
Crystal
100K
VOUT
100K
0.1uF
Figure 27. Crystal Oscillator
8.2.3 Infrared (IR) Receiver
The LMV7239-Q1 can also be used as an infrared receiver. The infrared photo diode creates a current relative to
the amount of infrared light present. The current creates a voltage across RD. When this voltage level cross the
voltage applied by the voltage divider to the inverting input, the output transitions.
Figure 28. IR Receiver
8.2.4 Window Detector
V
+
R1
+
VREF2
A
OUTPUT A
B
OUTPUT B
R2
VIN
+
-
VREF1
R3
Figure 29. Window Detector
A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are
true (high) when VREF1 < VIN < VREF2
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Typical Applications (continued)
VIN
V
OUTPUT B
+
VREF2
VREF1
OUTPUT A
BOTH OUTPUTS
ARE HIGH
Figure 30. Window Detector Output Signal
The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or "within the window", where these are
defined as:
VREF1 = R3/R1+R2+R3) × V+
(11)
VREF2 = R2+R3)/R1+R2+R3) × V+
(12)
To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be
reversed to invert the logic.
Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.
9 Power Supply Recommendations
To minimize supply noise, power supplies should be decoupled by a 0.01-μF ceramic capacitor in parallel with a
10-μF capacitor.
Due to the nanosecond edges on the output transition, peak supply currents will be drawn during the time the
output is transitioning. Peak current depends on the capacitive loading on the output. The output transition can
cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power
supply to "ring" due to trace inductance and low self-resonance frequency of high ESR bypass capacitors.
Treat the LMV7239-Q1 as a high-speed device. Keep the ground paths short and place small (low ESR ceramic)
bypass capacitors directly between the V+ and V– pins.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
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10 Layout
10.1 Layout Guidelines
Proper grounding and the use of a ground plane will help to ensure the specified performance of the LMV7239Q1. Minimizing trace lengths, reducing unwanted parasitic capacitance and using surface-mount components will
also help. Comparators are very sensitive to input noise.
The LMV7239-Q1 requires a high-speed layout. Follow these layout guidelines:
1. Use printed-circuit board with a good, unbroken low-inductance ground plane.
2. Place a decoupling capacitor (0.1-µF, ceramic surface-mount capacitor) as close as possible to VCC pin.
3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from output.
4. Solder the device directly to the printed-circuit board rather than using a socket.
5. For slow moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to tPD when the source impedance is low.
6. The top-side ground plane runs between the output and inputs.
7. Ground trace from the ground pin runs under the device up to the bypass capacitor, shielding the inputs from
the outputs.
10.2 Layout Example
Figure 31. SOT-23 Board Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
11.2 Documentation Support
11.2.1 Related Documentation
A Quad of Independently Func Comparators (SNOA654)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMV7239QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
ZBMX
LMV7239QM7/NOPB
ACTIVE
SC70
DCK
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
C42
LMV7239QM7X/NOPB
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
C42
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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