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LMV7275-Q1
SNOSD09 – SEPTEMBER 2015
LMV7275-Q1 Automotive Single 1.8-V Low Power Comparator With Rail-to-Rail Input
1 Features
3 Description
•
•
The LMV7275-Q1 is a single rail-to-rail input low
power comparator, characterized at supply voltages
of 1.8 V, 2.7 V, and 5 V. It consumes as little as 9-uA
supply current per channel while achieving a 800-ns
propagation delay.
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 3: -40°C to 85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
(VS = 1.8 V, TA = 25°C, Typical Values Unless
Specified).
Single or Dual Supplies
Open Drain Output
Ultra Low Supply Current 9 µA Per Channel
Low Input Bias Current 10 nA
Low Input Offset Current 200 pA
Low Ensured VOS 4 mV
Propagation Delay 880 ns (20-mV Overdrive)
Input Common Mode Voltage Range 0.1 V
Beyond Rails
The LMV7275-Q1 is available in a SC-70 package.
With these tiny packages, the PCB area can be
significantly reduced. They are ideal for low voltage,
low power, and space-critical designs.
The LMV7275-Q1 features an open-drain output
stage that allows for wired-OR configurations. The
open-drain output also offers the advantage of
allowing the output to be pulled to any voltage up to
5.5 V, regardless of the supply voltage of the
LMV7275-Q1, which is useful for level-shifting
applications.
The LMV7275-Q1 is built with Texas Instruments'
advance submicron silicon-gate BiCMOS process. It
has bipolar inputs for improved noise performance,
and CMOS outputs for lowest negative output swing.
2 Applications
•
•
•
•
Device Information(1)
PART NUMBER
Wearable Devices
Mobile Phones and Tablets
Battery-Powered Electronics
General Purpose Low Voltage Applications
VTH+
Low Supply Current
10
VIN
VTH+
RPULLUP
VTH-
+
VOUT
t
VOUT
VIN
VS
1.25 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VDIGITAL
+
VTH-
SUPPLY CURRENT (PA)
VS
BODY SIZE (NOM)
SC70 (5)
LMV7275-Q1 as a Window Comparator
VDIGITAL
PACKAGE
LMV7275-Q1
9
85°C
85°C
8
25°C
7
6
-40°C
t
5
1.8
2.44
3.08
3.72
4.36
5.0
SUPPLY VOLTAGE (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV7275-Q1
SNOSD09 – SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
3
3
3
4
4
4
5
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings LMV7275-Q1 .......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
1.8-V Electrical Characteristics .................................
1.8-V AC Electrical Characteristics ...........................
2.7-V Electrical Characteristics .................................
2.7-V AC Electrical Characteristics ...........................
5-V Electrical Characteristics ....................................
5-V AC Electrical Characteristics ............................
Typical Characteristics ............................................
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
4 Revision History
2
DATE
REVISION
NOTES
September 2015
*
Initial release.
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5 Pin Configuration and Functions
DGK Package
5-Pin SC70
Top View
Pin Functions
PIN
NAME
SC70
I/O
DESCRIPTION
IN+
1
I
Non-Inverting Input
V-
2
P
Negative Supply Voltage
IN-
3
I
Inverting Input
OUT
4
O
Output
V+
5
P
Positive Supply Voltage
6 Specifications
6.1 Absolute Maximum Ratings
(1)
MIN
VIN Differential
MAX
UNIT
±Supply
Voltage
V
6
V
Supply Voltage (V+ - V−)
(V−) − 0.1
Voltage at Input/Output pins
(V+) + 0.1
V
150
°C
150
°C
Junction Temperature (2)
Storage Temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
6.2 ESD Ratings LMV7275-Q1
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
Supply Voltage
1.8
5.5
V
Temperature (1)
–40
85
°C
(1)
UNIT
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
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6.4 Thermal Information
LMV7275-Q1
THERMAL METRIC (1)
DGK (SC70)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
(2)
273.8
°C/W
Junction-to-case (top) thermal resistance
106.1
°C/W
Junction-to-board thermal resistance
54.9
°C/W
ψJT
Junction-to-top characterization parameter
3.6
°C/W
ψJB
Junction-to-board characterization parameter
54.1
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
6.5 1.8-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 1.8 V, V− = 0 V.
PARAMETER
VOS
Input Offset Voltage
TC VOS Input Offset Temperature Drift
IB
Input Bias Current
IOS
Input Offset Current
IS
Supply Current
ISC
Output Short Circuit Current
CONDITION
MIN (1)
TYP (2)
MAX (1)
0.3
4
At the temperature extremes
VCM = 0.9 V
6
(3)
UNIT
mV
20
uV/°C
10
nA
200
9
At the temperature extremes
pA
12
µA
14
Sinking, VO = 0.9 V
4
6
mA
IO = −0.5 mA
52
100
IO = −1.5 mA
166
220
VOL
Output Voltage Low
mV
VCM
Input Common-Mode Voltage
Range
CMRR > 45 dB
−0.1
CMRR
Common-Mode Rejection Ratio
0 < VCM < 1.8 V
46
78
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8 V to 5 V
55
80
dB
ILEAKAG
Output Leakage Current
VO = 1.8 V
2
pA
1.9
V
E
(1)
(2)
(3)
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
6.6 1.8-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 1.8 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V −.
PARAMETER
tPHL
tPLH
(1)
(2)
4
Propagation Delay
(High to Low)
Propagation Delay
(Low to High)
CONDITION
MIN (1)
TYP (2)
MAX (1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
880
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
570
ns
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1100
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
800
ns
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
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6.7 2.7-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V.
PARAMETER
MIN (1)
CONDITIONS
TYP (2)
MAX (1)
0.3
4
UNIT
VOS
Input Offset Voltage
TC VOS
Input Offset Temperature Drift
20
µV/°C
IB
Input Bias Current
10
nA
IOS
Input offset Current
200
IS
Supply Current
ISC
Output Short Circuit Current
At the temperature extremes
mV
6
VCM = 1.35 V (3)
pA
9
13
At the temperature extremes
µA
15
Sinking, VO = 1.35 V
10
15
IO = −0.5 mA
mA
50
70
155
220
VOL
Output Voltage Low
VCM
Input Common Voltage Range
CMRR > 45 dB
−0.1
CMRR
Common-Mode Rejection Ratio
0 < VCM < 2.7 V
46
78
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8 V to 5 V
55
80
dB
ILEAKAGE
Output Leakage Current
VO = 2.7 V
2
pA
(1)
(2)
(3)
IO = −2 mA
mV
2.8
V
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
6.8 2.7-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V −.
PARAMETER
Propagation Delay
(High to Low)
tPHL
tPLH
(1)
(2)
CONDITION
Propagation Delay
(Low to High)
MIN (1)
TYP (2)
MAX (1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1200
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
810
ns
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1300
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
860
ns
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
6.9 5-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V.
PARAMETER
VOS
Input Offset Voltage
TC VOS
Input Offset Temperature Drift
IB
Input Bias Current
IOS
Input Offset Current
IS
Supply Current
CONDITIONS
MIN (1)
TYP (2)
MAX (1)
0.3
4
At the temperature extremes
VCM = 2.5 V (3)
20
µV/°C
10
nA
200
pA
VOL
Output Voltage Low
(1)
(2)
(3)
Sinking, VO = 2.5 V
14
16
At the temperature extremes
Output Short Circuit Current
mV
6
10
ISC
UNIT
18
34
µA
mA
IO = −0.5 mA
27
70
IO = −4.0 mA
225
315
mV
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
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5-V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V.
PARAMETER
MIN (1)
CONDITIONS
TYP (2)
MAX (1)
UNIT
VCM
Input Common Voltage Range
CMRR > 45 dB
−0.1
CMRR
Common-Mode Rejection Ratio
0 < VCM < 5.0 V
46
78
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8 V to 5 V
55
80
dB
ILEAKAGE
Output Leakage Current
VO = 5 V
2
pA
5.1
V
6.10 5-V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5.0 V, V− = 0 V, VCM = 0.5 V, VO = V+/2 and RL > 1 MΩ to
V −.
PARAMETER
tPHL
tPLH
(1)
(2)
6
Propagation Delay
(High to Low)
Propagation Delay
(Low to High)
CONDITION
MIN (1)
TYP (2)
MAX (1)
UNIT
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
2100
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
1380
ns
Input Overdrive = 20 mV
Load = 50 pF//5 kΩ
1800
ns
Input Overdrive = 50 mV
Load = 50 pF//5 kΩ
1100
ns
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
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6.11 Typical Characteristics
TA = 25°C, Unless otherwise specified.
VSUPPLY = ±0.9V
800
VSUPPLY = ±1.35V
800
-40°C
-40°C
400
400
VOS (PV)
VOS (PV)
25°C
0
0
85°C
-400
-400
25°C
85°C
-800
-800
-0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9
-1.35
-0.9
-0.45
VCM (V)
VSUPPLY = ±2.5V
400
VOS (PV)
-40°C
0
-400
25°C
85°C
-800
-2.5 -2
-1
0.45
0.9
1.35
Figure 2. VOS vs. VCM
SHORT CIRCUIT OUTPUT CURRENT (mA)
Figure 1. VOS vs. VCM
800
0
VCM (V)
0
1
2 2.5
40
30
20
SINK
10
0
1.8
2.44
VCM (V)
3.08
3.72
4.36
5.0
SUPPLY VOLTAGE (V)
Figure 4. Short Circuit vs. Supply Voltage
Figure 3. VOS vs. VCM
600
10
9
85°C
85°C
VOUT - V (mV)
8
400
4mA
-
SUPPLY CURRENT (PA)
ISINK
500
25°C
7
6
-40°C
300
2mA
200
1.5mA
100
0.5mA
0
5
1.8
2.44
3.08
3.72
4.36
1.8
5.0
2.3
2.8
3.3
3.8
4.3
4.8
VSUPPLY (V)
SUPPLY VOLTAGE (V)
Figure 5. Supply Current vs. Supply Voltage
Figure 6. Output Negative Swing vs. VSUPPLY
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Typical Characteristics (continued)
TA = 25°C, Unless otherwise specified.
0.8
0.5
VSUPPLY = 1.8V
VSUPPLY = 2.7V
0.45
0.7
85°C
85°C
0.4
0.35
VOUT - V (V)
0.3
-
0.5
-
VOUT - V (V)
0.6
25°C
0.4
0.3
25°C
0.25
0.2
0.15
0.2
0.1
-40°C
-40°C
0.1
0.05
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
4
0.5
1
1.5
ISINK (mA)
Figure 7. Output Negative Swing vs. ISINK
VSUPPLY = 5V
85°C
25°C
-
-40°C
0
0
4
VCC = 1.8V
TEMP = 25°C
LOAD = 5k:50pF
4
3
50mV
20mV
2
1
0.5
1
1.5
2
2.5
3
3.5
|
|
100
0
OVERDRIVE
-100
4
0
500
1000
OUTPUT VOLTAGE
(V)
5
VCC = 1.8 V
4 TEMP = 25°C
3 LOAD = 5k:50pF
50mV
1
2500 3000
Figure 10. Propagation Delay (tPLH)
Figure 9. Output Negative Swing vs. ISINK
2
1500 2000
TIME (ns)
ISINK (mA)
OUTPUT VOLTAGE
(V)
3.5
0
0.1
20mV
5
VCC = 2.7V
TEMP = 25°C
LOAD = 5k:50pF
4
3
50mV
2
20mV
1
0
|
|
100
OVERDRIVE
0
-100
500
1000
1500
INPUT VOLTAGE
(mV)
0
INPUT VOLTAGE
(mV)
3
5
0.2
INPUT VOLTAGE
(mV)
VOUT - V (V)
0.3
8
2.5
Figure 8. Output Negative Swing vs. ISINK
OUTPUT VOLTAGE
(V)
0.4
0
2
ISINK (mA)
|
|
100
0
OVERDRIVE
-100
2000 2500 3000
0
500
1000
1500 2000 2500 3000
TIME (ns)
TIME (ns)
Figure 11. Propagation Delay (tPHL)
Figure 12. Propagation Delay (tPLH)
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Typical Characteristics (continued)
5
VCC = 2.7 V
TEMP = 25°C
LOAD = 5k:50pF
4
3
2
50mV
1
5
OUTPUT VOLTAGE
(V)
OUTPUT VOLTAGE
(V)
TA = 25°C, Unless otherwise specified.
20mV
VCC = 5.0V
TEMP = 25°C
3 LOAD = 5k:50pF
20mV
2
1
0
|
|
100
INPUT VOLTAGE
(mV)
INPUT VOLTAGE
(mV)
0
OVERDRIVE
0
-100
0
500
1000 1500
|
|
100
0
OVERDRIVE
-100
2000 2500 3000
0
500
1000 1500 2000
TIME (ns)
Figure 14. Propagation Delay (tPLH)
5
8
VCC = 5.0 V
4
TEMP = 25°C
3 LOAD = 5k:50pF
7
VS = 5V
6
2
50mV
1
0
tPHL (PS)
OUTPUT VOLTAGE
(V)
2500 3000
TIME (ns)
Figure 13. Propagation Delay (tPHL)
INPUT VOLTAGE
(mV)
50mV
4
20mV
|
|
100
OVERDRIVE
5
4
VS = 2.7V
3
2
0
1
-100
VS = 1.8V
0
0
500
1000 1500
2000 2500 3000
0
10
TIME (ns)
100
1000
OVERDRIVE (mV)
Figure 15. Propagation Delay (tPHL)
Figure 16. tPHL vs. Overdrive
5
VS = 5V
4.5
4
tPLH (PS)
3.5
3
2.5
VS = 2.7V
2
1.5
1
VS = 1.8V
0.5
0
1
10
100
1000
OVERDRIVE (mV)
Figure 17. tPLH vs. Overdrive
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7 Detailed Description
7.1 Overview
A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 18, the comparator
compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output transistor turns
on and pulls the output to V-, and thus the output (VO) goes low.
However, if VIN is greater than VREF, the output transistor turns off and the voltage (VO) is pulled high by the
external pull-up resistor.
VOLTS
VO
VREF
TIME
VIN
Figure 18. Basic Comparator
7.2 Functional Block Diagram
V
VREF
+
VO
VIN
+
V
-
7.3 Feature Description
7.3.1 Rail-to-Rail Input Stage
The LMV7275-Q1 has an input common mode voltage range (VCM) of −0.1V below the V− to 0.1 V above V+.
This is achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN
pair is on and the PNP pair is off. When the VCM is near V−, the NPN pair is off and the PNP pair is on. The
crossover point between the NPN and PNP input stages is around 950mV from V+. Because each input stage
has its own offset voltage (VOS), the VOS of the comparator becomes a function of the VCM. See curves for VOS
vs. VCM in the Typical Characteristics section. In application design, it is recommended to keep the VCM away
from the crossover point to avoid problems. The wide input voltage range makes LMV7275-Q1 ideal in power
supply monitoring circuits, where the comparators are used to sense signals close to ground and power supplies.
10
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Feature Description (continued)
7.3.2 Output Stage
Figure 19. LMV7275-Q1 Open-Drain Output
The LMV7275-Q1 has an open-drain output that requires a pull-up resistor to a positive supply voltage for the
output to operate properly. When the internal output transistor is off, the output voltage will be pulled up to the
external positive voltage (V2+) by the external pull-up resistor. This allows the output to be OR'ed with other
open-drain outputs on the same bus.
The output pull-up resistor may be connected to any voltage level between V- and V+ for level shifting
applications.
7.4 Device Functional Modes
7.4.1 Capacitive and Resistive Loads
The propagation delay on the rising edge of the LMV7275-Q1 depends on the load resistance and capacitance
values.
7.4.2 Noise
Most comparators have rather low gain. This allows the output to alternate between high and low when the input
signal changes slowly. The result is the output may oscillate between high and low when the differential input is
near zero and triggers on noise. The high gain of this comparator eliminates this problem. Less than 1 μV of
change on the input will drive the output from one rail to the other rail. If the input signal is noisy, the output
cannot ignore the noise unless some hysteresis is provided by positive feedback. (See Hysteresis.)
7.4.3 Hysteresis
It is a standard procedure to use hysteresis (positive feedback) around a comparator to prevent oscillation due to
the comparator triggering its own noise on slowly ramping signals. The following sections will describe various
ways to apply hysteresis.
7.4.3.1 Non-inverting Comparator With Hysteresis
Non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (Vref) at the
inverting input. When Vin is low, the output is also low. For the output to switch from low to high, Vin must rise up
to Vin1 where Vin1 is calculated by:
(1)
When Vin is high, the output is also high. To make the comparator switch back to its low state, Vin must equal Vref
before VA will again equal Vref. Vin can be calculated by:
(2)
The hysteresis of this circuit is the difference between Vin1 and Vin2.
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Device Functional Modes (continued)
ΔVin = VCCR1/R2
(3)
VCC = +5V
RPULL-UP
3 .
VO
VREF = +2.5V
VO
+
VIN 2
VA
VIN 1
RLOAD
100 .
VIN
R1
330 N
5V
R2
1 0
0V
1.675
VIN
VO HIGH
VO LOW
VCC
VIN 1
R2
3.325
R1
VA = VREF
VA = VREF
R1
R2
VIN 2
Figure 20. Non-Inverting Comparator With Hysteresis
7.4.3.2 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply
voltage VCC of the comparator. When Vin at the inverting input is less than Va, the voltage at the non-inverting
node of the comparator (Vin < Va), the output voltage is high (for simplicity assume VO switches as high as VCC).
The three network resistors can be represented as R1//R3 in series with R2. The lower input trip voltage Va1 is
defined as:
(4)
When Vin is greater than Va (Vin > Va), the output voltage is low very close to ground. In this case the three
network resistors can be presented as R2//R3 in series with R1. The upper trip voltage Va2 is defined as:
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Device Functional Modes (continued)
(5)
The total hysteresis provided by the network is defined as:
ΔVa = Va1 - Va2
(6)
To assure that the comparator will always switch fully to VCC and not be pulled down by the load the resistors
values should be chosen as follow:
RPULL-UP RPULL-UP.
(7)
(8)
VCC = +5V
R1
1 0
RPULL-UP
3 .
5
VO
VIN
VA
VO
+
R2
1 0
VA2
VA1
RLOAD
100 .
R3
1 0
0
1.67
3.33
VIN
VO HIGH
VO LOW
VCC
VCC
R1
R3
R1
VA1
VA2
R2
R2
R3
Figure 21. Inverting Comparator With Hysteresis
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Device Functional Modes (continued)
7.4.4 Zero Crossing Detector
VCC
RPULL-UP
RPROT
+
VO
Figure 22. Simple Zero Crossing Detector
In a zero crossing detector circuit, the inverting input is connected to ground and the Non-Inverting input is
connected to a 100 mVPP AC signal. As the signal at the Non-Inverting input crosses 0 V, the output of the
comparator changes state.
RPROT is an optional input protection resistor to limit the current should the input voltage exceed the supply rails.
RPROT should be a minimum of 1 kΩ per volt of expected over-voltage and limit the current to less than ±1mA
under worst case fault conditions.
7.4.4.1 Zero Crossing Detector With Hysteresis
VCC
R3
R1
R4
RPULL-UP
R2
VIN
V2
VO
+
V1
D1
R6
R5
Figure 23. Zero Crossing Detector With Hysteresis
To improve switching times and centering the input threshold to ground a small amount of positive feedback is
added to the circuit. Voltage divider R4 and R5 establishes a reference voltage, V1, at the positive input. By
making the series resistance, R1 plus R2 equal to R5, the switching condition, V1 = V2, will be satisfied when VIN
= 0.
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Device Functional Modes (continued)
The positive feedback resistor, R6, is made very large (with respect to R5 || R6 = 2000 R5). The resultant
hysteresis established by this network is very small (ΔV1 < 10 mV) but it is sufficient to insure rapid output
voltage transitions.
Diode D1 is used to insure that the inverting input terminal of the comparator never goes below approximately
−100 mV. As the input terminal goes negative, D1 will forward bias, clamping the node between R1 and R2 to
approximately −300 mV. This sets up a voltage divider with R2 and R3 preventing V2 from going below ground.
The maximum negative input overdrive is limited by the current handling ability of D1.
7.4.5 Threshold Detector
VIN
VD
R1
RPULL-UP
+
R2
VOUT
VREF
Figure 24. Threshold Detector
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on
the Non-Inverting input passes the VREF threshold, the output of the comparator changes state. It is important to
use a stable reference voltage to ensure a consistent switching point.
7.4.6 Universal Logic Level Shifter
VA
VCC
VB
10 N
RPULL-UP
+
10 N
Logic
In
Logic
Out
VB 9CC
Figure 25. Logic Level Shifter
The output of LMV7275-Q1 is an unconnected drain of an NMOS device, which can be pulled up, through a
resistor, to any desired output level below the comparators power supply voltage (VB ≤ VCC). Hence, the following
simple circuit works as a universal logic level shifter, pulling up the signal to the desired level.
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Device Functional Modes (continued)
For example, VA could be the 5-V analog supply voltage, where VB could be the 3.3-V supply of the processor.
The output will now be compatible with the 3.3-V logic.
7.4.7 OR'ING the Output
VD
RPULL-UP
+
VO
+
+
+
Figure 26. OR’ing the Outputs
Open-drain outputs may be tied together, pulled up to VD by a common resistor to provide an output OR'ing
function. If any of the comparator outputs goes low, the output VO goes low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV7275-Q1 is a single-supply comparator with 880 ns of propagation delay and only 12 µA of supply
current.
8.2 Typical Applications
8.2.1 Square Wave Oscillator
+
V
4.3k:
R4 = 100k:
C1 = 750pF
VC
VO
+
R1 = 100k:
VA
R3 = 100k:
+
R2 = 100k:
V
0
f |10KHz
Figure 27. Square Wave Oscillator Application
8.2.1.1 Design Requirements
A typical application for a comparator is as a square wave oscillator. Figure 27 generates a square wave whose
period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is limited by
the large signal propagation delay of the comparator, and by the capacitive loading at the output, which limits the
output slew rate.
8.2.1.2 Detailed Design Procedure
To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than
the Non-Inverting input (VA).
Figure 28. Squarewave Oscillator Timing Thresholds
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Typical Applications (continued)
This causes the C1 to get charged through R4, and the voltage VC increases till it is equal to the Non-Inverting
input. The value of VA at this point is
VCC.R2
VA1 =
R2 + R1||R3
(9)
If R1 = R2 = R3, then VA1 = 2VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is
VCC (R2||R3)
VA2 =
R1 + (R2||R3)
(10)
If R1 = R2 = R3, then VA2 = VCC/3
The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:
F = 1/(2·R4·C1·ln2)
8.2.1.3 Application Curve
Figure 29 shows the simulated results of an oscillator using the following values:
1.
2.
3.
4.
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 750 pF, CL = 20 pF
V+ = 5 V, V- = GND
CSTRAY (not shown) from Va to GND = 10 pF
6
VOUT
5
Va
VOUT (V)
4
3
2
1
Vc
0
-1
0
100
200
300
TIME (µs)
400
500
C001
Figure 29. Square Wave Oscillator Output Waveforms
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Typical Applications (continued)
8.2.2 Positive Peak Detector
V+
R1
10 N
VIN
+
Q1
VOUT
R1
1 0
+
C1
- 10 µF
Figure 30. Positive Peak Detector
The positive peak detector is basically the comparator operated as a unity gain follower with a large holding
capacitor from the output to ground. A transistor is added to the output to provide a low impedance current
source. The upper output swing is limited by the emitter-base forward voltage. This allows capture of the most
positive input signal between 0 V and (V+) - 0.7V.
When the output of the comparator goes high, current is passed through the transistor to charge up the
capacitor. The only discharge path will be the 1-MΩ resistor shunting C1 and any load that is connected to the
output. The decay time can be altered simply by changing the 1-MΩ resistor.
8.2.3 Negative Peak Detector
VIN
+
VOUT
V-
R1
1 0
- C
1
+ 10 µF
Figure 31. Negative Peak Detector for Negative Supply
The Negative Peak Detector circuit will store the peak negative voltage below ground ( 0 V to V-). For the
negative detector, the output transistor acts as a low-impedance current sink.
When VIN is more negative than VOUT, the output transistor will conduct and pull the output to -VCC, charging C1.
Charging stops when C1 reaches the same level as VIN. Because there is no pull-up resistor, the only discharge
path will be the 1-MΩ resistor and any load impedance applied. Therefore, the decay time is set by varying the 1MΩ resistor. Be sure to observe the polarity of C1!
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Typical Applications (continued)
V+
R1
1 0
VIN
+
+
C1
- 10 µF
VOUT
Figure 32. Negative Peak Detector for Positive Supply
An alternate positive supply version is shown in Figure 32 that will capture the lowest applied VIN value between
V+ and ground (V+ to 0V).
The output of either version should be buffered by a high-impedance follower stage to prevent loading of the RC
circuit.
8.2.4 Window Detector
V
+
R1
+
VREF2
A
OUTPUT A
B
OUTPUT B
R2
VIN
+
-
VREF1
R3
Figure 33. Window Detector
A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are
true (high) when VREF1 < VIN < VREF2
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Typical Applications (continued)
VIN
V
OUTPUT B
+
VREF2
VREF1
OUTPUT A
BOTH OUTPUTS
ARE HIGH
Figure 34. Window Detector Output Signal
The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or within the window, where these are
defined as:
VREF1 = R3 / (R1 + R2 + R3) × V+
(11)
VREF2 = (R2 + R3) / (R1 + R2 + R3) × V+
(12)
To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be
reversed to invert the logic.
The outputs should be tied together and use a shared pull-up resistor for a common logic output. If individual limit
outputs are needed, then each output will require it's own pull-up resistor.
Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.
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9 Power Supply Recommendations
To minimize supply noise, power supplies should be decoupled by a 0.01-μF ceramic capacitor in parallel with a
10-μF capacitor.
Due to the nanosecond edges on the output transition, peak supply currents will be drawn during the time the
output is transitioning. Peak current depends on the capacitive loading on the output. The output transition can
cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power
supply to ring due to trace inductance and low self-resonance frequency of high ESR bypass capacitors.
Treat the LMV7275-Q1 as a high-speed device. Keep the ground paths short and place small (low-ESR ceramic)
bypass capacitors directly between the V+ and V– pins.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
10 Layout
10.1 Layout Guidelines
10.1.1 Circuit Techniques for Avoiding Oscillations in Comparator Applications
Feedback to almost any pin of a comparator can result in oscillation. In addition, when the input signal is a slow
voltage ramp or sine wave, the comparator may also burst into oscillation near the crossing point. To avoid
oscillation or instability, PCB layout should be engineered thoughtfully. Several precautions are recommended:
1. Power supply bypassing is critical, and will improve stability and response time. Resistance and inductance
from power supply wires and board traces increase power supply line impedance. When supply current
changes, the power supply line will move due to its impedance. Large enough supply line shift will cause the
comparator to malfunction. To avoid problems, a small bypass capacitor, such as 0.1-µF ceramic, should be
placed immediately adjacent to the supply pins. An additional 6.8 μF or greater tantalum capacitor should be
placed at the point where the power supply for the comparator is introduced onto the board. These
capacitors act as an energy reservoir and keep the supply impedance low. In a dual-supply application, a
0.1-μF capacitor is recommended to be placed across V+ and V− pins.
2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize any unwanted
coupling from any high-level signals (such as the output). The comparators can easily oscillate if the output
lead is inadvertently allowed to capacitively couple to the inputs through stray capacitance. This shows up
only during the output voltage transition intervals as the comparator changes states. Try to avoid a long loop
which could act as an inductor (coil).
3. It is a good practice to use an unbroken ground plane on a printed-circuit-board to provide all components
with a low inductive ground connection. Make sure ground paths are low-impedance where heavier currents
are flowing to avoid ground level shift. Preferably there should be a ground plane under the component.
4. The output trace should be routed away from inputs. The ground plane should extend between the output
and inputs to act as a guard. This can be achieved by running a topside ground plane between the output
and inputs. A typical PCB layout is shown in Figure 35.
5. When the signal source is applied through a resistive network to one input of the comparator, it is usually
advantageous to connect the other input with a resistor with the same value, for both DC and AC
consideration. Input traces should be laid out symmetrically if possible.
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10.2 Layout Example
Figure 35. Typical PCB Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For developmental support, see the following:
• LMV7275 PSPICE Model, SNOM555
• TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
• DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
• TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-74 A Quad of Independently Functioning Comparators, SNOA654
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMV7275IDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
SKA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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