LMV797MMX

LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 LMV796/LMV796Q/LMV797 17 MHz, Low Noise, CMOS Input, 1.8V Operational Amplifiers Check for Samples: LMV796, LMV797 FEATURES DESCRIPTION 1 (Typical 5V Supply, Unless Otherwise Noted) 2 • • • • • • • • • Input Referred Voltage Noise 5.8 nV/√Hz Input Bias Current 100 fA Unity Gain Bandwidth 17 MHz Supply Current per Channel – LMV796/LMV796Q 1.15 mA – LMV797 1.30 mA Rail-to-Rail Output Swing – @ 10 kΩ Load 25 mV from Rail – @ 2 kΩ Load 45 mV from Rail Guaranteed 2.5V and 5.0V Performance Total Harmonic Distortion 0.01% @ 1kHz, 600Ω Temperature Range −40°C to 125°C LMV796Q is an Automotive Grade Product that is AEC-Q100 Grade 1 Qualified and is Manufactured on an Automotive Grade Flow. APPLICATIONS • • • • • • Photodiode Amplifiers Active Filters and Buffers Low Noise Signal Processing Medical Instrumentation Sensor Interface Applications Automotive The LMV796/LMV796Q (Single) and the LMV797 (Dual) low noise, CMOS input operational amplifiers offer a low input voltage noise density of 5.8 nV/√Hz while consuming only 1.15 mA (LMV796/LMV796Q) of quiescent current. The LMV796/LMV796Q and LMV797 are unity gain stable op amps and have gain bandwidth of 17 MHz. The LMV796/LMV796Q/ LMV797 have a supply voltage range of 1.8V to 5.5V and can operate from a single supply. The LMV796/LMV796Q/LMV797 each feature a rail-to-rail output stage capable of driving a 600Ω load and sourcing as much as 60 mA of current. The LMV796/LMV796Q family provides optimal performance in low voltage and low noise systems. A CMOS input stage, with typical input bias currents in the range of a few femtoAmperes, and an input common mode voltage range, which includes ground, make the LMV796/LMV796Q and the LMV797 ideal for low power sensor applications. The LMV796/LMV796Q/LMV797 are manufactured using TI’s advanced VIP50 process. The LMV796/ LMV796Q are offered in 5–pin SOT-23 package. The LMV797 is offered in 8–pin VSSOP package. Typical Application CF 100 + V = 5.5V IIN CCM CD VB + + VOUT CIN = CD + CCM VOUT = - RF IIN VOLTAGE NOISE (nV/ Hz) RF V+ = 2.5V 10 1 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 1. Photodiode Transimpedance Amplifier Figure 2. Input Referred Voltage Noise vs. Frequency 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Human Body Model ESD Tolerance (3) 2000V Machine Model 200V Charge-Device Model 1000V VIN Differential ±0.3V Supply Voltage (V+ – V−) 6.0V Input/Output Pin Voltage V+ +0.3V, V− −0.3V −65°C to 150°C Storage Temperature Range Junction Temperature (4) +150°C Soldering Information (1) (2) (3) (4) Infrared or Convection (20 sec) 235°C Wave Soldering Lead Temperature (10 sec) 260°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model is 1.5kΩ in series with 100pF. Machine Model is 0Ω in series with 200pF. The maximum power dissipation is a function of TJMAX, θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJMAX - TA) / θJA. All numbers apply for packages soldered directly onto a PC Board. Operating Ratings (1) Temperature Range (2) −40°C to 125°C Supply Voltage (V+ – V−) Package Thermal Resistance (θJA) (2) (1) (2) −40°C ≤ TA ≤ 125°C 2.0V to 5.5V 0°C ≤ TA ≤ 125°C 1.8V to 5.5V 5-Pin SOT-23 180°C/W 8-Pin VSSOP 236°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics tables. The maximum power dissipation is a function of TJMAX, θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJMAX - TA) / θJA. All numbers apply for packages soldered directly onto a PC Board. 2.5V Electrical Characteristics Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.5V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage TC VOS Input Offset Voltage Temperature Drift Min Conditions (1) LMV796/LMV796Q (3) LMV797 Input Bias Current VCM = 1.0V (1) (2) (3) (4) (5) 2 Input Offset Current (1) Units 0.1 ±1.35 ±1.65 mV μV/°C −1.8 0.05 1 25 0.05 1 100 (4) (5) −40°C ≤ TA ≤ 125°C IOS Max (2) −1.0 (3) −40°C ≤ TA ≤ 85°C IB Typ VCM = 1.0V (5) 10 pA fA Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the statistical quality control (SQC) method. Typical values represent the parametric norm at the time of characterization. Offset voltage average drift is determined by dividing the change in VOS by temperature change. Positive current corresponds to current flowing into the device. This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 2.5V Electrical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.5V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Symbol CMRR Min Typ 80 75 94 2.0V ≤ V ≤ 5.5V, VCM = 0V 80 75 100 1.8V ≤ V+ ≤ 5.5V, VCM = 0V 80 98 Parameter Common Mode Rejection Ratio Conditions 0V ≤ VCM ≤ 1.4V + PSRR CMVR AVOL Power Supply Rejection Ratio Common Mode Voltage Range Open Loop Voltage Gain CMRR ≥ 60 dB CMRR ≥ 55 dB VOUT = 0.15V to 2.2V, RLOAD = 2 kΩ to V+/2 IS Supply Current per Amplifier SR Slew Rate GBW Gain Bandwidth en (1) Units dB 1.5 1.5 85 80 98 LMV797 82 78 92 88 84 110 25 75 82 RLOAD = 10 kΩ to V+/2 20 65 71 RLOAD = 2 kΩ to V+/2 30 75 78 RLOAD = 10 kΩ to V+/2 15 65 67 Sourcing to V− VIN = 200 mV (6) 35 28 47 Sinking to V+ VIN = –200 mV (6) 7 5 15 V dB RLOAD = 2 kΩ to V+/2 Output Voltage Swing Low Output Current Max dB LMV796/LMV796Q VOUT IOUT (2) −0.3 -0.3 VOUT = 0.15V to 2.2V, RLOAD = 10 kΩ to V+/2 Output Voltage Swing High (1) mV from either rail mA LMV796/LMV796Q 0.95 1.30 1.65 LMV797 per channel 1.1 1.50 1.85 mA AV = +1, Rising (10% to 90%) 8.5 AV = +1, Falling (90% to 10%) 10.5 14 MHz Input Referred Voltage Noise Density f = 1 kHz 6.2 nV/√Hz in Input Referred Current Noise Density f = 1 kHz 0.01 pA/√Hz THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, RLOAD = 600Ω 0.01 % (6) V/μs The short circuit test is a momentary test, the short circuit duration is 1.5ms. 5V Electrical Characteristics Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage TC VOS Input Offset Voltage Temperature Drift (1) (2) (3) Conditions Min (1) Typ Max (1) Units 0.1 ±1.35 ±1.65 mV (2) LMV796/LMV796Q (3) −1.0 LMV797 (3) −1.8 μV/°C Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the statistical quality control (SQC) method. Typical values represent the parametric norm at the time of characterization. Offset voltage average drift is determined by dividing the change in VOS by temperature change. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 3 LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. −40°C ≤ TA ≤ 85°C 0.1 1 25 −40°C ≤ TA ≤ 125°C 0.1 1 100 (4) (5) IB Input Bias Current VCM = 2.0V IOS Input Offset Current VCM = 2.0V (5) Common Mode Rejection Ratio 0V ≤ VCM ≤ 3.7V 80 75 100 2.0V ≤ V+ ≤ 5.5V, VCM = 0V 80 75 100 1.8V ≤ V+ ≤ 5.5V, VCM = 0V 80 98 CMRR PSRR CMVR AVOL 10 Power Supply Rejection Ratio Common Mode Voltage Range Open Loop Voltage Gain CMRR ≥ 60 dB CMRR ≥ 55 dB Output Voltage Swing High 85 80 97 LMV797 82 78 89 88 84 110 35 75 82 RLOAD = 10 kΩ to V+/2 25 65 71 LMV796/LM796Q 42 75 78 LMV797 45 80 83 20 65 67 + RLOAD = 2 kΩ to V /2 Output Voltage Swing Low RLOAD = 10 kΩ to V+/2 Output Current Sourcing to V− VIN = 200 mV (6) 45 37 60 Sinking to V+ VIN = –200 mV (6) 10 6 21 LMV796/LMV796Q IS Supply Current per Amplifier LMV797per channel 1.40 1.75 1.30 1.70 2.05 6.0 9.5 AV = +1, Falling (90% to 10%) 7.5 11.5 mV from either rail mA 1.15 AV = +1, Rising (10% to 90%) V dB RLOAD = 2 kΩ to V+/2 VOUT IOUT dB 4 4 LMV796/LMV796Q VOUT = 0.3V to 4.7V, RLOAD = 10 kΩ to V+/2 fA dB −0.3 -0.3 VOUT = 0.3V to 4.7V, RLOAD = 2 kΩ to V+/2 pA mA SR Slew Rate GBW Gain Bandwidth 17 MHz en Input Referred Voltage Noise Density f = 1 kHz 5.8 nV/√Hz in Input Referred Current Noise Density f = 1 kHz 0.01 pA/√Hz THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, RLOAD = 600Ω 0.01 % (4) (5) (6) 4 V/μs Positive current corresponds to current flowing into the device. This parameter is specified by design and/or characterization and is not tested in production. The short circuit test is a momentary test, the short circuit duration is 1.5ms. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 Connection Diagram 5 1 + V OUT A -IN A V - 2 7 + + V OUT B 2 + +IN 8 1 - OUTPUT 3 +IN A 4 -IN V Figure 3. 5-Pin SOT-23 Top View - 3 4 +- 6 5 -IN B +IN B Figure 4. 8-Pin VSSOP Top View Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 5 LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2. Supply Current vs. Supply Voltage (LMV796/LMV796Q) Supply Current vs. Supply Voltage (LMV797) 2 2 1.6 1.6 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 125°C 125°C 25°C 1.2 0.8 -40°C 0.4 0 1.5 2.5 3.5 4.5 25°C 1.2 -40°C 0.8 0.4 0 1.5 5.5 6.0 2.5 3.5 + 4.5 5.5 6 + V (V) V (V) Figure 5. Figure 6. VOS vs. VCM 0.5 VOS vs. VCM 0.6 + V = 1.8V 0.55 0.45 + V = 2.5V 125°C 0.5 0.4 0.45 0.3 VOS (mV) VOS (mV) -40°C 0.35 25°C 0.25 0.4 0.35 25°C 0.3 0.25 0.2 0.15 0.1 -0.3 -40°C 0.2 125°C 0.15 0 0.3 0.6 0.9 0.1 -0.3 1.2 Figure 7. Figure 8. VOS vs. VCM VOS vs. Supply Voltage + 0.45 0.4 0.4 -40°C 0.35 0.35 0.3 0.3 VOS (mV) VOS (mV) 1.8 0.5 V = 5V 0.45 25°C 0.25 0.2 -40°C 0.25 25°C 0.2 0.15 0.15 125°C 0.1 125°C 0.1 0.05 0.05 0 0.6 1.5 2.4 3.3 4.2 1.5 2.5 3.5 4.5 5.5 6.0 + VCM (V) V (V) Figure 9. 6 1.1 VCM (V) 0.5 0 -0.3 0.4 VCM (V) Figure 10. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2. Slew Rate vs. Supply Voltage Input Bias Current vs. VCM 1.5 13 + V = 5V 1 12 -40°C FALLING 0 IBIAS (pA) SLEW RATE (V/Ps) 0.5 11 10 9 -0.5 25°C -1 -1.5 8 -2 RISING 7 -2.5 6 1.8 -3 2.3 2.8 3.3 3.8 4.3 4.8 0 5.3 5.5 1 2 + V (V) Figure 11. 4 Figure 12. Input Bias Current vs. VCM 50 Sourcing Current vs. Supply Voltage 80 + V = 5V 40 70 30 125°C 60 20 125°C ISOURCE (mA) IBIAS (pA) 3 VCM (V) 10 0 85°C -10 -40°C 50 25°C 40 30 -20 20 -30 10 -40 0 -50 0 1 2 3 1 4 2 3 VCM (V) 4 5 6 V+ (V) Figure 13. Figure 14. Sinking Current vs. Supply Voltage Sourcing Current vs. Output Voltage 35 70 30 60 125°C 125°C 50 ISOURCE (mA) ISINK (mA) 25 25°C 20 15 -40°C 10 -40°C 40 25°C 30 20 5 10 0 0 1 2 3 4 5 6 0 + 1 2 3 V (V) VOUT (V) Figure 15. Figure 16. 4 5 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 7 LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2. Sinking Current vs. Output Voltage Positive Output Swing vs. Supply Voltage 40 30 RLOAD = 10 k: 35 VOUT FROM RAIL (mV) 125°C 25 ISINK (mA) 20 25°C 15 10 -40°C 5 125°C 25 25°C 20 -40°C 15 10 5 0 1.8 0 0 1 2 3 4 5 2.5 3.2 VOUT (V) V (V) Figure 17. Figure 18. 5.3 6 Positive Output Swing vs. Supply Voltage 25 50 45 VOUT FROM RAIL (mV) 20 15 125°C 10 5 125°C 40 25°C 35 30 25 20 -40°C 15 10 RLOAD = 10 k: 0 1.8 2.5 3.2 5 3.9 4.6 5.3 RLOAD = 2 k: 0 1.8 2.5 3.2 6 + V (V) 4.6 5.3 6 Figure 20. Negative Output Swing vs. Supply Voltage Positive Output Swing vs. Supply Voltage 100 50 -40°C 45 90 25°C VOUT FROM RAIL (mV) 40 35 125°C 30 25 20 15 RLOAD = 600: 80 125°C 70 60 25°C 50 40 -40°C 30 20 10 5 3.9 + V (V) Figure 19. VOUT FROM RAIL (mV) 4.6 Negative Output Swing vs. Supply Voltage -40°C 10 RLOAD = 2 k: 0 1.8 2.5 3.2 3.9 4.6 5.3 6 0 1.8 + 2.5 3.2 3.9 4.6 5.3 6 + V (V) V (V) Figure 21. 8 3.9 + 25°C VOUT FROM RAIL (mV) 30 Figure 22. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2. Negative Output Swing vs. Supply Voltage Time Domain Voltage Noise 120 VS = ±2.5V 125°C RLOAD = 600: VCM = 0.0V 25°C 80 400 nV/DIV VOUT FROM RAIL (mV) 100 -40°C 60 40 20 0 1.8 2.5 3.2 3.9 4.6 5.3 1S/DIV 6 + V (V) Figure 23. Figure 24. Input Referred Voltage Noise vs. Frequency Overshoot and Undershoot vs. CLOAD 100 70 OVERSHOOT AND UNDERSHOOT % + VOLTAGE NOISE (nV/ Hz) V = 5.5V V+ = 2.5V 10 1 US% 60 50 OS% 40 30 20 10 0 1 10 1k 100 10k 20 0 100k 40 FREQUENCY (Hz) 100 120 Figure 25. Figure 26. THD+N vs. Peak-to-Peak Output Voltage (VOUT) THD+N vs. Peak-to-Peak Output Voltage (VOUT) 0 0 + V = 1.2V + V = 2.75V -20 V = -2.75V AV = +2 -40 - -20 V = -0.6V AV = +2 THD+N (dB) -40 THD+N (dB) 80 60 CLOAD (pF) -60 RLOAD = 600: -80 -60 RLOAD = 600: -80 -100 -100 -120 RLOAD = 100 k: RLOAD = 100 k: -120 0.02 0.2 2 -140 0.02 0.2 OUTPUT AMPLITUDE (V) OUTPUT AMPLITUDE (V) Figure 27. Figure 28. 2 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 9 LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2. THD+N vs. Frequency THD+N vs. Frequency 0.006 0.006 0.005 0.004 THD+N (%) 0.004 RL = 100 k: 0.003 0.002 V+ = 1.2V + 0.003 V = 2.5V - V = 2.5V 0.002 VO = 4 VPP AV = +2 - V = 0.6V 0.001 VO = 0.9 VPP 0.001 AV = +2 0 10 RL = 100 k: 100 1k 10k 0 10 100k 100 Figure 29. CL = 50 pF GAIN (dB) GAIN 40 CL = 100 pF 100 80 80 80 60 60 60 40 20 20 0 CL = 20 pF -20 CL = 50 pF -40 CL = 100 pF -60 1k 10k 100k 1M 10M PHASE 100 GAIN (dB) CL = 20 pF 120 120 PHASE (°) 100 60 40 GAIN 20 20 0 0 0 -20 -20 -40 -40 -60 100M -20 -40 RLOAD = 600: 10 k: 10 M: -60 10k 100k -60 100M 10M FREQUENCY (Hz) Figure 31. Figure 32. Crosstalk Rejection 160 CROSSTALK REJECTION RATION (dB) OUTPUT IMPEDANCE (:) 1M FREQUENCY (Hz) 100 10 1 0.1 100 1k 10k 100k 1M 10M 100M 140 120 100 80 60 40 20 0 1k FREQUENCY (Hz) 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 33. 10 100 40 Closed Loop Output Impedance vs. Frequency 0.01 10 100k Open Loop Gain and Phase with Resistive Load 120 PHASE 80 10k Figure 30. Open Loop Gain and Phase with Capacitive Load 120 1k FREQUENCY (Hz) FREQUENCY (Hz) PHASE (°) THD+N (%) RL = 600: 0.005 RL = 600: Figure 34. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2. Large Signal Transient Response, AV = +1 10 mV/DIV 200 mV/DIV Small Signal Transient Response, AV = +1 INPUT = 20 mVPP INPUT = 1 VPP f = 200 kHz f = 1 MHz + + V = 2.5V V = 2.5V 800 ns/DIV Figure 35. Figure 36. Small Signal Transient Response, AV = +1 Large Signal Transient Response, AV = +1 10 mV/DIV 200 mV/DIV 200 ns/DIV INPUT = 20 mVPP f = 1 MHz INPUT = 1 VPP f = 200 kHz + V = 5V + V = 5V 200 ns/DIV 800 ns/DIV Figure 37. Figure 38. Phase Margin vs. Capacitive Load (Stability) Phase Margin vs. Capacitive Load (Stability) 50 50 RLOAD = 600: RLOAD = 600: 40 RLOAD = 10 k: 30 20 RLOAD = 10 M: 10 0 PHASE MARGIN (°) PHASE MARGIN (°) 40 RLOAD = 10 k: 30 20 RLOAD = 10 M: 10 0 + + V = 2.5V -10 10 V = 5V 100 1000 -10 10 100 1000 CLOAD (pF) CLOAD (pF) Figure 39. Figure 40. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 11 LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2. Negative PSRR vs. Frequency -20 -20 -40 NEGATIVE PSRR (dB) POSITIVE PSRR (dB) Positive PSRR vs. Frequency 0 -40 -60 1.8V -80 -60 + V = 1.8V -80 -100 + V = 5.5V 5.5V -100 10 -120 10k 1k 100 1M 100k 10 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 41. Figure 42. CMRR vs. Frequency Input Common Mode Capacitance vs. VCM 25 120 + V = 5V 100 20 + V = 2.5V CCM (pF) CMRR (dB) 80 + V = 5V 60 15 10 40 5 20 0 0 10 100 1k 10k 100k 1M 0 Figure 43. 12 1 2 3 4 VCM (V) FREQUENCY (Hz) Figure 44. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 APPLICATION INFORMATION ADVANTAGES OF THE LMV796/LMV797 Wide Bandwidth at Low Supply Current The LMV796 and LMV797 are high performance op amps that provide a unity gain bandwidth of 17 MHz while drawing a low supply current of 1.15 mA. This makes them ideal for providing wideband amplification in portable applications. Low Input Referred Noise and Low Input Bias Current The LMV796/LMV797 have a very low input referred voltage noise density (5.8 nV/√Hz at 1 kHz). A CMOS input stage ensures a small input bias current (100 fA) and low input referred current noise (0.01 pA/√Hz). This is very helpful in maintaining signal fidelity, and makes the LMV796 and LMV797 ideal for audio and sensor based applications. Low Supply Voltage The LMV796 and the LMV797 have performance specified at 2.5V and 5V supply. The LMV796 family is specified to be operational at all supply voltages between 2.0V and 5.5V, for ambient temperatures ranging from −40°C to 125°C, thus utilizing the entire battery lifetime. The LMV796 and LMV797 are also specified to be operational at 1.8V supply voltage, for temperatures between 0°C and 125°C. This makes the LMV796 family ideal for usage in low-voltage commercial applications. RRO and Ground Sensing Rail-to-rail output swing provides maximum possible dynamic range at the output. This is particularly important when operating at low supply voltages. An innovative positive feedback scheme is used to boost the current drive capability of the output stage. This allows the LMV796 and the LMV797 to source more than 40 mA of current at 1.8V supply. This also limits the performance of the LMV796 family as comparators, and hence the usage of the LMV796 and the LMV797 in an open-loop configuration is not recommended. The input common-mode range includes the negative supply rail which allows direct sensing at ground in single supply operation. Small Size The small footprint of the LMV796 and the LMV797 package saves space on printed circuit boards, and enables the design of smaller electronic products, such as cellular phones, pagers, or other portable systems. Long traces between the signal source and the op amp make the signal path susceptible to noise. By using the physically smaller LMV796 or LMV797 package, the op amp can be placed closer to the signal source, reducing noise pickup and increasing signal integrity. CAPACITIVE LOAD TOLERANCE The LMV796 and LMV797 can directly drive 120 pF in unity-gain without oscillation. The unity-gain follower is the most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers. The combination of the amplifier’s output impedance and the capacitive load induces phase lag. This results in either an underdamped pulse response or oscillation. To drive a heavier capacitive load, the circuit in Figure 45 can be used. In Figure 45, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO resistor value, the more stable VOUT will be. Increased RISO would, however, result in a reduced output swing and short circuit current. Figure 45. Isolation of CL to Improve Stability Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 13 LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com INPUT CAPACITANCE AND FEEDBACK CIRCUIT ELEMENTS The LMV796 family has a very low input bias current (100 fA) and a low 1/f noise corner frequency (400 Hz), which makes it ideal for sensor applications. However, to obtain this performance a large CMOS input stage is used, which adds to the input capacitance of the op amp, CIN. Though this does not affect the DC and low frequency performance, at higher frequencies the input capacitance interacts with the input and the feedback impedances to create a pole, which results in lower phase margin and gain peaking. This can be controlled by being selective in the use of feedback resistors, as well as, by using a feedback capacitance, CF. For example, in the inverting amplifier shown in Figure 46, if CIN and CF are ignored and the open loop gain of the op amp is considered infinite then the gain of the circuit is −R2/R1. An op amp, however, usually has a dominant pole, which causes its gain to drop with frequency. Hence, this gain is only valid for DC and low frequency. To understand the effect of the input capacitance coupled with the non-ideal gain of the op amp, the circuit needs to be analyzed in the frequency domain using a Laplace transform. CF R2 R1 + VIN CIN + + - - AV = - VOUT VIN =- VOUT R2 R1 Figure 46. Inverting Amplifier For simplicity, the op amp is modeled as an ideal integrator with a unity gain frequency of A0 . Hence, its transfer function (or gain) in the frequency domain is A0/s. Solving the circuit equations in the frequency domain, ignoring CF for the moment, results in an expression for the gain shown in Equation 1. -R2/R1 (s) = 1+ s2 s + § A0 R 1 § A0 ¨ ¨C R © R1 + R2 © IN 2 § ¨ © VIN § ¨ © VOUT (1) It can be inferred from the denominator of the transfer function that it has two poles, whose expressions can be obtained by solving for the roots of the denominator and are shown in Equation 2. -1 2CIN 1 1 + r R1 R2 §1 1 + ¨ R2 © R1 § ¨ © P1,2 = 2 - 4 A0CIN R2 (2) Equation 2 shows that as the values of R1 and R2 are increased, the magnitude of the poles, and hence the bandwidth of the amplifier, is reduced. This theory is verified by using different values of R1 and R2 in the circuit shown in Figure 45 and by comparing their frequency responses. In Figure 47 the frequency responses for three different values of R1 and R2 are shown. When both R1 and R2 are 1 kΩ, the response is flattest and widest; whereas, it narrows and peaks significantly when both their values are changed to 10 kΩ or 30 kΩ. So it is advisable to use lower values of R1 and R2 to obtain a wider and flatter response. Lower resistances also help in high sensitivity circuits since they add less noise. 14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 15 AV = -1 10 GAIN (dB) 5 0 -5 R1, R2 = 30 k: -10 R1, R2 = 10 k: -15 R1, R2 = 1 k: -20 -25 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 47. Gain Peaking Caused by Large R1, R2 A way of reducing the gain peaking is by adding a feedback capacitance CF in parallel with R2. This introduces another pole in the system and prevents the formation of pairs of complex conjugate poles which cause the gain to peak. Figure 48 shows the effect of CF on the frequency response of the circuit. Adding a capacitance of 2 pF removes the peak, while a capacitance of 5 pF creates a much lower pole and reduces the bandwidth excessively. 20 R1, R2 = 30 k: 10 CF = 0 pF AV = -1 GAIN (dB) 0 CF = 5 pF -10 CF = 2 pF -20 -30 -40 10k 100k 1M 10M FREQUENCY (Hz) Figure 48. Gain Peaking Eliminated by CF AUDIO PREAMPLIFIER WITH BAND PASS FILTERING With low input referred voltage noise, low supply voltage and current, and a low harmonic distortion, the LMV796 family is ideal for audio applications. Its wide unity gain bandwidth allows it to provide large gain for a wide range of frequencies and it can be used to design a preamplifier to drive a load of as low as 600Ω with less than 0.01% distortion. Two amplifier circuits are shown in Figure 49 and Figure 50. Figure 49 is an inverting amplifier, with a 10 kΩ feedback resistor, R2, and a 1kΩ input resistor, R1, and hence provides a gain of −10. Figure 50 is a noninverting amplifier, using the same values of R1and R2, and provides a gain of 11. In either of these circuits, the coupling capacitor CC1 decides the lower frequency at which the circuit starts providing gain, while the feedback capacitor CF decides the frequency at which the gain starts dropping off. Figure 51 shows the frequency response of the inverting amplifier with different values of CF. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 15 LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com CF R1 1 k: CC1 R2 10 k: + VIN CC2 - - + RB1 V + + - VOUT RB2 R2 = -10 R1 AV = - Figure 49. Inverting Audio Preamplifier + V RB1 CC2 + VIN RB2 - + - + R2 10 k: - VOUT CF R1 1 k: CC1 AV = 1 + R2 R1 = 11 Figure 50. Non-inverting Audio Preamplifier 25 CF = 10 pF 20 15 CF = 1 nF GAIN (dB) 10 CF = 100 pF 5 0 -5 -10 -15 -20 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 51. Frequency Response of the Inverting Audio Preamplifier TRANSIMPEDANCE AMPLIFIER CMOS input op amps are often used in transimpedance applications as they have an extremely high input impedance. A transimpedance amplifier converts a small input current into a voltage. This current is usually generated by a photodiode. The transimpedance gain, measured as the ratio of the output voltage to the input current, is expected to be large and wide-band. Since the circuit deals with currents in the range of a few nA, low noise performance is essential. The LMV796/LMV797 are CMOS input op amps providing wide bandwidth and low noise performance, and are hence ideal for transimpedance applications. 16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 LMV796, LMV797 www.ti.com SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 Usually, a transimpedance amplifier is designed on the basis of the current source driving the input. A photodiode is a very common capacitive current source, which requires transimpedance gain for transforming its miniscule current into easily detectable voltages. The photodiode and the amplifier’s gain are selected with respect to the speed and accuracy required of the circuit. A faster circuit would require a photodiode with lesser capacitance and a faster amplifier. A more sensitive circuit would require a sensitive photodiode and a high gain. A typical transimpedance amplifier is shown in Figure 52. The output voltage of the amplifier is given by the equation VOUT = −IINRF. Since the output swing of the amplifier is limited, RF should be selected such that all possible values of IIN can be detected. The LMV796/LMV797 have a large gain-bandwidth product (17 MHz), which enables high gains at wide bandwidths. A rail-to-rail output swing at 5.5V supply allows detection and amplification of a wide range of input currents. A CMOS input stage with negligible input current noise and low input voltage noise allows the LMV796/LMV797 to provide high fidelity amplification for wide bandwidths. These properties make the LMV796/LMV797 ideal for systems requiring wide-band transimpedance amplification. CF RF IIN CCM CD VB + + VOUT CIN = CD + CCM VOUT = - RF IIN Figure 52. Photodiode Transimpedance Amplifier As mentioned earlier, the following parameters are used to design a transimpedance amplifier: the amplifier gainbandwidth product, A0; the amplifier input capacitance, CCM; the photodiode capacitance, CD; the transimpedance gain required, RF; and the amplifier output swing. Once a feasible RF is selected using the amplifier output swing, these numbers can be used to design an amplifier with the desired transimpedance gain and a maximally flat frequency response. An essential component for obtaining a maximally flat response is the feedback capacitor, CF. The capacitance seen at the input of the amplifier, CIN, combined with the feedback capacitor, RF, generate a phase lag which causes gain-peaking and can destabilize the circuit. CIN is usually just the sum of CD and CCM. The feedback capacitor CF creates a pole, fP in the noise gain of the circuit, which neutralizes the zero in the noise gain, fZ, created by the combination of RF and CIN. If properly positioned, the noise gain pole created by CF can ensure that the slope of the gain remains at 20 dB/decade till the unity gain frequency of the amplifier is reached, thus ensuring stability. As shown in Figure 53, fP is positioned such that it coincides with the point where the noise gain intersects the op amp’s open loop gain. In this case, fP is also the overall −3 dB frequency of the transimpedance amplifier. The value of CF needed to make it so is given by Equation 3. A larger value of CF causes excessive reduction of bandwidth, while a smaller value fails to prevent gain peaking and instability. CF = 1 + 1 + 4SRFCINA0 2SRFA0 (3) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV796 LMV797 17 LMV796, LMV797 SNOSAU9D – MARCH 2006 – REVISED MARCH 2013 www.ti.com GAIN OP AMP OPEN LOOP GAIN fZ = fP = NOISE GAIN WITH NO CF 1 2S RFCIN NOISE GAIN WITH CF A0 2S RF(CIN+CF) fP fZ A0 FREQUENCY Figure 53. CF Selection for Stability Calculating CF from Equation 3 can sometimes return unreasonably small values (