Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
LOW-VOLTAGE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS
Check for Samples: LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
FEATURES
1
•
•
•
•
•
•
•
2.5-V, 2.7-V, and 5-V Performance
–40°C to 125°C Operation
No Crossover Distortion
Low Supply Current at VCC+ = 5 V:
– LMV821…0.3 mA Typ
– LMV822…0.5 mA Typ
– LMV824…1 mA Typ
Rail-to-Rail Output Swing
Gain Bandwidth of 5.5 MHz Typ at 5 V
Slew Rate of 1.9 V/μs Typ at 5 V
DESCRIPTION/
ORDERING INFORMATION
The LMV821 single, LMV822 dual, and LMV824 quad
devices are low-voltage (2.5 V to 5.5 V), low-power
commodity
operational
amplifiers.
Electrical
characteristics are very similar to the LMV3xx
operational amplifiers (low supply current, rail-to-rail
outputs, input common-mode range that includes
ground). However, the LMV8xx devices offer a higher
bandwidth (5.5 MHz typical) and faster slew rate
(1.9 V/μs typical).
The LMV8xx devices are cost-effective solutions for
applications
requiring
low-voltage/low-power
operation and space-saving considerations. The
LMV821 is available in the ultra-small DCK package,
which is approximately half the size of SOT-23-5. The
DCK package saves space on printed circuit boards
and enables the design of small portable electronic
devices (cordless and cellular phones, laptops, PDAs,
PCMIA). It also allows the designer to place the
device closer to the signal source to reduce noise
pickup and increase signal integrity.
The LMV8xx devices are characterized for operation
from –40°C to 85°C. The LMV8xxI devices are
characterized for operation from –40°C to 125°C.
LMV824 . . . D, DGV, OR PW PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
VCC+
2IN+
2IN−
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN−
4IN+
GND/VCC−
3IN+
3IN−
3OUT
LMV822 . . . D OR DGK PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN+
GND/VCC−
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN −
2IN+
LMV821 . . . DBV OR DCK PACKAGE
(TOP VIEW)
IN+
GND/VCC−
IN−
1
5
VCC+
4
OUT
2
3
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
ORDERING INFORMATION
PACKAGE (1)
TA
SC-70 – DCK
Single
SOT-23 – DBV
SOIC – D
–40°C to 85°C
Dual
MSOP/VSSOP – DGK
SOIC – D
Quad
TSSOP – PW
TVSOP – DGV
SC-70 – DCK
Single
SOT-23 – DBV
SOIC – D
–40°C to 125°C
Dual
MSOP/VSSOP – DGK
SOIC – D
Quad
TSSOP – PW
TVSOP – DGV
(1)
(2)
2
ORDERABLE PART NUMBER
Reel of 3000
LMV821DCKR
Reel of 250
LMV821DCKT
Reel of 3000
LMV821DBVR
Reel of 250
LMV821DBVT
Tube of 75
LMV822D
Reel of 2500
LMV822DR
Tube of 100
LMV822DGK
Reel of 2500
LMV822DGKR
Tube of 50
LMV824D
Reel of 2500
LMV824DR
Tube of 90
LMV824PW
Reel of 2000
LMV824PWR
Reel of 2000
LMV824DGVR
Reel of 3000
LMV821IDCKR
Reel of 250
LMV821IDCKT
Reel of 3000
LMV821IDBVR
Reel of 250
LMV821IDBVT
Tube of 75
LMV822ID
Reel of 2500
LMV822IDR
Tube of 100
LMV822IDGK
Reel of 2500
LMV822IDGKR
Tube of 50
LMV824ID
Reel of 2500
LMV824IDR
Tube of 90
LMV824IPW
Reel of 2000
LMV824IPWR
Reel of 2000
LMV824IDGVR
TOP-SIDE MARKING (2)
RY_
RB8_
MV822
RA_
LMV824
MV824
MV824
RZ_
RB1_
MV822I
R8_
LMV824I
MV824I
MV824I
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DGK: The actual top-side marking has one additional character that designates the assembly/test site.
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
Figure 1. SYMBOL (EACH AMPLIFIER)
−
IN −
OUT
+
IN +
Figure 2. LMV824 SIMPLIFIED SCHEMATIC
VCC
VBIAS1
+
VCC
−
VBIAS2
VBIAS5
+
+
Output
−
VCC VCC
−
VBIAS3
+
IN−
IN+
VBIAS4−
+
−
Copyright © 2004–2006, Texas Instruments Incorporated
3
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
(2)
VCC
Supply voltage
VID
Differential input voltage (3)
VI
Input voltage range (either input)
Duration of output short circuit (one amplifier) to ground (4)
VCC–
At or below TA = 25°C, VCC ≤ 5.5 V
D package
θJA
Package thermal impedance (5)
(6)
TJ
Operating virtual junction temperature
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
(6)
MAX
UNIT
5.5
V
±VCC
V
VCC+
V
Unlimited
8 pin
97
14 pin
86
DBV package
206
DCK package
252
DGK package
172
DGV package
127
PW package
113
–65
°C/W
150
°C
150
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND.
Differential voltages are at IN+ with respect to IN–.
Short circuits from outputs to VCC can cause excessive heating and eventual destruction.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN
VCC
TA
4
Supply voltage (single-supply operation)
Operating free-air temperature
MAX
2.5
5
LMV8xxI
–40
125
LMV8xx
–40
85
UNIT
V
°C
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
LMV8xx 2.5-V Electrical Characteristics
VCC+ = 2.5 V, VCC– = 0 V, VIC = 1 V, VO = 1.25 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
TEST CONDITIONS
TA
MIN
25°C
Input offset voltage
TYP
MAX
1
3.5
–40°C to 85°C
High level
VCC+ = 2.5 V, RL = 600 Ω to 1.25 V
Low level
VO
LMV8xx
Output swing
High level
VCC+ = 2.5 V, RL = 2 kΩ to 1.25 V
Low level
4
25°C
2.3
–40°C to 85°C
2.2
25°C
0.13
0.2
0.3
2.4
–40°C to 85°C
2.3
25°C
mV
2.37
–40°C to 85°C
25°C
UNIT
2.46
0.08
–40°C to 85°C
V
0.12
0.2
LMV8xxI 2.5-V Electrical Characteristics
VCC+ = 2.5 V, VCC– = 0 V, VIC = 1 V, VO = 1.25 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
TEST CONDITIONS
TA
25°C
Input offset voltage
TYP
MAX
1
3.5
–40°C to 125°C
High level
VCC+ = 2.5 V, RL = 600 Ω to 1.25 V
Low level
VO
LMV8xxI
MIN
Output swing
High level
VCC+ = 2.5 V, RL = 2 kΩ to 1.25 V
Low level
Copyright © 2004–2006, Texas Instruments Incorporated
5.5
25°C
2.28
–40°C to 125°C
2.18
25°C
0.13
–40°C to 125°C
2.28
25°C
–40°C to 125°C
0.22
0.32
2.38
mV
2.37
–40°C to 125°C
25°C
UNIT
2.46
0.08
V
0.14
0.22
5
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
LMV8xx 2.7-V Electrical Characteristics
VCC+ = 2.7 V, VCC– = 0 V, VIC = 1 V, VO = 1.35 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Average temperature coefficient
of input offset voltage
IIB
Input bias current
IIO
Input offset current
CMRR Common-mode rejection ratio
TEST CONDITIONS
VIC = 0 to 1.7 V
VCC+ = 1.7 V, VCC– = –1 V to –3.3 V,
VO = 0, VIC = 0
VICR
Common-mode input
voltage range
CMRR ≥ 50 dB
RL = 600 Ω to 1.35 V,
VO = 1.35 V to 2.2 V
Sourcing
RL = 600 Ω to 1.35 V,
VO = 1.35 V to 0.5 V
Sinking
RL = 2 kΩ to 1.35 V,
VO = 1.35 V to 2.2 V
Sourcing
RL = 2 kΩ to 1.35 V,
VO = 1.35 V to 0.5 V
Sinking
High level
VCC+ = 2.7 V,
RL = 600 Ω to 1.35 V
Low level
Output swing
High level
VCC+ = 2.7 V,
RL = 2 kΩ to 1.35 V
Low level
Supply current
25°C
1
25°C
30
0.5
25°C
70
68
25°C
75
–40°C to 85°C
70
25°C
73
–40°C to 85°C
70
100
25°C
90
–40°C to 85°C
85
25°C
85
–40°C to 85°C
80
25°C
95
90
85
25°C
2.5
–40°C to 85°C
2.4
25°C
2.58
0.2
0.3
2.6
–40°C to 85°C
2.5
25°C
2.66
0.08
–40°C to 85°C
V
0.12
0.2
12
16
VO = 2.7 V
Sinking
25°C
12
26
0.22
–40°C to 85°C
mA
0.3
0.5
0.45
–40°C to 85°C
25°C
dB
95
0.13
25°C
–40°C to 85°C
V
100
–40°C to 85°C
25°C
dB
90
25°C
LMV822 (both amplifiers)
nA
90
–40°C to 85°C
25°C
nA
dB
85
–0.3
to 2
mV
dB
85
–0.2
to 1.9
25°C
30
85
25°C
–40°C to 85°C
90
50
–40°C to 85°C
UNIT
μV/°C
140
Sourcing
LMV824 (all four amplifiers)
6
3.5
VO = 0 V
LMV821
ICC
1
4
25°C
Negative supply-voltage
rejection ratio
Output current
MAX
–40°C to 85°C
–kSVR
IO
TYP
–40°C to 85°C
VCC+ = 1.7 V to 4 V, VCC– = –1 V,
VO = 0, VIC = 0
VO
MIN
25°C
Positive supply-voltage
rejection ratio
Large-signal voltage
amplification
LMV8xx
–40°C to 85°C
+kSVR
AV
TA
0.6
0.8
0.72
mA
1
1.2
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
LMV8xx 2.7-V Electrical Characteristics (continued)
VCC+ = 2.7 V, VCC– = 0 V, VIC = 1 V, VO = 1.35 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
LMV8xx
MIN
TYP
MAX
UNIT
SR
Slew rate (1)
25°C
1.7
V/μs
GBW
Gain bandwidth product
(2)
25°C
5
MHz
Φm
Phase margin
(2)
25°C
60
deg
Gain margin
(2)
dB
25°C
8.6
Amplifier-to-amplifier isolation
VCC+ = 5 V, RL = 100 kΩ to 2.5 V (3)
25°C
135
dB
Vn
Equivalent input noise voltage
f = 1 kHz, VIC = 1 V
25°C
45
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.18
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = –2, RL = 10 kΩ,
VO = 4.1 Vp-p
25°C
0.01
%
THD
(1)
(2)
(3)
Connected as voltage follower with 1-V step input. Value specified is the slower of the positive and negative slew rates.
40-dB closed-loop dc gain, CL = 22 pF
Each amplifier excited in turn with 1 kHz to produce VO = 3 Vp-p
Copyright © 2004–2006, Texas Instruments Incorporated
7
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
LMV8xxI 2.7-V Electrical Characteristics
VCC+ = 2.7 V, VCC– = 0 V, VIC = 1 V, VO = 1.35 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Average temperature coefficient
of input offset voltage
IIB
Input bias current
IIO
Input offset current
CMRR Common-mode rejection ratio
TEST CONDITIONS
VIC = 0 to 1.7 V
VCC+ = 1.7 V, VCC– = –1 V to –3.3 V,
VO = 0, VIC = 0
VICR
Common-mode input
voltage range
CMRR ≥ 50 dB
RL = 600 Ω to 1.35 V,
VO = 1.35 V to 2.2 V
Sourcing
RL = 600 Ω to 1.35 V,
VO = 1.35 V to 0.5 V
Sinking
RL = 2 kΩ to 1.35 V,
VO = 1.35 V to 2.2 V
Sourcing
RL = 2 kΩ to 1.35 V,
VO = 1.35 V to 0.5 V
Sinking
High level
VCC+ = 2.7 V,
RL = 600 Ω to 1.35 V
Low level
Output swing
High level
VCC+ = 2.7 V,
RL = 2 kΩ to 1.35 V
Low level
Supply current
25°C
1
25°C
30
0.5
25°C
70
68
25°C
75
–40°C to 125°C
70
25°C
73
–40°C to 125°C
70
–0.3
to 2
100
25°C
90
–40°C to 125°C
85
25°C
85
–40°C to 125°C
80
25°C
95
–40°C to 125°C
90
25°C
90
–40°C to 125°C
85
25°C
2.5
–40°C to 125°C
2.4
25°C
2.5
25°C
2.58
0.2
2.66
0.08
V
0.12
0.2
12
16
VO = 2.7 V
Sinking
25°C
12
26
0.22
–40°C to 125°C
mA
0.3
0.5
0.45
–40°C to 125°C
25°C
dB
95
–40°C to 125°C
–40°C to 125°C
V
0.3
–40°C to 125°C
25°C
dB
100
0.13
2.6
nA
90
–40°C to 125°C
25°C
nA
dB
85
–0.2
to 1.9
mV
dB
85
25°C
LMV822 (both amplifiers)
30
85
25°C
25°C
90
50
–40°C to 125°C
UNIT
μV/°C
140
Sourcing
LMV824 (all four amplifiers)
8
3.5
VO = 0 V
LMV821
ICC
1
5.5
25°C
Negative supply-voltage
rejection ratio
Output current
MAX
–40°C to 125°C
–kSVR
IO
TYP
–40°C to 125°C
VCC+ = 1.7 V to 4 V, VCC– = –1 V,
VO = 0, VIC = 0
VO
MIN
25°C
Positive supply-voltage
rejection ratio
Large-signal voltage
amplification
LMV8xxI
–40°C to 125°C
+kSVR
AV
TA
0.6
0.8
0.72
mA
1
1.2
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
LMV8xxI 2.7-V Electrical Characteristics (continued)
VCC+ = 2.7 V, VCC– = 0 V, VIC = 1 V, VO = 1.35 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
LMV8xxI
MIN
TYP
MAX
UNIT
SR
Slew rate (1)
25°C
1.7
V/μs
GBW
Gain bandwidth product
(2)
25°C
5
MHz
Φm
Phase margin
(2)
25°C
60
deg
Gain margin
(2)
dB
25°C
8.6
Amplifier-to-amplifier isolation
VCC+ = 5 V, RL = 100 kΩ to 2.5 V (3)
25°C
135
dB
Vn
Equivalent input noise voltage
f = 1 kHz, VIC = 1 V
25°C
45
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.18
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = –2, RL = 10 kΩ,
VO = 4.1 Vp-p
25°C
0.01
%
THD
(1)
(2)
(3)
Connected as voltage follower with 1-V step input. Value specified is the slower of the positive and negative slew rates.
40-dB closed-loop dc gain, CL = 22 pF
Each amplifier excited in turn with 1 kHz to produce VO = 3 Vp-p
Copyright © 2004–2006, Texas Instruments Incorporated
9
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
LMV8xx 5-V Electrical Characteristics
VCC+ = 5 V, VCC– = 0 V, VIC = 2 V, VO = 2.5 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Average temperature coefficient
of input offset voltage
IIB
Input bias current
IIO
Input offset current
CMRR Common-mode rejection ratio
TEST CONDITIONS
VIC = 0 to 4 V
VCC+ = 1.7 V, VCC– = –1 V to –3.3 V,
VO = 0, VIC = 0
VICR
Common-mode input
voltage range
CMRR ≥ 50 dB
RL = 600 Ω to 2.5 V,
VO = 2.5 V to 4.5 V
Sourcing
RL = 600 Ω to 2.5 V,
VO = 2.5 V to 0.5 V
Sinking
RL = 2 kΩ to 2.5 V,
VO = 2.5 V to 4.5 V
Sourcing
RL = 2 kΩ to 2.5 V,
VO = 2.5 V to 0.5 V
Sinking
High level
VCC+ = 5 V,
RL = 600 Ω to 2.5 V
Low level
Output swing
High level
VCC+ = 5 V,
RL = 2 kΩ to 2.5 V
Low level
VO = 0 V
Sourcing
Output current
VO = 5 V
Sinking
LMV821
Supply current
LMV822 (both amplifiers)
LMV824 (all four amplifiers)
10
1
3.5
4
25°C
1
25°C
40
0.5
25°C
72
70
25°C
75
–40°C to 85°C
70
25°C
73
–40°C to 85°C
70
105
25°C
95
–40°C to 85°C
90
25°C
95
–40°C to 85°C
90
25°C
95
–40°C to 85°C
95
–40°C to 85°C
4.7
25°C
dB
105
105
4.84
0.17
0.25
0.3
25°C
4.85
–40°C to 85°C
4.8
25°C
4.9
0.1
–40°C to 85°C
V
0.15
0.2
25°C
20
–40°C to 85°C
15
25°C
20
–40°C to 85°C
15
45
mA
40
0.3
–40°C to 85°C
0.4
0.6
0.5
–40°C to 85°C
25°C
V
105
–40°C to 85°C
–40°C to 85°C
dB
90
4.75
25°C
nA
90
25°C
25°C
nA
dB
85
–0.3
to 4.3
mV
dB
85
–0.2
to 4.2
25°C
30
90
25°C
–40°C to 85°C
100
50
–40°C to 85°C
UNIT
μV/°C
150
25°C
Negative supply-voltage
rejection ratio
ICC
MAX
–40°C to 85°C
–kSVR
IO
TYP
–40°C to 85°C
VCC+ = 1.7 V to 4 V, VCC– = –1 V,
VO = 0, VIC = 0
VO
MIN
25°C
Positive supply-voltage
rejection ratio
Large-signal voltage
amplification
LMV8xx
–40°C to 85°C
+kSVR
AV
TA
0.7
0.9
1
mA
1.3
1.5
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
LMV8xx 5-V Electrical Characteristics (continued)
VCC+ = 5 V, VCC– = 0 V, VIC = 2 V, VO = 2.5 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC+ = 5 V (1)
TA
25°C
LMV8xx
MIN
TYP
1.4
MAX
UNIT
SR
Slew rate
1.9
V/μs
GBW
Gain bandwidth product
(2)
25°C
5.5
MHz
Φm
Phase margin
(2)
25°C
64.2
deg
Gain margin
(2)
dB
25°C
8.7
Amplifier-to-amplifier isolation
VCC+ = 5 V, RL = 100 kΩ to 2.5 V (3)
25°C
135
dB
Vn
Equivalent input noise voltage
f = 1 kHz, VIC = 1 V
25°C
42
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.2
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = –2, RL = 10 kΩ,
VO = 4.1 Vp-p
25°C
0.01
%
THD
(1)
(2)
(3)
Connected as voltage follower with 3-V step input. Value specified is the slower of the positive and negative slew rates.
40-dB closed-loop dc gain, CL = 22 pF
Each amplifier excited in turn with 1 kHz to produce VO = 3 Vp-p
Copyright © 2004–2006, Texas Instruments Incorporated
11
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
LMV8xxI 5-V Electrical Characteristics
VCC+ = 5 V, VCC– = 0 V, VIC = 2 V, VO = 2.5 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Average temperature coefficient
of input offset voltage
IIB
Input bias current
IIO
Input offset current
CMRR Common-mode rejection ratio
TEST CONDITIONS
VIC = 0 to 4 V
VCC+ = 1.7 V, VCC– = –1 V to –3.3 V,
VO = 0, VIC = 0
VICR
Common-mode input
voltage range
CMRR ≥ 50 dB
RL = 600 Ω to 2.5 V,
VO = 2.5 V to 4.5 V
Sourcing
RL = 600 Ω to 2.5 V,
VO = 2.5 V to 0.5 V
Sinking
RL = 2 kΩ to 2.5 V,
VO = 2.5 V to 4.5 V
Sourcing
RL = 2 kΩ to 2.5 V,
VO = 2.5 V to 0.5 V
Sinking
High level
VCC+ = 5 V,
RL = 600 Ω to 2.5 V
Low level
Output swing
High level
VCC+ = 5 V,
RL = 2 kΩ to 2.5 V
Low level
VO = 0 V
Sourcing
Output current
VO = 5 V
Sinking
LMV821
Supply current
LMV822 (both amplifiers)
LMV824 (all four amplifiers)
12
1
3.5
5.5
25°C
1
25°C
40
0.5
25°C
72
70
25°C
75
–40°C to 125°C
70
25°C
73
–40°C to 125°C
70
105
25°C
95
–40°C to 125°C
90
25°C
95
–40°C to 125°C
90
25°C
95
–40°C to 125°C
90
25°C
95
4.75
–40°C to 125°C
4.6
25°C
V
dB
105
105
4.84
0.17
0.25
0.3
25°C
4.85
–40°C to 125°C
4.8
25°C
4.9
0.1
–40°C to 125°C
V
0.15
0.2
25°C
20
–40°C to 125°C
15
25°C
20
–40°C to 125°C
15
45
mA
40
0.3
–40°C to 125°C
0.4
0.6
0.5
–40°C to 125°C
25°C
dB
105
–40°C to 125°C
–40°C to 125°C
nA
90
25°C
25°C
nA
dB
85
–0.3
to 4.3
mV
dB
85
–0.2
to 4.2
25°C
30
90
25°C
–40°C to 125°C
100
50
–40°C to 125°C
UNIT
μV/°C
150
25°C
Negative supply-voltage
rejection ratio
ICC
MAX
–40°C to 125°C
–kSVR
IO
TYP
–40°C to 125°C
VCC+ = 1.7 V to 4 V, VCC– = –1 V,
VO = 0, VIC = 0
VO
MIN
25°C
Positive supply-voltage
rejection ratio
Large-signal voltage
amplification
LMV8xxI
–40°C to 125°C
+kSVR
AV
TA
0.7
0.9
1
mA
1.3
1.5
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
LMV8xxI 5-V Electrical Characteristics (continued)
VCC+ = 5 V, VCC– = 0 V, VIC = 2 V, VO = 2.5 V, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC+ = 5 V (1)
TA
25°C
LMV8xxI
MIN
TYP
1.4
MAX
UNIT
SR
Slew rate
1.9
V/μs
GBW
Gain bandwidth product
(2)
25°C
5.5
MHz
Φm
Phase margin
(2)
25°C
64.2
deg
Gain margin
(2)
dB
25°C
8.7
Amplifier-to-amplifier isolation
VCC+ = 5 V, RL = 100 kΩ to 2.5 V (3)
25°C
135
dB
Vn
Equivalent input noise voltage
f = 1 kHz, VIC = 1 V
25°C
42
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
25°C
0.2
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = –2, RL = 10 kΩ,
VO = 4.1 Vp-p
25°C
0.01
%
THD
(1)
(2)
(3)
Connected as voltage follower with 3-V step input. Value specified is the slower of the positive and negative slew rates.
40-dB closed-loop dc gain, CL = 22 pF
Each amplifier excited in turn with 1 kHz to produce VO = 3 Vp-p
Copyright © 2004–2006, Texas Instruments Incorporated
13
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
TYPICAL CHARACTERISTICS
TA = 25°C, VCC+ = 5-V Single Supply (Unless Otherwise Noted)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
1200
INPUT CURRENT
vs
TEMPERATURE
−30
LMV824
All Channels
VCC+ = 5 V
Vin = VCC+/2
TA = 855C
−40
II − Input Current − nA
ICC − Supply Current − µA
1000
TA = 255C
800
600
TA = −405C
400
−50
−60
200
−70
−40
0
0
1
2
3
4
VCC+ − Supply Voltage − V
5
6
80
100
0.01
0.1
1
Output Voltage Referenced to V+ − (V)
10
Figure 4.
SOURCING CURRENT
vs
OUTPUT VOLTAGE
SOURCING CURRENT
vs
OUTPUT VOLTAGE
100
VCC+ = 2.7 V
VCC+ = 5 V
10
IO − Source Current − mA
IO − Source Current − mA
0
20
40
60
TA − Temperature − °C
Figure 3.
100
1
0.1
0.01
0.001
0.01
0.1
1
Output Voltage Referenced to V+ − (V)
Figure 5.
14
−20
10
10
1
0.1
0.01
0.001
Figure 6.
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VCC+ = 5-V Single Supply (Unless Otherwise Noted)
SINKING CURRENT
vs
OUTPUT VOLTAGE
SINKING CURRENT
vs
OUTPUT VOLTAGE
100
100
VCC+ = 2.7 V
VCC+ = 5 V
10
IO − Sink Current − mA
IO − Sink Current − mA
10
1
1
0.1
0.1
0.01
0.01
0.1
0.01
1
10
Figure 8.
OUTPUT VOLTAGE SWING
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE SWING
vs
SUPPLY VOLTAGE
80
RL = 2 kΩ to Mid Rail
Output Voltage From Supply Voltage − mV
Output Voltage From Supply Voltage − mV
10
Output Voltage Referenced to GND − V
RL = 10 kΩ to Mid Rail
40
30
Negative Swing
20
0
2.6
1
Figure 7.
50
10
0.1
0.01
Output Voltage Referenced to GND − V
Positive Swing
3
3.4
3.8
4.2
VCC+ − Supply Voltage − V
Figure 9.
Copyright © 2004–2006, Texas Instruments Incorporated
4.6
5
70
60
50
Negative Swing
40
Positive Swing
30
20
10
0
2.6
3
3.4
3.8
4.2
VCC+ − Supply Voltage − V
4.6
5
Figure 10.
15
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VCC+ = 5-V Single Supply (Unless Otherwise Noted)
OUTPUT VOLTAGE SWING
vs
SUPPLY VOLTAGE
160
RL = 600 Ω to Mid Rail
Output Voltage From Supply Voltage − mV
Output Voltage From Supply Voltage − mV
160
OUTPUT VOLTAGE SWING
vs
LOAD RESISTANCE
150
140
Negative Swing
130
120
110
Positive Swing
100
90
80
70
60
2.6
RlL = 5 kΩ to Mid Rail
VCC+ = 5 V
140
120
100
80
60
40
20
0
3
3.4
3.8
4.2
4.6
100
5
VCC+ − Supply Voltage − V
10k
1000
Resistive Load − Ω
Figure 11.
Figure 12.
CROSSTALK REJECTION
vs
FREQUENCY
+PSRR
vs
FREQUENCY
100
160
100k
VCC+ = +2.5 V
90
150
140
70
VCC+ = +1.35 V
PSRR − dB
Crosstalk Rejection − dB
80
130
120
110
100
90
100
50
40
30
VCC+ = ±2.5 V
VI = 3 VPP
RL = 5 kΩ
AV = 1
20
10
1k
10k
Frequency − Hz
Figure 13.
16
60
100k
0
100
1k
10k
Frequency − Hz
100k
1M
Figure 14.
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VCC+ = 5-V Single Supply (Unless Otherwise Noted)
–PSRR
vs
FREQUENCY
100
VCC+ = +2.5 V
90
80
PSRR − dB
70
60 VCC+ = +1.35 V
50
40
30
20
10
0
100
1k
10k
100k
Frequency − Hz
Figure 15.
1M
GAIN AND PHASE MARGIN
vs
FREQUENCY
(VCC+ = 2.7 V, RL = 600 Ω, 2 kΩ, 100 kΩ)
80
140
Gain − dB
Phase
60
100
50
80
40
60
30
40
Gain
20
20
0
10
VCC+ = 2.7 V
600 Ω
2 kΩ
100 kΩ
0
−10
−20
−40
−20
1k
Phase Margin − Deg
120
70
10k
100k
1M
−60
10M
Frequency − Hz
Figure 16.
Copyright © 2004–2006, Texas Instruments Incorporated
17
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VCC+ = 5-V Single Supply (Unless Otherwise Noted)
GAIN AND PHASE MARGIN
vs
FREQUENCY
(VCC+ = 5 V, RL = 600 Ω, 2 kΩ, 100 kΩ)
80
140
70
120
100
Phase
50
80
40
60
30
40
20
20
Gain
0
10
−10
−20
−20
VCC+ = 5 V
600 Ω
2 kΩ
100 kΩ
0
1k
Phase Margin − Deg
Gain − dB
60
−40
10k
100k
Frequency − Hz
1M
−60
10M
Figure 17.
GAIN AND PHASE MARGIN
vs
FREQUENCY
(VCC+ = 2.7 V, RL = 10 kΩ, CL = 22 pF, 100 pF, 200 pF)
80
100
70
Gain − dB
60
60
50
40
40
20
30
0
20
−20
Gain
−40
10
VCC+ = 2.7 V
RL = 10 kΩ
22 pF
100 pF
200 pF
0
−10
−60
−80
−20
1k
Phase Margin − Deg
80
Phase
10k
100k
1M
−100
10M
Frequency − Hz
Figure 18.
18
Copyright © 2004–2006, Texas Instruments Incorporated
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
www.ti.com
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VCC+ = 5-V Single Supply (Unless Otherwise Noted)
GAIN AND PHASE MARGIN
vs
FREQUENCY
(VCC+ = 5 V, RL = 10 kΩ, CL = 22 pF, 100 pF, 200 pF)
80
100
70
80
Phase
60
50
40
40
20
0
30
Gain
−20
20
10
0
−10
−20
−40
VCC+ = 5 V
RL = 10 kΩ
22 pF
100 pF
200 pF
1k
Phase Margin − Deg
Gain − dB
60
−60
−80
10k
100k
1M
−100
10M
Frequency − Hz
Figure 19.
GAIN AND PHASE MARGIN
vs
FREQUENCY
(VCC+ = 2.7 V, RL = 600 Ω, CL = 22 pF, 100 pF, 200 pF)
80
140
70
120
Phase
100
50
80
40
60
30
40
20
20
Gain
VCC+ = 2.7 V
RL = 600 Ω
10
0
−20
22 pF
100 pF
200 pF
−10
−20
0
1k
Phase Margin − Deg
Gain − dB
60
−40
10k
100k
1M
−60
10M
Frequency − Hz
Figure 20.
Copyright © 2004–2006, Texas Instruments Incorporated
19
Not Recommended for New Designs
LMV821 SINGLE, LMV822 DUAL, LMV824 QUAD
SLOS434I – FEBRUARY 2004 – REVISED JULY 2006
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VCC+ = 5-V Single Supply (Unless Otherwise Noted)
GAIN AND PHASE MARGIN
vs
FREQUENCY
(VCC+ = 5 V, RL = 600 Ω, CL = 22 pF, 100 pF, 200 pF)
80
140
70
120
Phase
100
50
80
40
60
40
30
Gain
20
20
10
VCC+ = 5 V
RL = 600 Ω
0
−20
22 pF
100 pF
200 pF
−10
−20
0
1k
Phase Margin − Deg
Gain − dB
60
−40
10k
100k
1M
−60
10M
Frequency − Hz
Figure 21.
20
Copyright © 2004–2006, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
(4/5)
LMV821DBVR
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 85
LMV821DBVRE4
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 85
LMV821DBVRG4
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 85
LMV821DBVT
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 85
LMV821DBVTE4
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 85
LMV821DBVTG4
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 85
LMV821DCKR
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 85
LMV821DCKRE4
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 85
LMV821DCKRG4
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 85
LMV821DCKT
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 85
LMV821DCKTE4
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 85
LMV821DCKTG4
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 85
LMV821IDBVR
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDBVRE4
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDBVRG4
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDBVT
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDBVTE4
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDBVTG4
OBSOLETE
SOT-23
DBV
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDCKR
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDCKRE4
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDCKRG4
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDCKT
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDCKTE4
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 125
LMV821IDCKTG4
OBSOLETE
SC70
DCK
5
TBD
Call TI
Call TI
-40 to 125
LMV822D
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 85
LMV822DE4
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 85
LMV822DG4
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 85
LMV822DGKR
OBSOLETE
VSSOP
DGK
8
TBD
Call TI
Call TI
-40 to 85
Addendum-Page 1
Device Marking
(RB8B ~ RB8C ~
RB8I)
(RB8B ~ RB8C ~
RB8I)
(RYB ~ RYC ~ RYI)
(RYB ~ RYI)
RB1B
RB1B
(RZB ~ RZI)
(RZB ~ RZI)
MV822
(RAB ~ RAC)
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
(4/5)
LMV822DGKRG4
OBSOLETE
VSSOP
DGK
8
TBD
Call TI
Call TI
-40 to 85
LMV822DR
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 85
LMV822DRE4
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 85
LMV822DRG4
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 85
LMV822ID
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 125
LMV822IDE4
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 125
LMV822IDG4
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 125
LMV822IDGKR
OBSOLETE
VSSOP
DGK
8
TBD
Call TI
Call TI
-40 to 125
LMV822IDGKRG4
OBSOLETE
VSSOP
DGK
8
TBD
Call TI
Call TI
-40 to 125
LMV822IDR
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 125
LMV822IDRE4
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 125
LMV822IDRG4
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
-40 to 125
LMV824D
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 85
LMV824DE4
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 85
LMV824DG4
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 85
LMV824DGVR
OBSOLETE
TVSOP
DGV
14
TBD
Call TI
Call TI
-40 to 85
LMV824DGVRE4
OBSOLETE
TVSOP
DGV
14
TBD
Call TI
Call TI
-40 to 85
LMV824DGVRG4
OBSOLETE
TVSOP
DGV
14
TBD
Call TI
Call TI
-40 to 85
LMV824DR
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 85
LMV824DRE4
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 85
LMV824DRG4
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 85
LMV824ID
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 125
LMV824IDE4
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 125
LMV824IDG4
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 125
LMV824IDGVR
OBSOLETE
TVSOP
DGV
14
TBD
Call TI
Call TI
-40 to 125
LMV824IDGVRE4
OBSOLETE
TVSOP
DGV
14
TBD
Call TI
Call TI
-40 to 125
LMV824IDGVRG4
OBSOLETE
TVSOP
DGV
14
TBD
Call TI
Call TI
-40 to 125
LMV824IDR
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 125
LMV824IDRE4
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 125
LMV824IDRG4
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
-40 to 125
LMV824IPW
OBSOLETE
TSSOP
PW
14
TBD
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Call TI
-40 to 125
Addendum-Page 2
Device Marking
MV822
MV822I
(R8B ~ R8C)
MV822I
LMV824
MV824
LMV824
LMV824I
MV824I
LMV824I
MV824I
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV824IPWE4
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 125
LMV824IPWG4
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 125
LMV824IPWR
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 125
LMV824IPWRE4
NRND
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 125
LMV824IPWRG4
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 125
LMV824PW
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
LMV824PWE4
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
LMV824PWG4
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
LMV824PWR
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
LMV824PWRE4
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
LMV824PWRG4
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
MV824I
MV824
MV824
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV821 :
• Automotive: LMV821-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 4
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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