LMV832MMEVAL

User's Guide SNOA530A – October 2008 – Revised April 2013 AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 1 General Description To demonstrate the EMI robustness of the LMV831/LMV832/LMV834 and to be able to measure the parameter EMIRR, three evaluation boards have been developed; one for each device. This document describes the evaluation boards and explains how to perform EMIRR measurements. Focus is on one of the input pins as those are most sensitive to EMI. Based on symmetry considerations, it can be expected that both inputs have the same EMIRR. For reasons of simplicity of the required schematic the measurement on the IN+ pin is selected. A detailed description on EMI and EMIRR for the other pins can be found in the AN-1698 A Specification for EMI Hardened Operational Amplifiers Application Report (SNOA497). To identify EMI robust op amps, a parameter is defined that quantitatively describes the EMI performance. A quantitative measure enables the comparison and the ranking of op amps on their EMI robustness. The definition of the parameter EMIRR is given by: § VRF_PEAK · ¸ EMIRRV RF_PEAK = 20 log ¨ ¨ 'VOS ¸ © ¹ where VRF_PEAK is the amplitude of the applied unmodulated RF signal (V) and ΔVOS is the resulting inputreferred offset voltage shift (V). 2 Op Amp Configuration To have best defined RF levels on the pin under test, no op amp feedback elements should be in the RF signal path. Therefore, the op amp is connected in an unity-gain configuration. This yields the lowest level of RF filtering due to a feedback network. Schematics and layouts are included in this application report. 3 Applying the RF Signal Care needs to be taken in applying the RF signal to the pin under test. Signals up to a few GHz will be used, so the whole RF signal path needs to match the characteristic impedance of the RF generator. This requires proper coaxial cabling from the generator to the test board. On the test board a 50Ω stripline needs to be used to bring the RF signal as close as possible to the pin under test. In this case the stripline can be connected directly from the connector to the IN+ pin. A 50Ω termination at the pin under test is also required. For symmetry reasons this is done with two 100Ω resistors in parallel, one on each side of the strip line. Setting up the test environment with a 50Ω resistor close to the LMV831/LMV832/LMV834 ensures that the RF levels at the pin under test are well defined. This 50Ω resistor is also used to set the bias level of the IN+ pin to ground level. The DC measurements are taken at the output of the op amp. Since the op amp is in the unity gain configuration, the input referred offset voltage shift corresponds oneto-one to the measured output voltage shift. 4 Isolating the Other Pins When the pin under test is tested, the other pins need to be decoupled for RF signals. This ensures that the obtained offset voltage shift is dominantly a result of coupling the RF signal to the pin under test. For this decoupling standard, SMD components can be used. All trademarks are the property of their respective owners. SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 Copyright © 2008–2013, Texas Instruments Incorporated 1 Layout Considerations 5 www.ti.com Layout Considerations The layout of the evaluation board requires some attention. For decoupling the supply lines, it is suggested that 10 nF capacitors be placed as close as possible to the op amp. For single supply, place a capacitor between V+ and V−. For dual supplies, place one capacitor between V+ and the board ground, and a second capacitor between ground and V−. On the LMV831 evaluation board, the decoupling of the negative pin V− is implemented by a capacitor between V+ and V−. This is done for easy routing and to keep connections to the pins short. Even with the LMV831/LMV832/LMV834's inherent hardening against EMI, it is still recommended to keep the input traces short and as far as possible from RF sources. Then the RF signals entering the chip are as low as possible, and the remaining EMI can be, almost, completely eliminated in the chip by the EMI reducing features of the LMV831/LMV832/LMV834. 6 Measurement Procedure The measurement procedure is the same for all test circuits. To measure the input referred offset voltage shift needed for calculating the EMIRR, the following procedure can be used: 1. Measure VOUT when the RF signal is off. 2. Measure VOUT when the RF signal is on. 3. Translate measured VOUT voltages to input referred voltages. Translation is one-to-one in this case since the gain is one in the IN+ test setup. 4. Subtract the two measured input referred voltages. 5. Verify if the offset shift is above the noise level of the op amp setup and the op amp is not saturated. If this is not the case choose another RF level and start the procedure again. 6. Calculate the EMIRR. 7. If needed, transform the results to an EMIRR based on a 100 mVP RF signal. 7 Measurement Results To show the sensitivity of the IN+ pin, two types of measurement results are presented using the LMV831 evaluation board: • The EMIRR as a function of the frequency of the applied signal. The level of the signal is set to the standard level of 100 mVP (−20 dBVP). • The EMIRR as a function of the level of the applied signal. The frequency is set to four typical values: 400 MHz, 900 MHz, 1.8 GHz, and 2.4 GHz. 7.1 EMIRR Vs. Frequency Figure 1 shows the EMIRR versus frequency for the various temperatures. The measurement is performed with a fixed RF level of −20 dBVP and a varying RF signal frequency. The frequency range is 10 MHz to 10 GHz. 2 AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Measurement Results EMIRR V_PEAK (dB) www.ti.com 125°C 140 130 120 110 100 90 80 70 60 50 40 30 20 85°C 25°C -40°C + V = 3.3V, 5.0V VPEAK = -20 dBVp 10 100 1000 10000 FREQUENCY (MHz) Figure 1. EMIRR vs. Frequency 7.2 EMIRR Vs. Power Figure 2 shows the EMIRR as a function of power at four typical frequencies. EMIRRV_PEAK (dB) 2400 MHz 140 130 120 110 100 90 80 70 60 50 40 30 20 400 MHz 900MHz 1800 MHz -40 -30 -20 -10 0 10 RF INPUT PEAK VOLTAGE (dBVp) Figure 2. EMIRR vs. Power In this figure two areas can be distinguished. At the left side of the figure, the EMIRR increases as a function of input level; whereas at the right side the EMIRR decreases as a function of the input level. The left side of the figure is actually an artifact resulting from the limited accuracy of the measurement setup. For the relatively low input levels, the resulting offset voltage shift is well below the noise level. Thus, when calculating the EMIRR for that region, the ratio of the input level to the noise level is depicted. As the noise level is constant for the setup, an increasing EMIRR is obtained for increasing input signal level. For the right side, the obtained offset-shift is well above the noise level. As the relation between offset voltage shift and RF input level is quadratic, the ratio as used in the EMIRR is inversely proportional to the RF input level, which is in line with the displayed slope of “−1”. SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 Copyright © 2008–2013, Texas Instruments Incorporated 3 Bill Of Materials 8 www.ti.com Bill Of Materials The Bill of Materials (BOM) of the LMV831 evaluation board is given in Table 1. Table 1. LMV831 Bill Of Materials Designator Description Comment C1, C3 0603 Capacitor 100 pF C2 0603 Capacitor 22 pF C4, C5 Case_B Capacitor 10 µF P1 Connector Banana P2 Connector SMA P3 Connector BNC P4 Connector Banana P5 Connector Banana R1, R2 0603 Resistor 100Ω U1 SC70 LMV831 The Bill of Materials (BOM) of the LMV832 evaluation board is given in Table 2. Table 2. LMV832 Bill Of Materials Designator Description Comment C1, C2 0603 Capacitor 22 pF C3, C4 0603 Capacitor 100 pF C5, C6 Case_B Capacitor 10 µF P1, P2 Connector SMA P3, P4 Connector BNC P5 Connector Banana P6 Connector Banana P7 Connector Banana R1, R2, R3, R4 0603 Resistor 100Ω U1 MSOP LMV832 The Bill of Materials (BOM) of the LMV834 evaluation board is given in Table 3. Table 3. LMV834 Bill Of Materials 4 Designator Description Comment C1, C3 0603 Capacitor 100 pF C2, C4 Case_B Capacitor 10 µF C5, C6, C7, C8 0603 Capacitor 22 pF P1 Connector Banana P2 Connector Banana P3 Connector Banana P4, P5, P6, P7 Connector SMA P8, P9, P10, P11 Connector BNC R1, R2, R3, R4, R5, R6, R7, R8 0603 Resistor 100Ω U1 TSSOP LMV834 AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated LMV831 Evaluation Board www.ti.com 9 LMV831 Evaluation Board C4 10 µF + P1 VDD C1 100 pF P2 R1 RFin 100: 1 R2 3 100: U1 P3 + LMV831 Out - 4 5 2 C2 C3 22 pF 100 pF P5 GND VSS + P4 C5 10 µF Figure 3. Schematic for LMV831, Coupling RF Signal to the IN+ Pin SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 Copyright © 2008–2013, Texas Instruments Incorporated 5 LMV831 Evaluation Board www.ti.com Figure 4. Layout for LMV831, All Layers Figure 5. Layout for LMV831, Silk Screen 6 AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated LMV832 Evaluation Board www.ti.com 10 LMV832 Evaluation Board P1 RFin R1 P2 U1:A 100: 3 R2 2 100: P3 LMV832 + RFin Out 1 U1:B R3 100: 5 R4 - 6 100: C1 C2 22 pF 22 pF LMV832 + P4 Out 7 - P5 V + P6 GND P7 - V C3 + C5 100 pF C4 100 pF U1 - pin 8 10 µF + C6 10 µF U1 - pin 4 Figure 6. Schematic for LMV832, Coupling RF Signal to the IN+ Pin SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 Copyright © 2008–2013, Texas Instruments Incorporated 7 LMV832 Evaluation Board www.ti.com Figure 7. Layout for LMV832, All Layers Figure 8. Layout for LMV832, Silk Screen 8 AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated LMV834 Evaluation Board www.ti.com 11 LMV834 Evaluation Board P4 RFin R1 100: 3 R2 2 100: P5 RFin P7 U1:A P8 LMV834 + RFin Out U1:D R7 100: 12 1 R8 - 13 100: C5 C8 22 pF 22 pF R3 P6 U1:B 100: 5 R4 6 100: P9 LMV834 + RFin Out 100: 10 9 100: C6 C7 22 pF 22 pF P2 GND - - P10 LMV834 + Out 8 - P1 V V Out 7 U1:C R6 + + R5 7 - P11 LMV834 P3 C1 100 pF C3 100 pF + C2 10 µF U1 - pin 4 + C4 10 µF U1 - pin 11 Figure 9. Schematic for LMV834, Coupling RF Signal to the IN+ Pin SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 Copyright © 2008–2013, Texas Instruments Incorporated 9 LMV834 Evaluation Board www.ti.com Figure 10. Layout for LMV834, All Layers Figure 11. Layout for LMV834, Silk Screen 10 AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 SNOA530A – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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