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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
LMV98x-N Small, Low-Power, 1.8-V RRIO Operational Amplifiers With Shutdown
1 Features
3 Description
•
•
LMV98x-N are low-voltage, low-power operational
amplifiers. LMV98x-N operate from 1.8-V to 5-V
supply voltages and have rail-to-rail input and output.
LMV98x-N input common mode voltage extends
200mV beyond the supplies which enables user
enhanced functionality beyond the supply voltage
range. The output can swing rail-to-rail unloaded and
within 105 mV from the rail with 600-Ω load at 1.8-V
supply. LMV98x-N are optimized to work at 1.8 V,
which makes them ideal for portable two-cell battery
powered systems and single cell Li-Ion systems.
1
•
•
•
•
•
•
•
•
•
Ensured 1.8-V, 2.7-V, and 5-V Specifications
Output Swing:
– 600-Ω Load: 80-mV from Rail
– 2-kΩ Load: 30-mV from Rail
VCM 200 mV Beyond Rails
Supply Current (Per Channel): 100 µA
Gain Bandwidth Product: 1.4 MHz
Maximum VOS: 4 mV
Gain with 600-Ω Load: 101 dB
Ultra-Small Package: DSBGA 1.0 mm × 1.5 mm
Turnon Time from Shutdown: 19 µs
Independent Shutdown on Dual
Temperature Range: −40°C to 125°C
2 Applications
•
•
•
•
•
•
•
•
•
Industrial and Automotive
Consumer Communication
Fitness Trackers
Wearables
Mobile Phones
Portable Audio
Portable and Battery-Powered Electronic
Equipment
Supply Current Monitoring
Battery Monitoring
Typical Application
LMV98x-N offer a shutdown pin that can be used to
disable the device and reduce the supply current. The
device is in shutdown when the SHDN pin is low. The
output is high impedance in shutdown.
LMV98x-N exhibit excellent speed-power ratio,
achieving 1.4-MHz gain bandwidth product at 1.8-V
supply voltage with low supply current. LMV98x-N are
capable of driving a 600-Ω load and up to 1000-pF
capacitive load with minimal ringing. LMV98x-N have
a high DC gain of 101 dB, making them suitable for
low frequency applications.
Device Information(1)
PART NUMBER
LMV981-N
LMV982-N
PACKAGE
BODY SIZE (NOM)
DSBGA (6)
1.50 mm × 1.30 mm
SC70 (6)
2.00 mm × 1.25 mm
SOT-23 (6)
2.90 mm × 1.60 mm
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V+
+
R1
2 NŸ
RSENSE
0.2 Ÿ
R2
2 NŸ
±
Q1
2N3906
+
VOUT
Load
R3
10 NŸ
ICHARGE
VOUT
RSENSE u R3
R1
u ICHARGE
1: u ICHARGE
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics – DC, 1.8 V....................... 6
Electrical Characteristics – AC, 1.8 V ....................... 7
Electrical Characteristics – DC, 2.7 V....................... 8
Electrical Characteristics – AC, 2.7 V ....................... 9
Electrical Characteristics – DC, 5 V........................ 10
Electrical Characteristics – AC, 5 V ...................... 11
Typical Characteristics .......................................... 12
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Applications ............................................... 20
9.3 Do's and Don'ts ...................................................... 23
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (March 2013) to Revision M
Page
•
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
•
Changed RθJA values for LMV981-N: YZR (DSBGA) From: 286 To: 138.2 ........................................................................... 5
•
Changed RθJA values for LMV981-N: DCK (SC70) From: 286 To: 229.1............................................................................... 5
•
Changed RθJA values for LMV981-N: DBV (SOT-23) From: 286 To: 209.9 ........................................................................... 5
•
Changed RθJA values for LMV982-N: DGS (VSSOP) From: 286 To: 182.8 ........................................................................... 5
Changes from Revision K (March 2013) to Revision L
•
2
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
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Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: LMV981-N LMV982-N
LMV981-N, LMV982-N
www.ti.com
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
5 Description (continued)
LMV981-N is offered in space-saving, 6-pin DSBGA, SC70, and SOT-23 packages. The 6-pin DSBGA package
has only a 1.006 mm × 1.514 mm × 0.945 mm footprint. LMV982-N is offered in a space-saving, 10-pin VSSOP
package. These small packages are ideal solutions for area constrained PCBs and portable electronics such as
cellular phones and PDAs.
6 Pin Configuration and Functions
YZR Package
6-Pin DSBGA
Top View
V+
SHDN
+IN
A1
B1
C1
A2
B2
C2
DCK or DBV Package
6-Pin SC70 or SOT-23
Top View
OUT
+IN
V-
1
V-
2
-IN
3
6
+
V+
5 SHDN
4
OUT
-IN
Pin Functions: LMV981-N
PIN
NAME
DSBGA
SC70, SOT-23
+IN
C1
1
–IN
C2
OUT
A2
SHDN
TYPE (1)
DESCRIPTION
I
Noninverting input
3
I
Inverting input
4
O
Output
B1
5
I
Shutdown input
V+
A1
6
P
Positive (highest) power supply
V–
B2
2
P
Negative (lowest) power supply
(1)
I = Input, O = Output, P = Power
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: LMV981-N LMV982-N
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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
www.ti.com
DGS Package
10-Pin VSSOP
Top View
OUT A
1
10 V+
-IN A
2
9
OUT B
+IN A
3
8
-IN B
V-
4
7
+IN B
6
SHDN B
+
+
SHDN A
5
Pin Functions: LMV982-N
PIN
TYPE (1)
DESCRIPTION
NAME
VSSOP
+IN A
3
I
Noninverting input, channel A
+IN B
7
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
8
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
9
O
Output, channel B
SHDN A
5
I
Shutdown input, channel A
SHDN B
6
I
Shutdown input, channel B
V+
10
P
Positive (highest) power supply
V–
4
P
Negative (lowest) power supply
(1)
4
I = Input, O = Output, P = Power
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Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: LMV981-N LMV982-N
LMV981-N, LMV982-N
www.ti.com
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Supply voltage (V+ – V −)
Differential input voltage
Junction temperature (3)
Storage temperature, Tstg
(2)
(3)
UNIT
5.5
V
±Supply voltage
V++ 0.3
Voltage at input/output pins
(1)
MAX
–65
V– - 0.3
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see TI application report, Absolute Maximum Ratings for Soldering (SNOA549).
The maximum power dissipation is a function of TJ(MAX) , RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX)–TA)/RθJA. All numbers apply for packages soldered directly into a PCB.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Machine model (2)
±200
UNIT
V
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process.
Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Supply voltage
1.8
5
UNIT
V
Temperature
–40
125
°C
7.4 Thermal Information
LMV981-N
THERMAL METRIC
(1)
LMV982-N
YZR
(DSBGA)
DCK
(SC70)
DBV
(SOT-23)
DGS
(VSSOP)
6 PINS
6 PINS
6 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
138.2
229.1
209.9
182.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.2
116.1
181.2
73.1
°C/W
RθJB
Junction-to-board thermal resistance
23.4
53.3
53.2
103.3
°C/W
ψJT
Junction-to-top characterization parameter
5
8.8
55.5
12.8
°C/W
ψJB
Junction-to-board characterization parameter
23.2
52.7
52.6
101.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: LMV981-N LMV982-N
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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
www.ti.com
7.5 Electrical Characteristics – DC, 1.8 V
TJ = 25°C, V+ = 1.8 V, V– = 0 V, VCM = V+/2, VO = V+/2, RL > 1 MΩ, and SHDN tied to V+ (unless otherwise noted) (1)
PARAMETER
LMV981-N (single)
VOS
Input offset voltage
Input offset voltage
average drift
IB
Input bias current
IOS
Input offset current
TJ = 25°C
TYP (3)
MAX (2)
1
4
1
5.5
TJ = –40°C to 125°C
6
TJ = 25°C
LMV982-N (dual)
TCVOS
MIN (2)
TEST CONDITIONS
TJ = –40°C to 125°C
5.5
TJ = 25°C
15
TJ = –40°C to 125°C
13
TJ = –40°C to 125°C
TJ = –40°C to 125°C
CMRR
Common mode rejection
ratio
Power supply rejection
ratio
LMV981-N
(single)
LMV982-N
(dual)
TJ = 25°C
0.156
TJ = –40°C to 125°C
0.178
TJ = –40°C to 125°C
Input common-mode
voltage
LMV981-N, 0 V ≤ VCM ≤ 0.6 V,
1.4 V ≤ VCM ≤ 1.8 V (4)
TJ = –40°C to 125°C
55
LMV982, 0 V ≤ VCM ≤ 0.6 V,
1.4 V ≤ VCM ≤ 1.8 V (4)
TJ = 25°C
55
TJ = –40°C to 125°C
50
For CMRR range ≥ 50 dB
Large signal voltage gain
LMV981-N (single)
TJ = 25°C
75
100
TJ = –40°C to 125°C
70
V− − 0.2
Large signal voltage gain
LMV982-N (dual)
(1)
(2)
(3)
(4)
6
dB
dB
–0.2
2.1
V+ + 0.2
−
V+
V− + 0.2
V+ − 0.2
V
RL = 600 Ω to 0.9 V,
VO = 0.2 V to 1.6 V, VCM = 0.5 V
TJ = 25°C
77
TJ = –40°C to 125°C
73
RL = 2 kΩ to 0.9 V,
VO = 0.2 V to 1.6 V, VCM = 0.5 V
TJ = 25°C
80
TJ = –40°C to 125°C
75
RL = 600 Ω to 0.9 V,
VO = 0.2 V to 1.6 V, VCM = 0.5 V
TJ = 25°C
75
TJ = –40°C to 125°C
72
RL = 2 kΩ to 0.9 V,
VO = 0.2 V to 1.6 V, VCM = 0.5 V
TJ = 25°C
78
TJ = –40°C to 125°C
75
AV
3.5
76
72
TA = 125°C
µA
78
50
TA = –40°C to 85°C
1
5
60
TA = 25°C
CMVR
nA
185
2
TJ = 25°C
1.8 V ≤ V+ ≤ 5 V
25
nA
205
TJ = 25°C
–0.2 V ≤ VCM ≤ 0 V, 1.8 V ≤ VCM ≤ 2 V
PSRR
35
40
103
In shutdown
µV/°C
50
TJ = 25°C
Supply current
(per channel)
mV
7.5
TJ = 25°C
IS
UNIT
V
101
105
dB
90
100
dB
Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the
electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicated junction temperature limits
beyond which the device may be permanently degraded, either mechanically or electrically.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
For ensured temperature ranges, see input common-mode voltage range specifications.
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Product Folder Links: LMV981-N LMV982-N
LMV981-N, LMV982-N
www.ti.com
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
Electrical Characteristics – DC, 1.8 V (continued)
TJ = 25°C, V+ = 1.8 V, V– = 0 V, VCM = V+/2, VO = V+/2, RL > 1 MΩ, and SHDN tied to V+ (unless otherwise noted)(1)
PARAMETER
RL = 600 Ω to 0.9 V,
VIN = ±100 mV
VO
MIN (2)
TEST CONDITIONS
1.65
TJ = 25°C
RL = 2 kΩ to 0.9 V,
VIN = ±100 mV
IO
Sourcing, VO = 0 V,
VIN = 100 mV
Sinking, VO = 1.8 V,
VIN = –100 mV
TJ = 25°C
7
TJ = –40°C to 125°C
5
VSHDN
3.3
mA
9
19
Turnon voltage to enable
part
µs
1
Turnoff voltage
(5)
0.035
8
Turnon time from
shutdown
Ton
V
0.04
4
TJ = –40°C to 125°C
0.105
1.77
1.74
TJ = 25°C
UNIT
0.12
0.024
TJ = –40°C to 125°C
Output short circuit
current (5)
1.63
1.75
TJ = 25°C
MAX (2)
1.72
0.077
TJ = –40°C to 125°C
Output swing
TYP (3)
V
0.55
Applies to both single-supply and split-supply operation. Continuous short-circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely
affect reliability.
7.6 Electrical Characteristics – AC, 1.8 V
TJ = 25°C, V+ = 1.8 V, V– = 0 V, VCM = V+/2, VO = V+/2, RL > 1 MΩ, and SHDN tied to V+ (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
SR
Slew rate (4)
GBW
Φm
Gm
Gain margin
en
Input-referred voltage noise
f = 10 kHz, VCM = 0.5 V
in
Input-referred current noise
f = 10 kHz
Total harmonic distortion
f = 1 kHz, AV = +1, RL = 600 Ω,
VIN = 1 VPP
THD
(2)
(3)
(4)
(5)
TYP (3)
MAX (2)
UNIT
0.35
V/µs
Gain-bandwidth product
1.4
MHz
Phase margin
67
°
7
dB
60
nV/√Hz
0.08
pA/√Hz
Amp-to-amp isolation (5)
(1)
MIN (2)
0.023%
123
dB
Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the
electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicated junction temperature limits
beyond which the device may be permanently degraded, either mechanically or electrically.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates.
Input referred, RL = 100 kΩ connected to V+/ 2. Each amp excited in turn with 1 kHz to produce VO = 3 VPP (for supply voltages < 3 V,
VO = V+).
Copyright © 2001–2016, Texas Instruments Incorporated
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SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
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7.7 Electrical Characteristics – DC, 2.7 V
TJ = 25°C, V+ = 2.7 V, V– = 0 V, VCM = V+/2, VO = V+/2, RL > 1 MΩ, and SHDN tied to V+ (unless otherwise noted) (1)
PARAMETER
LMV981-N (single)
VOS
Input offset voltage
LMV982-N (dual)
TCVOS
Input offset voltage average
drift
IB
Input bias current
IOS
Input offset current
MIN (2)
TEST CONDITIONS
TJ = 25°C
TYP (3)
MAX (2)
1
4
TJ = –40°C to 125°C
6
TJ = 25°C
1
TJ = –40°C to 125°C
5.5
TJ = 25°C
15
TJ = –40°C to 125°C
TJ = 25°C
8
TJ = –40°C to 125°C
TJ = –40°C to 125°C
Supply current
(per channel)
CMRR
Common mode rejection
ratio
LMV981-N
(single)
LMV982-N
(dual)
TJ = 25°C
0.061
TJ = –40°C to 125°C
Power supply rejection ratio
0.101
LMV981-N, 0 V ≤ VCM ≤ 1.5 V,
2.3 V ≤ VCM ≤ 2.7 V (4)
60
TJ = –40°C to 125°C
55
LMV982, 0 V ≤ VCM ≤ 1.5 V,
2.3 V ≤ VCM ≤ 2.7 V (4)
TJ = 25°C
55
TJ = –40°C to 125°C
50
Input common mode
voltage
For CMRR Range ≥ 50 dB
TJ = 25°C
75
100
TJ = –40°C to 125°C
70
V− − 0.2
Large signal voltage gain
LMV982-N (dual)
(1)
(2)
(3)
(4)
8
µA
3.5
dB
dB
–0.2
3
TA = −40°C to 85°C
1
V+ + 0.2
−
V+
V− + 0.2
V+ − 0.2
V
RL = 600 Ω to 1.35 V,
VO = 0.2 V to 2.5 V
TJ = 25°C
87
TJ = –40°C to 125°C
86
RL = 2 kΩ to 1.35 V,
VO = 0.2 V to 2.5 V
TJ = 25°C
92
TJ = –40°C to 125°C
91
RL = 600 Ω to 1.35 V,
VO = 0.2 V to 2.5 V
TJ = 25°C
78
TJ = –40°C to 125°C
75
RL = 2 kΩ to 1.35 V,
VO = 0.2 V to 2.5 V
TJ = 25°C
81
TJ = –40°C to 125°C
78
AV
190
80
74
TA = 125°C
Large signal voltage gain
LMV981-N (single)
nA
81
50
TA = 25°C
CMVR
nA
5
TJ = 25°C
1.8 V ≤ V+ ≤ 5 V, VCM = 0.5 V
25
2
TJ = –40°C to 125°C
−0.2 V ≤ VCM ≤ 0 V, 2.7 V ≤ VCM ≤ 2.9 V
PSRR
mV
210
TJ = 25°C
In shutdown
35
40
105
mV
µV/°C
50
TJ = 25°C
IS
6
7.5
UNIT
V
104
110
90
dB
100
Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the
electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicated junction temperature limits
beyond which the device may be permanently degraded, either mechanically or electrically.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
For ensured temperature ranges, see input common mode voltage range specifications.
Submit Documentation Feedback
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: LMV981-N LMV982-N
LMV981-N, LMV982-N
www.ti.com
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
Electrical Characteristics – DC, 2.7 V (continued)
TJ = 25°C, V+ = 2.7 V, V– = 0 V, VCM = V+/2, VO = V+/2, RL > 1 MΩ, and SHDN tied to V+ (unless otherwise noted)(1)
PARAMETER
RL = 600 Ω to 1.35 V,
VIN = ±100 mV
VO
MIN (2)
TEST CONDITIONS
2.55
TJ = 25°C
RL = 2 kΩ to 1.35 V,
VIN = ±100 mV
2.53
2.65
TJ = 25°C
Output short circuit
current (5)
IO
TJ = 25°C
20
TJ = –40°C to 125°C
15
Sinking, VO = 0 V,
VIN = –100 mV
TJ = 25°C
18
TJ = –40°C to 125°C
12
V
0.04
0.045
30
mA
25
Ton
Turnon time from shutdown
VSHDN
Turnon voltage to enable
part
1.9
Turnoff voltage
0.8
(5)
0.11
2.675
2.64
Sourcing, VO = 0 V,
VIN = 100 mV
UNIT
0.13
0.025
TJ = –40°C to 125°C
MAX (2)
2.62
0.083
TJ = –40°C to 125°C
Output swing
TYP (3)
12.5
µs
V
Applies to both single-supply and split-supply operation. Continuous short-circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely
affect reliability.
7.8 Electrical Characteristics – AC, 2.7 V
TJ = 25°C, V+ = 2.7 V, V − = 0 V, VCM = 1 V, VO = 1.35 V, RL > 1 MΩ, and SHDN tied to V+ (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
(4)
MIN (2)
TYP (3)
MAX (2)
UNIT
SR
Slew rate
GBW
Gain-bandwidth product
Φm
Phase margin
70
°
Gm
Gain margin
7.5
dB
en
Input-referred voltage noise
f = 10 kHz, VCM = 0.5 V
57
nV/√Hz
in
Input-referred current noise
f = 10 kHz
0.08
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = +1, RL = 600 Ω,
VIN = 1 VPP
THD
Amp-to-amp isolation (5)
(1)
(2)
(3)
(4)
(5)
0.4
V/µs
1.4
MHz
0.022%
123
dB
Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the
electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicated junction temperature limits
beyond which the device may be permanently degraded, either mechanically or electrically.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates.
Input referred, RL = 100 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 3 VPP (for supply voltages < 3 V,
VO = V+).
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7.9 Electrical Characteristics – DC, 5 V
TJ = 25°C, V+ = 5 V, V − = 0 V, VCM = V+/2, VO = V+/2, RL > 1 MΩ, and SHDN tied to V+ (unless otherwise noted) (1)
PARAMETER
LMV981-N (single)
VOS
Input offset voltage
LMV982-N (dual)
TCVOS
Input offset voltage
average drift
IB
Input bias current
IOS
Input offset current
MIN (2)
TEST CONDITIONS
TJ = 25°C
TYP (3)
MAX (2)
1
4
1
5.5
TJ = –40°C to 125°C
6
TJ = 25°C
TJ = –40°C to 125°C
5.5
TJ = 25°C
14
TJ = –40°C to 125°C
9
TJ = –40°C to 125°C
TJ = –40°C to 125°C
CMRR
Common mode rejection
ratio (4)
TJ = 25°C
LMV982-N
(dual)
TJ = 25°C
0.201
TJ = –40°C to 125°C
Power supply rejection
ratio
1.8 V ≤ V+ ≤ 5 V,
VCM = 0.5 V
TJ = –40°C to 125°C
Input common mode
voltage
For CMRR range ≥ 50 dB
60
TJ = –40°C to 125°C
55
Large signal voltage gain
LMV981-N (single)
TJ = 25°C
75
100
TJ = –40°C to 125°C
70
V− − 0.2
Large signal voltage gain
LMV982-N (dual)
VO
RL = 2 kΩ to 2.5 V,
VO = 0.2 V to 4.8 V
TJ = 25°C
94
TJ = –40°C to 125°C
93
RL = 600 Ω to 2.5 V,
VO = 0.2 V to 4.8 V
TJ = 25°C
81
TJ = –40°C to 125°C
78
RL = 2 kΩ to 2.5 V,
VO = 0.2 V to 4.8 V
TJ = 25°C
85
Output swing
RL = 2 kΩ to 2.5 V,
VIN = ±100 mV
(2)
(3)
(4)
10
102
dB
113
90
dB
100
4.89
0.12
4.835
4.945
TJ = 25°C
V
82
4.855
4.935
0.16
0.18
4.967
0.037
TJ = –40°C to 125°C
(1)
V+ − 0.3
87
TJ = –40°C to 125°C
V+ + 0.2
V− + 0.3
88
TJ = 25°C
µA
dB
V+
TJ = –40°C to 125°C
RL = 600 Ω to 2.5 V,
VIN = ±100 mV
3.5
V−
TJ = 25°C
TJ = –40°C to 125°C
1
–0.2
5.3
RL = 600 Ω to 2.5 V,
VO = 0.2 V to 4.8 V
AV
µA
dB
78
TA = 125°C
nA
86
50
TA = −40°C to 85°C
nA
5
TJ = 25°C
TA = 25°C
CMVR
210
2
0.302
−0.2 V ≤ VCM ≤ 0 V, 5 V ≤ VCM ≤ 5.2 V
PSRR
25
230
LMV981-N
(single)
0 V ≤ VCM ≤ 3.8 V,
4.6 V ≤ VCM ≤ 5 V
35
40
116
In shutdown
µV/°C
50
TJ = 25°C
Supply current (per
channel)
mV
7.5
TJ = 25°C
IS
UNIT
V
0.065
0.075
Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the
electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicated junction temperature limits
beyond which the device may be permanently degraded, either mechanically or electrically.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
For ensured temperature ranges, see input common mode voltage range specifications.
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Electrical Characteristics – DC, 5 V (continued)
TJ = 25°C, V+ = 5 V, V − = 0 V, VCM = V+/2, VO = V+/2, RL > 1 MΩ, and SHDN tied to V+ (unless otherwise noted)(1)
PARAMETER
Output short-circuit
current (5)
IO
Ton
VSHDN
(5)
TEST CONDITIONS
MIN (2)
TYP (3)
100
LMV981-N, sourcing,
VO = 0 V, VIN = 100 mV
TJ = 25°C
80
TJ = –40°C to 125°C
68
Sinking, VO = 5 V,
VIN = −100 mV
TJ = 25°C
58
TJ = –40°C to 125°C
45
MAX (2)
UNIT
mA
65
Turnon time from
shutdown
8.4
Turnon voltage to enable
part
4.2
Turnoff voltage
0.8
µs
V
Applies to both single-supply and split-supply operation. Continuous short-circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely
affect reliability.
7.10 Electrical Characteristics – AC, 5 V
TJ = 25°C, V+ = 5 V, V − = 0 V, VCM = V+/2, VO = 2.5 V, R L > 1 MΩ, and SHDN tied to V+ (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN (2)
(4)
TYP (3)
MAX (2)
UNIT
SR
Slew rate
0.42
V/µs
GBW
Gain-bandwidth product
1.5
MHz
Φm
Phase margin
71
°
Gm
Gain margin
8
dB
en
Input-referred voltage noise
f = 10 kHz, VCM = 1 V
50
nV/√Hz
in
Input-referred current noise
f = 10 kHz
0.08
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = +1, RL = 600 Ω,
VO = 1 V PP
THD
Amp-to-amp isolation (5)
(1)
(2)
(3)
(4)
(5)
0.022%
123
dB
Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the
electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicated junction temperature limits
beyond which the device may be permanently degraded, either mechanically or electrically.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Connected as voltage follower with input step from V– to V+. Number specified is the slower of the positive and negative slew rates.
Input referred, RL = 100 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 3 VPP (for supply voltages < 3 V,
VO = V+).
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7.11 Typical Characteristics
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
100
160
125°C
VS = 5V
10
120
ISOURCE (mA)
SUPPLY CURRENT (éA)
140
85°C
100
25°C
80
-40°C
60
VS = 2.7V
1
VS = 1.8V
40
0.1
20
1
2
3
4
0.01
0.001
5
SUPPLY VOLTAGE (V)
Figure 1. Supply Current vs Supply Voltage (LMV981-N)
OUTPUT VOLTAGE PROXIMITY TO SUPPLY
VOLTAGE (mV ABSOLUTE VALUE)
VS = 5V
ISINK (mA)
10
VS = 2.7V
1
VS = 1.8V
0.01
0.001
0.01
0.1
10
1
Figure 3. Sinking Current vs Output Voltage
10
RL = 600:
130
NEGATIVE SWING
120
110
100
90
80
POSITIVE SWING
70
60
1
0
4
2
3
SUPPLY VOLTAGE (V)
5
6
Figure 4. Output Voltage Swing vs Supply Voltage
135.
0
60
45
VS = 1.8V
RL = 2k:
CL = 1000pF
50 RL = 600:
40
PHASE
40
NEGATIVE SWING
GAIN (dB)
OUTPUT VOLTAGE PROXIMITY TO
SUPPLY VOLTAGE (mV ABSOLUTE VALUE)
1
140
OUTPUT VOLTAGE REF TO GND (V)
35
30
20
1
2
3
5
4
6
30
67.5
GAIN
20
45.
0
22.5
CL = 1000pF
CL = 300pF
CL = 0pF
-10
10k
100k
SUPPLY VOLTAGE (V)
Figure 5. Output Voltage Swing vs Supply Voltage
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90.0
CL = 0pF
0
POSITIVE SWING
112.5
CL = 300pF
10
25
0
12
0.1
Figure 2. Sourcing Current vs Output Voltage
100
0.1
0.01
OUTPUT VOLTAGE REFERENCED TO V+ (V)
PHASE (°)
0
0
0.
0
1M
10
M
-22.5
FREQUENCY (Hz)
Figure 6. Gain and Phase vs Frequency
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Typical Characteristics (continued)
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
60
135.0
60
112.5
50
VS = 5.0V
CL = 1000pF
GAIN (dB)
67.5
GAIN
45.0
10
100k
1M
30
-40°C
GAIN
10
0.0
0
-22.5
10
M
-10
10k
50
125°C
100k
10
M
1M
-22.5
Figure 8. Gain and Phase vs Frequency
VS = 5.0V
135.
0
RL = 600:
112.5
90
VS = 5V
85
CL = 150pF
90.0
67.5
-40°C
25°C
85°C
20
GAIN
45.
0
125°C
10
-40°C
-10
10k
100k
10
M
1M
VS = 2.7V
75
VS = 1.8V
70
22.5
25°C
85°C
125°C
0
80
CMRR (dB)
30
PHASE (°)
PHASE
GAIN (dB)
0.
0
FREQUENCY (Hz)
40
0.
0
65
-22.5
60
1k
100
FREQUENCY (Hz)
10
FREQUENCY (Hz)
100
1000
VS = 5V
INPUT VOLTAGE NOISE (nV/ Hz)
+PSRR
90
80
70
-PSRR
60
50
40
30
10
10k
Figure 10. CMRR vs Frequency
Figure 9. Gain and Phase vs Frequency
PSRR (dB)
45.
0
22.5
-40°C
25°C
85°C
FREQUENCY (Hz)
Figure 7. Gain and Phase vs Frequency
60
67.5
25°C
85°C
125°C
20
22.5
CL = 1000pF
CL = 300pF
CL = 0pF
-10
10k
90.0
PHASE
30
0
112.5
40
90.0
CL = 0pF
20
RL = 600:
PHASE (°)
CL = 300pF
GAIN (dB)
PHASE
40
135.
0
CL = 150pF
PHASE (°)
50 RL = 600:
VS = 1.8V
100
1k
FREQUENCY (Hz)
10k
100
10
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 11. PSRR vs Frequency
Figure 12. Input Voltage Noise vs Frequency
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Typical Characteristics (continued)
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
10
1
1
THD (%)
INPUT CURRENT NOISE (pA/ Hz)
RL = 600:
AV = +1
0.1
1.8V
0.1
2.7V
5V
0.01
10
100
1k
10k
0.01
10
100k
10k
1k
100
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
Figure 14. THD vs Frequency
Figure 13. Input Current Noise vs Frequency
0.5
10
RL = 600:
AV = +10
SLEW RATE (V/Ps)
0.45
THD (%)
1
5V
0.1
FALLING EDGE
0.4
RISING EDGE
0.35
RL = 2k:
0.3
1.8V
AV = +1
2.7V
0.01
10
VIN = 1VPP
0.25
100
1k
10k
0
100k
1
3
4
5
6
RL = 2 k:
VS = 2.7V
RL = 2 k:
(50 mV/DIV)
INPUT SIGNAL
VS = 1.8V
Figure 16. Slew Rate vs Supply Voltage
OUTPUT SIGNAL
INPUT SIGNAL
OUTPUT SIGNAL
(50 mV/DIV)
Figure 15. THD vs Frequency
14
2
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
TIME (2.5 Ps/DIV)
TIME (2.5 Ps/DIV)
Figure 17. Small-Signal Noninverting Response
Figure 18. Small-Signal Noninverting Response
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Typical Characteristics (continued)
VIN
VS = 5V
(900 mV/div)
RL = 2 k:
(50 mV/DIV)
OUTPUT SIGNAL
INPUT SIGNAL
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
VOUT
VS = 1.8V
RL = 2k:
AV = +1
TIME (10 Ps/div)
TIME (2.5 Ps/DIV)
Figure 19. Small-Signal Noninverting Response
Figure 20. Large-Signal Noninverting Response
VIN
(2.5 V/div)
(1.35V/DIV)
VIN
VOUT
VOUT
VS = 2.7V
VS = 5.0V
RL = 2 k:
RL = 2k:
AV = +1
AV = +1
TIME (10 Ps/div)
TIME (10 Ps/DIV)
Figure 21. Large-Signal Noninverting Response
Figure 22. Large-Signal Noninverting Response
90
90
SHORT CIRCUIT CURRENT (mA)
SHORT CIRCUIT CURRENT (mA)
5V
80
5V
70
60
50
40
2.7V
30
20
1.8V
10
0
-40
110
10
60
TEMPERATURE
(°C)
Figure 23. Short-Circuit Current vs Temperature (Sinking)
80
70
60
50
40
2.7V
30
20
1.8V
10
0
-40
10
60
TEMPERATURE
(°C)
110
Figure 24. Short-Circuit Current vs Temperature (Sourcing)
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Typical Characteristics (continued)
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
3
3
VS = 1.8V
VS = 2.7V
2.5
2.5
2
2
25°C
-40°C
1.5
VOS (mV)
VOS (mV)
25°C
1
0.5
85°C
1
0.5
85°C
125°C
125°C
0
0
-0.5
-0.5
-1
-0.4
0
0.4
0.8
-40°C
1.5
1.2
2
1.6
-1
-0.4
2.4
0.1
0.6
VCM (V)
1.1
1.6
2.1
2.6
3.1
VCM (V)
Figure 25. Offset Voltage vs Common Mode Range
Figure 26. Offset Voltage vs Common Mode Range
3
VS = 5V
2.5
2
VOS (mV)
-40°C
1.5
1
0.5
125°C
25°C
85°C
0
-0.5
-1
-0.4
0.6
1.6
2.6
3.6
4.6
5.6
VCM (V)
Figure 27. Offset Voltage vs Common Mode Range
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8 Detailed Description
8.1 Overview
The LMV98x-N are low-voltage, low-power operational amplifiers (op-amp) operating from 1.8-V to 5.5-V supply
voltages and have rail-to-rail input and output with shutdown. LMV98x-N input common-mode voltage extends
200 mV beyond the supplies which enables user enhanced functionality beyond the supply voltage range.
8.2 Functional Block Diagram
V
IN –
IN +
+
_
OUT
+
V
–
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(each amplifier)
8.3 Feature Description
The differential inputs of the amplifier consist of a noninverting input (+IN) and an inverting input (–IN). The
amplifer amplifies only the difference in voltage between the two inputs, which is called the differential input
voltage. The output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AOL (IN+ – IN–)
where
•
AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10 µV per volt).
(1)
8.4 Device Functional Modes
8.4.1 Input and Output Stage
The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV98x-N use a
complimentary PNP and NPN input stage in which the PNP stage senses common-mode voltage near V− and
the NPN stage senses common-mode voltage near V+. The transition from the PNP stage to NPN stage occurs
1 V below V+. Because both input stages have their own offset voltage, the offset of the amplifier becomes a
function of the input common-mode voltage and has a crossover point at 1 V below V+.
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Device Functional Modes (continued)
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Simplified Schematic Diagram
This VOS crossover point can create problems for both DC− and AC-coupled signals if proper care is not taken.
Large input signals that include the VOS crossover point causes distortion in the output signal. One way to avoid
such distortion is to keep the signal away from the crossover. For example, in a unity gain buffer configuration
with VS = 5 V, a 5-V peak-to-peak signal contains input-crossover distortion while a 3-V peak-to-peak signal
centered at 1.5 V does not contain input-crossover distortion as it avoids the crossover point. Another way to
avoid large signal distortion is to use a gain of −1 circuit which avoids any voltage excursions at the input
terminals of the amplifier. In that circuit, the common-mode DC voltage can be set at a level away from the VOS
cross-over point. For small signals, this transition in VOS shows up as a VCM dependent spurious signal in series
with the input signal and can effectively degrade small-signal parameters such as gain and common-mode
rejection ratio. To resolve this problem, the small signal must be placed such that it avoids the VOS crossover
point. In addition to the rail-to-rail performance, the output stage can provide enough output current to drive
600-Ω loads. Because of the high-current capability, take care not to exceed the 150°C maximum junction
temperature specification.
8.4.2 Shutdown Mode
The LMV98x-N family has a shutdown pin. To conserve battery life in portable applications, the LMV98x-N can
be disabled when the shutdown pin voltage is pulled low. When in shutdown, the output stage is in a highimpedance state and the input bias current drops to less than 1 nA.
The shutdown pin cannot be left unconnected. In case shut-down operation is not required, the shutdown pin
must be connected to V+ when the LMV98x-N are used. Leaving the shutdown pin floating results in an
undefined operation mode, either shutdown or active, or even oscillating between the two modes.
18
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Device Functional Modes (continued)
8.4.3 Input Bias Current Consideration
The LMV98x-N family has a complementary bipolar input stage. The typical input bias current (IB) is 15 nA. The
input bias current can develop a significant offset voltage. This offset is primarily due to IB flowing through the
negative feedback resistor, RF. For example, if IB is 50 nA and RF is 100 kΩ, then an offset voltage of 5 mV
develops (VOS = IB x RF). Using a compensation resistor (RC), as shown in Figure 29, cancels this effect. But the
input offset current (IOS) still contributes to an offset voltage in the same manner.
Figure 29. Canceling the Offset Voltage due to Input Bias Current
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMV98x-N devices bring performance, economy, and ease-of-use to low-voltage, low-power systems. They
provide rail-to-rail input and rail-to-rail output swings into heavy loads.
9.2 Typical Applications
9.2.1 High-Side Current-Sensing Application
V+
+
R1
2 NŸ
RSENSE
0.2 Ÿ
R2
2 NŸ
±
Q1
2N3906
+
VOUT
Load
R3
10 NŸ
ICHARGE
VOUT
RSENSE u R3
R1
u ICHARGE
1: u ICHARGE
Copyright © 2016, Texas Instruments Incorporated
Figure 30. High-Side Current Sensing
9.2.1.1 Design Requirements
The high-side current-sensing circuit (Figure 30) is commonly used in a battery charger to monitor charging
current to prevent overcharging. A sense resistor RSENSE is connected to the battery directly. This system
requires an op amp with rail-to-rail input. The LMV98x-N are ideal for this application because its common-mode
input range extends up to the positive supply.
9.2.1.2 Detailed Design Procedure
As seen in Figure 30, the ICHARGE current flowing through sense resistor RSENSE develops a voltage drop equal to
VSENSE. The voltage at the negative sense point is now less than the positive sense point by an amount
proportional to the VSENSE voltage.
The low-bias currents of the LMV98x cause little voltage drop through R2, so the negative input of the LMV98x
amplifier is at essentially the same potential as the negative sense input.
The LMV98x detects this voltage error between its inputs and servo the transistor base to conduct more current
through Q1, increasing the voltage drop across R1 until the LMV98x inverting input matches the noninverting
input. At this point, the voltage drop across R1 now matches VSENSE.
IG, a current proportional to ICHARGE, flows according to Equation 2.
IG = VRSENSE / R1 = ( RSENSE × ICHARGE ) / R1
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Typical Applications (continued)
IG also flows through the gain resistor R3 developing a voltage drop equal to Equation 3 and Equation 4.
V3 = IG × R3 = ( VRSENSE / R1 ) × R3 = ( ( RSENSE × ICHARGE ) / R2 ) × R3
VOUT = (RSENSE × ICHARGE ) × G
(3)
where
•
G = R3 / R1
(4)
The other channel of the LMV98x may be used to buffer the voltage across R3 to drive the following stages.
9.2.1.3 Application Curve
Figure 31 shows the results of the example current sense circuit. After 4 V, there is an error where transistor Q1
runs out of headroom and saturates, limiting the upper output swing.
5
VOUT (V)
4
3
2
1
0
0
1
2
3
4
5
ICHARGE (A)
C001
Figure 31. Current Sense Amplifier Results
9.2.2 Half-Wave Rectifier Applications
RI
VIN
VOUT
RI
VIN
VCC
3
VOUT
LMV981
4
+
0
t
1
t
Figure 32. Half-Wave Rectifier With Rail-To-Ground Output Swing Referenced to Ground
VCC
VIN
VOUT
3
+
VCC
4
VIN
VCC
VOUT
LMV981
RI
t
1
t
RI
Figure 33. Half-Wave Rectifier With Negative-Going Output Referenced to VCC
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Typical Applications (continued)
9.2.2.1 Design Requirements
Because the LMV98x-N input common-mode range includes both positive and negative supply rails and the
output can also swing to either supply, achieving half-wave rectifier functions in either direction is an easy task.
All that is required are two external resistors; there is no requirement for diodes or matched resistors. The halfwave rectifier can have either positive or negative going outputs, depending on the way the circuit is arranged.
9.2.2.2 Detailed Design Procedure
In Figure 32 the circuit is referenced to ground, while in Figure 33 the circuit is biased to the positive supply.
These configurations implement the half-wave rectifier because the LMV98x-N can not respond to one-half of the
incoming waveform. It can not respond to one-half of the incoming because the amplifier cannot swing the output
beyond either rail; therefore, the output disengages during this half cycle. During the other half cycle, however,
the amplifier achieves a half wave that can have a peak equal to the total supply voltage. RI must be large
enough not to load the LMV98x-N.
9.2.2.3 Application Curves
Figure 35. Output of Rail-to-Ground Circuit
Figure 34. Output of Ground-to-Rail Circuit
9.2.3 Instrumentation Amplifier With Rail-to-Rail Input and Output Application
R2
R1
R3
R4
Figure 36. Rail-to-Rail Instrumentation Amplifier
9.2.3.1 Design Requirements
Using three of the LMV98x-N amplifiers, an instrumentation amplifier with rail-to-rail inputs and outputs can be
made as shown in Figure 36.
9.2.3.2 Detailed Design Procedure
In this example, amplifiers on the left side act as buffers to the differential stage. These buffers assure that the
input impedance is high. They also assure that the difference amp is driven from a voltage source. This is
necessary to maintain the CMRR set by the matching R1 to R2 with R3 to R4. The gain is set by the ratio of R2/R1
and R3 must equal R1 and R4 equal R2. With both rail-to-rail input and output ranges, the input and output are
only limited by the supply voltages. Remember that even with rail-to-rail outputs, the output can not swing past
the supplies so the combined common-mode voltages plus the signal must not be greater that the supplies or
limiting occurs.
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SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
Typical Applications (continued)
9.2.3.3 Application Curve
Figure 37 shows the results of the instrumentation amplifier with R1 and R3 = 1 K, and R2 and R4 = 100 kΩ, for a
gain of 100, running on a single 5-V supply with a input of VCM = VS/2. The combined effects of the individual
offset voltages can be seen as a shift in the offset of the curve.
5
VOUT (V)
4
3
2
1
0
0
10
20
30
40
VDIFF (mV)
50
C001
Figure 37. Instrumentation Amplifier Output Results
9.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 kΩ per volt).
10 Power Supply Recommendations
The LMV98x-N is specified for operation from 1.8 V to 5 V; many specifications apply from –40°C to 125°C.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in
Typical Characteristics.
CAUTION
Supply voltages larger than 5.5 V can permanently damage the device; see Absolute
Maximum Ratings.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For singlesupply, place a capacitor between V+ and V− supply leads. For dual supplies, place one capacitor between V+
and ground, and one capacitor between V– and ground.
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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
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11 Layout
11.1 Layout Guidelines
The V+ pin must be bypassed to ground with a low-ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between V+ and ground.
The ground pin must be connected to the PCB ground plane at the pin of the device.
The feedback components must be placed as close to the device as possible minimizing strays.
11.2 Layout Example
Figure 38. SOT-23 Layout Example
24
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SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Absolute Maximum Ratings for Soldering (SNOA549)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMV981-N
Click here
Click here
Click here
Click here
Click here
LMV982-N
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2001–2016, Texas Instruments Incorporated
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25
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMV981MF
NRND
SOT-23
DBV
6
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
A78A
LMV981MF/NOPB
ACTIVE
SOT-23
DBV
6
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
A78A
LMV981MFX/NOPB
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
A78A
LMV981MG/NOPB
ACTIVE
SC70
DCK
6
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
A77
LMV981MGX/NOPB
ACTIVE
SC70
DCK
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
A77
LMV981TL/NOPB
ACTIVE
DSBGA
YZR
6
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
A
H
LMV981TLX/NOPB
ACTIVE
DSBGA
YZR
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
A
H
LMV982MM/NOPB
ACTIVE
VSSOP
DGS
10
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
A87A
LMV982MMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
A87A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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