LMX2487ESQE/NOPB

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 LMX2487 1-GHz to 6-GHz High Performance Delta-Sigma Low-Power Dual PLLatinum™ Frequency Synthesizers With 3-GHz Integer PLL 1 Features 3 Description • The LMX2487 device is a low power, high performance delta-sigma fractional-N PLL with an auxiliary integer-N PLL. It is fabricated using TI’s advanced process. 1 • • • • Quadruple Modulus Prescaler for Lower Divides – RF PLL: 16/17/20/21 or 32/33/36/37 – IF PLL: 8/9 or 16/17 Advanced Delta Sigma Fractional Compensation – 12-Bit or 22-Bit Selectable Fractional Modulus – Up to 4th Order Programmable Delta-Sigma Modulator Improved Lock Times – Fastlock / Cycle Slip Reduction With SingleWord Write to Change Frequencies – Integrated Time-Out Counter Wide Operating Range – LMX2487 RF PLL: 1.0 GHz to 6.0 GHz Useful Features – Digital Lock Detect Output – Hardware and Software Power-Down Control – On-Chip Input Frequency Doubler – RF Phase Comparison Detector Up to 50 MHz – 2.5-V to 3.6-V Operation With ICC = 8.5 mA With delta-sigma architecture, fractional spurs at lower offset frequencies are pushed to higher frequencies outside the loop bandwidth. The ability to push close in spur and phase noise energy to higher frequencies is a direct function of the modulator order. Unlike analog compensation, the digital feedback technique used in the LMX2487 is highly resistant to changes in temperature and variations in wafer processing. The LMX2487 delta-sigma modulator is programmable up to fourth order, which allows the designer to select the optimum modulator order to fit the phase noise, spur, and lock time requirements of the system. Serial data for programming the LMX2487 is transferred through a three-line, high-speed (20-MHz) MICROWIRE interface. The LMX2487 offers fine frequency resolution, low spurs, fast programming speed, and a single-word write to change the frequency. This makes it ideal for direct digital modulation applications, where the N-counter is directly modulated with information. The LMX2487 is available in a 24-lead 4.0 × 4.0 × 0.8 mm WQFN package. 2 Applications • • • • Cellular Phones and Base Stations Direct Digital Modulation Applications Satellite and Cable TV Tuners WLAN Standards Device Information(1) PART NUMBER LMX2487 PACKAGE WQFN (24) BODY SIZE (NOM) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram IF N Divider B Counter 8/9 or 16/17 Prescaler A Counter FinIF ENOSC OSCin VddIF1 VddIF2 Phase Comp Charge Pump CPoutIF Ftest/LD MUX Ftest/LD Charge Pump CPoutRF IF LD IF R Divider OSCout VddRF1 VddRF2 1X / 2X RF R Divider VddRF3 VddRF4 VddRF5 FinRF FinRF* RF LD RF N Divider C Counter 16/17/20/21 or B Counter RF N Divider 32/33/36/37 Prescaler A Counter Phase Comp CE CLK DATA LE RF Fastlock MICROWIRE Interface 6' Compensation FLoutRF GND GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. 7 Parameter Measurement Information ................ 13 8 Detailed Description ............................................ 18 7.1 Bench Test Set-Ups................................................ 13 8.1 Overview ................................................................. 18 8.2 Functional Block Diagram ....................................... 18 8.3 8.4 8.5 8.6 9 Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Register Maps ........................................................ 18 25 26 28 Application and Implementation ........................ 39 9.1 Application Information............................................ 39 9.2 Typical Application ................................................. 40 10 Power Supply Recommendations ..................... 42 11 Layout................................................................... 42 11.1 Layout Guidelines ................................................. 42 11.2 Layout Example .................................................... 42 12 Device and Documentation Support ................. 43 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 43 43 43 43 13 Mechanical, Packaging, and Orderable Information ........................................................... 43 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2013) to Revision C • Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................ 1 Changes from Revision A (March 2013) to Revision B • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 38 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 5 Pin Configuration and Functions VddRF4 FLoutRF VddRF3 NC OSCin ENOSC RTW Package 24-Pin WQFN Top View 24 23 22 21 20 19 CPoutRF 1 18 OSCout GND 2 17 VddIF2 VddRF1 3 16 CPoutIF Pin 0 (Ground Substrate) FinRF 4 FinRF* 5 14 VddIF1 LE 6 13 FinIF 8 9 10 11 12 CLK VddRF2 CE VddRF5 Ftest/LD DATA 7 15 GND Pin Functions PIN NO. NAME I/O DESCRIPTION 0 GND — Ground Substrate. This is on the bottom of the package and must be grounded. 1 CPoutRF O RF PLL charge pump output. 2 GND — RF PLL analog ground. 3 VddRF1 — RF PLL analog power supply. 4 FinRF I RF PLL high-frequency input pin. 5 FinRF* I RF PLL complementary high-frequency input pin. Shunt to ground with a 100-pF capacitor. 6 LE I MICROWIRE Load Enable. High-impedance CMOS input. Data stored in the shift registers is loaded into the internal latches when LE goes HIGH 7 DATA I MICROWIRE Data. High-impedance binary serial data input. 8 CLK I MICROWIRE Clock. High-impedance CMOS Clock input. Data for the various counters is clocked into the 24-bit shift register on the rising edge 9 VddRF2 — 10 CE I Chip Enable control pin. Must be pulled high for normal operation. 11 VddRF5 I Power supply for RF PLL digital circuitry. 12 Ftest/LD O Test frequency output / Lock Detect. IF PLL high-frequency input pin. Power supply for RF PLL digital circuitry. 13 FinIF I 14 VddIF1 — IF PLL analog power supply. 15 GND — IF PLL digital ground. 16 CPoutIF O IF PLL charge pump output 17 VddIF2 — IF PLL power supply. 18 OSCout O Buffered output of the OSCin signal. 19 ENOSC I Oscillator enable. When this is set to high, the OSCout pin is enabled regardless of the state of other pins or register bits. 20 OSCin I Reference Input. 21 NC I This pin must be left open. 22 VddRF3 — Power supply for RF PLL digital circuitry. 23 FLoutRF O RF PLL Fastlock Output. Also functions as Programmable TRI-STATE CMOS output. 24 VddRF4 — RF PLL analog power supply. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 3 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) See . MIN MAX UNIT VCC Power supply voltage –0.3 4.25 V Vi Voltage on any pin with GND = 0 V –0.3 VCC + 0.3 V TL Lead temperature (solder 4 seconds) 260 °C Tstg Storage temperature 150 °C (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Electrostatic discharge (1) V(ESD) (1) Human-body model (HBM) ±2000 Charged-device model (CDM) ±750 Machine model (MM) ±200 UNIT V This is a high performance RF device is ESD-sensitive. Handling and assembly of this device should be done at an ESD free workstation. 6.3 Recommended Operating Conditions MIN (1) VCC Power supply voltage TA Operating temperature (1) NOM MAX UNIT 2.5 3 3.6 V –40 25 85 °C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. The voltage at all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. VCC will be used to refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these power pins. 6.4 Thermal Information THERMAL METRIC (1) LMX2485, LMX2485E RTW (WQFN) UNIT 24 PINS RθJA Junction-to-ambient thermal resistance 47.2 °C/W RθJC(top) RθJB Junction-to-case (top) thermal resistance 43 °C/W Junction-to-board thermal resistance 24 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 24 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 6.5 Electrical Characteristics (VCC = 3.0 V; –40°C ≤ TA ≤ +85°C unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC PARAMETERS ICCRF Power supply current, RF synthesizer IF PLL OFF RF PLL ON Charge Pump TRI-STATE 5.7 mA ICCIF Power supply current, IF synthesizer IF PLL ON RF PLL OFF Charge Pump TRI-STATE 2.5 mA ICCTOTAL Power supply current, entire synthesizer IF PLL ON RF PLL ON Charge Pump TRI-STATE 8.5 mA ICCPD Power-down current CE = ENOSC = 0 V CLK, DATA, LE = 0 V 2 3% 10% RF_CPG ≤ 2 3% 13% 0.5 ≤ VCPoutRF ≤ VCC -0.5 TA = 25°C 2% 8% VCPoutRF = VCC/2 4% nA IF SYNTHESIZER PARAMETERS IF_P = 8 250 2000 IF_P = 16 250 3000 fFinIF Operating frequency pFinIF IF input sensitivity fCOMP Phase detector frequency ICPoutIFSRCE IF charge pump source current VCPoutIF = VCC/2 3.5 mA ICPoutIFSINK IF charge pump sink current VCPoutIF = VCC/2 –3.5 mA ICPoutIFTRI IF charge pump TRI-STATE current magnitude 0.5 ≤ VCPoutIF ≤ VCC RF -0.5 | ICPoutIF%MIS | Magnitude of IF CP sink vs CP source VCPoutIF = VCC/2 mismatch TA = 25°C | ICPoutIF%V | Magnitude of IF CP current vs CP voltage | ICPoutIF%TEMP Magnitude of IF CP current vs temperature (1) (2) –10 MHz 5 dBm 10 MHz 2 10 1% 8% 0.5 ≤ VCPoutIF ≤ VCC -0.5 TA = 25°C 4% 10% VCPoutIF = VCC/2 4% nA For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required. Refer to the table in RF_CPG – RF PLL Charge Pump Gain for a complete listing of charge pump currents. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 5 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) (VCC = 3.0 V; –40°C ≤ TA ≤ +85°C unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCILLATOR PARAMETERS fOSCin Oscillator operating frequency vOSCin Oscillator input sensitivity IOSCin Oscillator input current OSC2X = 0 5 110 MHz OSC2X = 1 5 20 MHz 0.5 VCC VP-P –100 100 µA SPURS Spurs in band (3) –55 dBc PHASE NOISE LF1HzRF LF1HzIF RF synthesizer normalized phase noise contribution (4) RF_CPG = 0 –202 RF_CPG = 1 –204 RF_CPG = 3 –206 RF_CPG = 7 –210 RF_CPG = 15 –210 IF synthesizer normalized phase noise contribution dBc/Hz –209 dBc/Hz DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF) VIH High-level input voltage VIL Low-level input voltage IIH High-level input current VIH = VCC IIL Low-level input current VIL = 0 V VOH High-level output voltage IOH = –500 µA VOL Low-level output voltage IOL = 500 µA (3) (4) 1.6 VCC V 0.4 V –1 1 µA –1 1 µA VCC – 0.4 V 0.4 V In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate the impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency = 20 MHz, RF_CPG = 7, DITH = 0, VCO Frequency = 3 GHz, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range. Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for RF_CPG = 7, Fraction = 1/2000, Comparison Frequency = 20 MHz, FM = 0, DITH = 0, VCO Frequency = 3 GHz. 6.6 Timing Requirements MIN NOM MAX UNIT MICROWIRE INTERFACE TIMING tCS Data to clock set-up time See Figure 1 25 ns tCH Data to clock hold time See Figure 1 8 ns tCWH Clock pulse width high See Figure 1 25 ns tCWL Clock pulse width low See Figure 1 25 ns tES Clock to load enable set-up time See Figure 1 25 ns tEW Load enable pulse width See Figure 1 25 ns MSB DATA D19 LSB D18 D17 D16 D15 D0 C3 C2 C1 C0 CLK tCS tCH tCWH tES tCWL LE tEW Figure 1. MICROWIRE Input Timing Diagram 6 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 6.7 Typical Characteristics 6.7.1 Sensitivity Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics. 20 20 TA = 85oC 10 10 VCC = 2.5V TA = 25oC VCC = 3.0V and 3.6V TA = -40oC 0 pFinRF (dBm) pFinRF (dBm) 0 -10 -20 -10 -20 TA = 85oC VCC = 3.6V TA = -40oC -30 -30 VCC = 2.5V VCC = 3.0V TA = 25oC -40 1000 0 2000 4000 3000 6000 5000 -40 7000 1000 0 2000 4000 3000 6000 5000 7000 fFinRF (MHz) fFinRF (MHz) TA = 25°C, RF_P = 32 Figure 2. RF PLL Fin Sensitivity VCC = 3.0 V, RF_P = 32 Figure 3. RF PLL Fin Sensitivity 20 20 10 TA = -40oC 10 TA = 25oC, and 85oC 0 VCC = 3.0 and 3.6V VCC = 2.5V pFinIF (dBm) pFinIF (dBm) 0 -10 -10 -20 VCC = 3.0V VCC = 3.6V TA = 25oC TA = -40oC -30 -20 TA = 85oC -40 -30 VCC = 2.5V -50 0 2000 1000 3000 4000 -40 3000 2000 1000 0 fFinIF (MHz) 4000 fFinIF (MHz) VCC = 3.0 V, IF_P = 16 TA = 25°C, IF_P = 16 Figure 4. IF PLL Fin Sensitivity Figure 5. IF PLL Fin Sensitivity 20 20 10 10 VCC = 2.5V, 3.0V, and 3.6V TA = -40oC, 25oC, and 85oC 0 INPUT POWER (dBm) INPUT POWER (dBm) 0 -10 VCC = 3.6V -20 VCC = 3.0V VCC = 2.5V -30 -10 -20 TA = 25oC TA = 85oC -30 -40 -40 TA = -40oC -50 0 10 30 60 90 fOSCin (MHz) TA = 25°C, OSC_2X = 0 Figure 6. OSCin Sensitivity 120 150 -50 0 10 30 90 60 120 150 fOSCin (MHz) VCC = 3.0 V, OSC_2X = 0 Figure 7. OSCin Sensitivity Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 7 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Sensitivity (continued) Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics. 20 20 10 10 TA = -40oC, 25oC, and 85oC VCC = 2.5V, 3.0V, and 3.6V 0 INPUT POWER (dBm) INPUT POWER (dBm) 0 VCC = 3.6V -10 VCC = 3.0V -20 VCC =2.5V -10 TA = 85oC -20 TA = -40oC -30 -30 -40 -40 -50 -50 TA = 25oC 0 5 10 15 20 25 0 TA = 25°C, OSC_2X =1 Figure 8. OSCin Sensitivity 8 5 10 15 20 25 fOSCin (MHz) fOSCin (MHz) VCC = 3.0 V, OSC_2X = 1 Figure 9. OSCin Sensitivity Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 6.7.2 FinRF Input Impedance Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics. Marker 1: 3 GHz Marker 2: 4 GHz Marker 3: 5 GHz Marker 4: 6 GHz 1 Start 2.5 GHz Stop 7.0 GHz 4 3 2 Figure 10. FinRF Input Impedance Table 1. FinRF Input Impedance FinRF INPUT IMPEDANCE FREQUENCY (MHz) REAL (Ω) IMAGINARY (Ω) 3000 39 –94 3200 37 –86 3400 33 –78 3600 30 –72 3800 28 –69 4000 26 –66 4250 24 –63 4500 23 –60 4750 22 –57 5000 20 –54 5250 19 –50 5500 18 –49 5750 17 –47 6000 17 –45 6250 16 –44 6500 16 –42 6750 16 –40 7000 16 –39 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 9 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 6.7.3 FinIF Input Impedance Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics. Marker 1: 100 MHz Marker 2: 250 MHz Marker 3: 2300 MHz 2 1 Marker 4: 3000 MHz 3 Start 100 MHz Stop 3000 MHz 4 Figure 11. FinIF Input Impedance Table 2. FinIF Input Impedance FinIF INPUT IMPEDANCE 10 FREQUENCY (MHz) REAL (Ω) IMAGINARY (Ω) 100 508 –233 150 456 –215 200 420 –206 250 403 –205 300 370 –207 400 344 –215 500 207 –223 600 274 –225 700 242 –225 800 242 –225 900 214 –222 1000 171 –208 1200 137 –191 1400 112 –176 1600 91 –158 1800 76 –139 2000 62 –122 2200 51 –105 2300 46 –96 2400 42 –88 2600 37 –74 2800 29 –63 3000 25 –54 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 6.7.4 OSCin Input Impedance Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics. MAGNITUDE OF INPUT IMPEDANCE (:) 6000 5000 4000 3000 Powered Down 2000 1000 Powered Up 0 0 25 50 75 100 125 150 FREQUENCY (MHz) Figure 12. OSCin Input Impedance Table 3. OSCin Input Impedance FREQUENCY (MHz) POWERED UP POWERED DOWN REAL IMAGINARY MAGNITUDE REAL IMAGINARY MAGNITUDE 5 1730 –3779 4157 392 –8137 8146 10 846 –2236 2391 155 –4487 4490 20 466 –1196 1284 107 –2215 2217 30 351 –863 932 166 –1495 –1504 40 316 –672 742 182 –1144 1158 50 278 –566 631 155 –912 925 60 261 –481 547 153 –758 774 70 252 –425 494 154 –652 669 80 239 –388 456 147 –576 595 90 234 –358 428 145 –518 538 100 230 –337 407 140 –471 492 110 225 –321 392 138 –436 458 120 219 –309 379 133 –402 123 130 214 –295 364 133 –374 397 140 208 –285 353 132 –349 373 150 207 –279 348 133 –329 355 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 11 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 6.7.5 Currents Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics. 10 TA = 85oC 9.0 2000 8.0 1500 TA = -40oC TA = 25oC RF_CPG = 15 7.0 ICC TOTAL (mA) 1000 6.0 ICPoutRF (PA) 500 5.0 4.0 RF_CPG = 8 0 -500 RF_CPG = 0 3.0 2.0 -1000 1.0 -1500 RF_CPG = 1 0 2.5 2.75 3.3 3.0 -2000 3.6 0.5 0 1.0 1.5 VCC (V) 2.0 2.5 3.0 VCPoutRF (V) CE = High VCC = 3 V Figure 13. Power Supply Current Figure 14. RF PLL Charge Pump Current 10 8 4.0 6 3.0 4 ICPoutRF TRI (nA) 5.0 ICPoutIF (mA) 2.0 1.0 0 -1.0 TA = 85o C 2 0 TA = -40o C -2 TA = 25o C -4 -2.0 -6 -3.0 -8 -4.0 -10 0.5 0 1.5 1.0 2.0 2.5 3.0 -5.0 0 0.5 1.0 1.5 2.0 3.0 2.5 VCPoutRF (V) VCPoutIF (V) VCC = 3 V VCC = 3 V Figure 16. Charge Pump Leakage RF PLL Figure 15. IF PLL Charge Pump Current 10 8 6 TA = 85o C ICPoutIF TRI (nA) 4 2 0 -2 TA = -40o C -4 o TA = 25 C -6 -8 -10 0 0.5 1.0 1.5 2.0 2.5 3.0 VCPoutIF (V) VCC = 3 V Figure 17. Charge Pump Leakage IF PLL 12 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 7 Parameter Measurement Information 7.1 Bench Test Set-Ups 7.1.1 Charge Pump Current Measurement Procedure DC Blocking Capacitor 10 MHz SMA Cable Frequency Input Pin SMA Cable CPout Pin Signal Generator Semiconductor Parameter Analyzer Device Under Test OSCin Pin Evaluation Board Power Supply Figure 18. Setup for Charge Pump Current Measurement Figure 18 shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current level, mismatch, and leakage measurements. In order to measure the charge pump currents, a signal is applied to the high frequency input pins. The reason for this is to ensure that the phase detector gets enough transitions in order to be able to change states. If no signal is applied, it is possible that the charge pump current reading will be low due to the fact that the duty cycle is not 100%. The OSCin Pin is tied to the supply. The charge pump currents can be measured by simply programming the phase detector to the necessary polarity. For instance, in order to measure the RF charge pump, a 10-MHz signal is applied to the FinRF pin. The source current can be measured by setting the RF PLL phase detector to a positive polarity, and the sink current can be measured by setting the phase detector to a negative polarity. The IF PLL currents can be measured in a similar way. NOTE The magnitude of the RF PLL charge pump current is controlled by the RF_CPG bit. Once the charge pump currents are known, the mismatch can be calculated. In order to measure leakage, the charge pump is set to a TRI-STATE mode by enabling the RF_CPT and IF_CPT bits. Table 4 shows a summary of the various charge pump tests. Table 4. Charge Pump Current Measurement Settings CURRENT TEST RF_CPG RF_CPP RF_CPT IF_CPP IF_CPT RF Source 0 to 15 0 0 X X RF Sink 0 to 15 1 0 X X RF TRI-STATE X X 1 X X IF Source X X X 0 0 IF Sink X X X 1 0 IF TRI-STATE X X X X 1 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 13 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 7.1.2 Charge Pump Current Specification Definitions Figure 19. Charge Pump Definitions I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV I2 = Charge Pump Sink Current at VCPout = Vcc/2 I3 = Charge Pump Sink Current at VCPout = ΔV I4 = Charge Pump Source Current at VCPout = Vcc - ΔV I5 = Charge Pump Source Current at VCPout = Vcc/2 I6 = Charge Pump Source Current at VCPout = ΔV ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this part. vCPout refers to either VCPoutRF or VCPoutIF ICPout refers to either ICPoutRF or ICPoutIF 7.1.2.1 Charge Pump Output Current Variation vs Charge Pump Output Voltage Use Equation 1 to calculate the charge pump output current variation versus the charge pump output voltage. (1) 7.1.2.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch Use Equation 2 to calculate the charge pump sink current versus the source current mismatch. (2) 14 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 7.1.2.3 Charge Pump Output Current Variation vs Temperature Use Equation 3 to calculate the charge pump output current magnitude variation versus the temperature. (3) 7.1.3 Sensitivity Measurement Procedure SMA Cable Signal Generator Frequency Input Pin Matching Network DC Blocking Capacitor Device Under Test SMA Cable Ftest/LD Pin Frequency Counter Evaluation Board Power Supply Figure 20. Setup for Sensitivity Measurement Table 5. Settings for Sensitivity Measurement FREQUENCY INPUT PIN DC-BLOCKING CAPACITOR CORRESPONDING COUNTER DEFAULT COUNTER VALUE MUX VALUE OSCin 1000 pF RF_R / 2 50 14 FinRF 100 pF// 1000 pF RF_N / 2 502 + 2097150 / 4194301 15 FinIF 100 pF IF_N / 2 534 13 OSCin 1000 pF IF_R / 2 50 12 Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz or more of its expected value. It is typically measured over frequency, voltage, and temperature. In order to test sensitivity, the MUX[3:0] word is programmed to the appropriate value. The counter value is then programmed to a fixed value and a frequency counter is set to monitor the frequency of this pin. The expected frequency at the Ftest/LD pin should be the signal generator frequency divided by twice the corresponding counter value. The factor of two comes in because the LMX2487 has a flip-flop which divides this frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter input impedance should be set to high impedance. In order to perform the measurement, the temperature, frequency, and voltage is set to a fixed value and the power level of the signal is varied. NOTE The power level at the part is assumed to be 4 dB less than the signal generator power level. This accounts 1 dB for cable losses and 3 dB for the pad. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 15 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com The power level range where the frequency is correct at the Ftest/LD pin to within 1-Hz accuracy is recorded for the sensitivity limits. The temperature, frequency, and voltage can be varied in order to produce a family of sensitivity curves. Because this is an open-loop test, the charge pump is set to TRI-STATE and the unused side of the PLL (RF or IF) is powered down when not being tested. For this part, there are actually four frequency input pins, although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin are shown in the table in the Charge Pump Current Specification Definitions section. NOTE For the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a fraction of 2097150 / 4194301 is used. The reason for this long fraction is to test the RF N counter and supporting fractional circuitry as completely as possible. 16 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 7.1.4 Input Impedance Measurement Procedure Frequency Input Pin Network Analyzer Device Under Test Evaluation Board Power Supply Figure 21. Block Diagram Figure 21 shows the test set-up used for measuring the input impedance for the LMX2487. The DC-blocking capacitor used between the input SMA connector and the pin being measured must be changed to a 0-Ω resistor. This procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the network analyzer, ensure the part is powered up, and then measure the input impedance. The network analyzer can be calibrated by using either calibration standards or by soldering resistors directly to the evaluation board. An open can be implemented with no resistor. A short can be implemented by soldering a 0-Ω resistor as close as possible to the pin being measured, and can also be implemented by soldering two 100-Ω resistors in parallel as close as possible to the pin being measured. Calibration is done with the PLL removed from the PCB. This requires the use of a clamp down fixture that may not always be generally available. If no clamp down fixture is available, then this procedure can be done by calibrating up to the point where the DC-blocking capacitor usually is, and then implementing port extensions with the network analyzer. A 0-Ω resistor is added back in for the actual measurement. Once the set-up is calibrated, it is necessary to ensure the PLL is powered up. This can be done by toggling the power down bits (RF_PD and IF_PD) and observing the current consumption increases when the bit is disabled. Sometimes it may be necessary to apply a signal to the OSCin pin in order to program the part. If this is necessary, disconnect the signal once it is established the part is powered up. It is useful to know the input impedance of the PLL for the purposes of debugging RF problems and designing matching networks. Another use for knowing this parameter is make the trace width on the PCB such that the input impedance of this trace matches the real part of the input impedance of the PLL frequency of operation. In general, it is good practice to keep trace lengths short and make designs that are relatively resistant to variations in the input impedance of the PLL. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 17 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 8 Detailed Description 8.1 Overview The LMX2487 consists of integrated N counters, R counters, and charge pumps. The TCXO, VCO and loop filter are supplied external to the chip. 8.2 Functional Block Diagram IF N Divider B Counter 8/9 or 16/17 Prescaler A Counter FinIF ENOSC OSCin VddIF1 VddIF2 Phase Comp Charge Pump CPoutIF Ftest/LD MUX Ftest/LD Charge Pump CPoutRF IF LD IF R Divider OSCout VddRF1 VddRF2 RF R Divider 1X / 2X VddRF3 RF LD VddRF4 VddRF5 RF N Divider C Counter 16/17/20/21 or B Counter RF N Divider 32/33/36/37 Prescaler A Counter FinRF FinRF* Phase Comp CE CLK DATA LE RF Fastlock MICROWIRE Interface 6' Compensation FLoutRF GND GND GND 8.3 Feature Description 8.3.1 TCXO, Oscillator Buffer, and R Counter The oscillator buffer must be driven single-ended by a signal source, such as a TCXO. The OSCout pin is included to provide a buffered output of this input signal and is active when the OSC_OUT bit is set to one. The ENOSC pin can be also pulled high to ensure that the OSCout pin is active, regardless of the status of the registers in the LMX2487. The R counter divides this TCXO frequency down to the comparison frequency. 8.3.2 Phase Detector The maximum phase detector operating frequency for the IF PLL is straightforward, but is a little more involved for the RF PLL because it is fractional. The maximum phase detector frequency for the LMX2487 RF PLL is 50 MHz. However, this is not possible in all circumstances due to illegal divide ratios of the N counter. The crystal reference frequency also limits the phase detector frequency, although the doubler helps with this limitation. There are trade-offs in choosing the phase detector frequency. If this frequency is run higher, then phase noise will be lower; but lock time may be increased due to cycle slipping and the capacitors in the loop filter may become rather large. 8.3.3 Charge Pump For the majority of the time, the charge pump output is high impedance, and the only current through this pin is the TRI-STATE leakage. However, it does put out fast correction pulses that have a width that is proportional to the phase error presented at the phase detector. The charge pump converts the phase error presented at the phase detector into a correction current. The magnitude of this current is theoretically constant, but the duty cycle is proportional to the phase error. For the IF PLL, this current is not programmable, but for the RF PLL it is programmable in 16 steps. Also, the RF PLL allows for a higher charge pump current to be used when the PLL is locking in order to reduce the lock time. 18 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 Feature Description (continued) 8.3.4 Loop Filter The loop filter design can be rather involved. In addition to the regular constraints and design parameters, deltasigma PLLs have the additional constraint that the order of the loop filter should be one greater than the order of the delta sigma modulator. This rule of thumb comes from the requirement that the loop filter must roll off the delta sigma noise at 20 dB/decade faster than it rises. However, because the noise can not have infinite power, it must eventually roll off. If the loop bandwidth is narrow, this requirement may not be necessary. For the purposes of discussion in this datasheet, the pole of the loop filter at 0 Hz is not counted. So a second order filter has 3 components, a 3rd order loop filter has 5 components, and the 4th order loop filter has 7 components. Although a 5th order loop filter is theoretically necessary for use with a 4th order modulator, typically a 4th order filter is used in this case. The loop filter design, especially for higher orders can be rather involved, but there are many simulation tools and references available, such as the one given at the end of the functional description block. 8.3.5 N Counters and High Frequency Input Pins The N counter divides the VCO frequency down to the comparison frequency. Because prescalers are used, there are limitations on how small the N value can be. The N counters are discussed in greater depth in the programming section. Because the input pins to these counters (FinRF and FinIF) are high frequency, layout considerations are important. 8.3.5.1 High Frequency Input Pins, FinRF and FinIF It is generally recommended that the VCO output go through a resistive pad and then through a DC-blocking capacitor before it gets to these high frequency input pins. If the trace length is sufficiently short ( < 1/10th of a wavelength ), then the pad may not be necessary, but a series resistor of about 39 Ω is still recommended to isolate the PLL from the VCO. The DC-blocking capacitor should be chosen at least to be 27 pF. It may turn out that the frequency is above the self-resonant frequency of the capacitor, but because the input impedance of the PLL tends to be capacitive, it actually is a benefit to exceed the tune frequency. The pad and the DC-blocking capacitor should be placed as close to the PLL as possible 8.3.5.2 Complementary High Frequency Pin, FinRF* These inputs may be used to drive the PLL differentially, but it is very common to drive the PLL in a single ended fashion. A shunt capacitor should be placed at the FinRF* pin. The value of this capacitor should be chosen such that the impedance, including the ESR of the capacitor, is as close to an AC short as possible at the operating frequency of the PLL. 100 pF is a typical value. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 19 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) 8.3.6 Digital Lock Detect Operation The RF PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase detector to a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less than the ε RC delay for 5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater δ. The values of ε and δ are dependent on which PLL is used and are shown in Table 6: Table 6. Digital Lock Detect Settings PLL ε δ RF 10 ns 20 ns IF 15 ns 30 ns When the PLL is in the power-down mode and the Ftest/LD pin is programmed for the lock detect function, it is forced LOW. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to divide the comparison frequency presented to the lock detect circuit by 4. NOTE If the MUX[3:0] word is set such as to view lock detect for both PLLs, an unlocked (LOW) condition is shown whenever either one of the PLLs is determined to be out of lock. 20 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 START LD = LOW (Not Locked) NO Phase Error < H YES NO Phase Error < H YES NO Phase Error < H YES NO Phase Error < H YES NO Phase Error < H YES LD = HIGH (Locked) YES NO Phase Error > G Figure 22. Digital Lock Detect Flowchart Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 21 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 8.3.7 Cycle Slip Reduction and Fastlock The LMX2487 offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This means that it requires no additional programming overhead to use them. It is generally recommended that the charge pump current in the steady-state be 8X or less in order to use cycle slip reduction, and 4X or less in steady-state in order to use Fastlock. The next step is to decide between using Fastlock or CSR. This determination can be made based on the ratio of the comparison frequency (fCOMP) to loop bandwidth (BW). Table 7. Cycle Slip/Fastlock Usage COMPARISON FREQUENCY ( fCOMP ) fCOMP ≤ 1.25 MHz Noticeable better than CSR 1.25 MHz < fCOMP ≤ 2 MHz Marginally better than CSR fCOMP > 2 MHz CYCLE SLIP REDUCTION ( CSR ) FASTLOCK Likely to provide a benefit, provided that fCOMP > 100 × BW Same or worse than CSR 8.3.7.1 Cycle Slip Reduction (CSR) Cycle slip reduction works by reducing the comparison frequency during frequency acquisition while keeping the same loop bandwidth, thereby reducing the ratio of the comparison frequency to the loop bandwidth. In cases where the ratio of the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping can occur and significantly degrade lock times. The greater this ratio, the greater the benefit of CSR. This is typically the case of high comparison frequencies. In circumstances where there is not a problem with cycle slipping, CSR provides no benefit. There is a glitch when CSR is disengaged, but because CSR should be disengaged long before the PLL is actually in lock, this glitch is not an issue. A good rule of thumb for CSR disengagement is to do this at the peak time of the transient response. Because this time is typically much sooner than Fastlock should be disengaged, it does not make sense to use CSR and Fastlock in combination. 8.3.7.2 Fastlock Fastlock works by increasing the loop bandwidth only during frequency acquisition. In circumstances where the comparison frequency is less than or equal to 2 MHz, Fastlock may provide a benefit beyond what CSR can offer. Because Fastlock also reduces the ratio of the comparison frequency to the loop bandwidth, it may provide a significant benefit in cases where the comparison frequency is above 2 MHz. However, CSR can usually provide an equal or larger benefit in these cases, and can be implemented without using an additional resistor. The reason for this restriction on frequency is that Fastlock has a glitch when it is disengaged. As the time of engagement for Fastlock decreases and becomes on the order of the fast lock time, this glitch grows and limits the benefits of Fastlock. This effect becomes worse at higher comparison frequencies. There is always the option of reducing the comparison frequency at the expense of phase noise in order to satisfy this constraint on comparison frequency. Despite this glitch, there is still a net improvement in lock time using Fastlock in these circumstances. When using Fastlock, it is also recommended that the steady-state charge pump state be 4X or less. Also, Fastlock was originally intended only for second order filters, so when implementing it with higher order filters, the third and fourth poles can not be too close in, or it will not be possible to keep the loop filter well optimized when the higher charge pump current and Fastlock resistor are engaged. 8.3.7.3 Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping Once it is decided that CSR is to be used, the cycle slip reduction factor needs to be chosen. The available factors are 1/2, 1/4, and 1/16. In order to preserve the same loop characteristics, TI recommends that Equation 4 be satisfied: (Fastlock Charge Pump Current) / (Steady-State Charge Pump Current) = CSR (4) In order to satisfy this constraint, the maximum charge pump current in steady-state is 8X for a CSR of 1/2, 4X for a CSR of 1/4, and 1X for a CSR of 1/16. Because the PLL phase noise is better for higher charge pump currents, it makes sense to choose CSR only as large as necessary to prevent cycle slipping. Choosing it larger than this will not improve lock time, and will result in worse phase noise. 22 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 Consider an example where the desired loop bandwidth in steady-state is 100 kHz and the comparison frequency is 20 MHz. This yields a ratio of 200. Cycle slipping may be present, but would not be too severe if it was there. If a CSR factor of 1/2 is used, this would reduce the ratio to 100 during frequency acquisition, which is probably sufficient. A charge pump current of 8X could be used in steady-state, and a factor of 16X could be used during frequency acquisition. This yields a ratio of 1/2, which is equal to the CSR factor and this satisfies Equation 4. In this circumstance, it could also be decided to just use 16X charge pump current all the time, because it would probably have better phase noise, and the degradation in lock time would not be too severe. 8.3.7.4 Using Fastlock to Improve Lock Times Figure 23. Loop Filter with Fastlock Resistor Once it is decided that Fastlock is to be used, the loop bandwidth multiplier, K, is needed in order to determine the theoretical impact of Fastlock on the loop bandwidth and the resistor value, R2p, that is switched in parallel during Fastlock. This ratio is calculated in Equation 5: K = ( Fastlock Charge Pump Current ) / ( Steady-State Charge Pump Current ) (5) Table 8. Fastlock Usage K LOOP BANDWIDTH R2P VALUE LOCK TIME 1 2 1.00 X Open 100% 1.41 X R2/0.41 71% 3 1.73 X R2/0.73 58% 4 2.00 X R2 50% 8 2.83 X R2/1.83 35% 9 3.00 X R2/2 33% 16 4.00 X R2/3 25% Table 8 shows how to calculate the fastlock resistor and theoretical lock time improvement, once the ratio, K, is known. This all assumes a second order filter (not counting the pole at 0 Hz). However, it is generally recommended that the loop filter order be one greater than the order of the delta sigma modulator, which means that a second order filter is never recommended. In this case, the value for R2p is typically about 80% of what it would be for a second order filter. Because the fastlock disengagement glitch gets larger and it is harder to keep the loop filter optimized as the K value becomes larger, designing for the largest possible value for K usually, but not always yields the best improvement in lock time. To get a more accurate estimate requires more simulation tools, or trial and error. 8.3.7.5 Capacitor Dielectric Considerations for Lock Time The LMX2487 has a high fractional modulus and high charge pump gain for the lowest possible phase noise. One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop filter to become larger in value. For larger capacitor values, it is common to have a trade-off between capacitor dielectric quality and physical size. Using film capacitors or NPO/COG capacitors yields the best possible lock times, where as using X7R or Z5R capacitors can increase lock time by 0 – 500%. However, it is a general tendency that designs that use a higher compare frequency tend to be less sensitive to the effects of capacitor dielectrics. Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances, allowing a larger footprint for the loop filter capacitors, using a lower charge pump current, and reducing the fractional modulus are all ways to reduce capacitor values. Capacitor dielectrics have very little impact on phase noise and spurs. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 23 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 8.3.8 Fractional Spur and Phase Noise Controls Control of the fractional spurs is more of an art than an exact science. The first differentiation that needs to be made is between primary fractional and sub-fractional spurs. The primary fractional spurs are those that occur at increments of the channel spacing only. The sub-fractional spurs are those that occur at a smaller resolution than the channel spacing, usually one-half or one-fourth. There are trade-offs between fractional spurs, sub-fractional spurs, and phase noise. The rules of thumb presented in this section are just that. There will be exceptions. The bits that impact the fractional spurs are FM and DITH, and these bits should be set in this order. The first step to do is choose FM, for the delta sigma modulator order. TI recommends to start with FM = 3 for a third order modulator and use strong dithering. In general, there is a trade-off between primary and sub-fractional spurs. Choosing the highest order modulator (FM = 0 for 4th order) typically provides the best primary fractional spurs, but the worst sub-fractional spurs. Choosing the lowest modulator order (FM = 2 for 2nd order), typically gives the worst primary fractional spurs, but the best sub-fractional spurs. Choosing FM = 3, for a 3rd order modulator can be a compromise. The second step is to choose DITH, for dithering. Dithering has a very small impact on primary fractional spurs, but a much larger impact on sub-fractional spurs. The only problem is that it can add a few dB of phase noise, or even more if the loop bandwidth is very wide. Disabling dithering (DITH = 0), provides the best phase noise, but the sub-fractional spurs are worst (except when the fractional numerator is 0, and in this case, they are the best). Choosing strong dithering (DITH = 2) significantly reduces sub-fractional spurs, if not eliminating them completely, but adds the most phase noise. Weak dithering (DITH = 1) can be a compromise. The third step is to tinker with the fractional word. Although 1/10 and 400/4000 are mathematically the same, expressing fractions with much larger fractional numerators often improve the fractional spurs. Increasing the fractional denominator only improves spurs to a point. A good practical limit could be to keep the fractional denominator as large as possible, not exceeding 4095. It is not necessary to use the extended fractional numerator or denominator. NOTE For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction, Fastlock, and many other topics, visit http://www.ti.com. The clock design and clock architect simulation tools and an online reference called PLL Performance, Simulation, and Design. 24 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 8.4 Device Functional Modes 8.4.1 Power Pins, Power-Down, and Power-Up Modes RI recommends that all of the power pins be filtered with a series 18-Ω resistor and then placing two capacitors shunt to ground, thus creating a low pass filter. Although it makes sense to use large capacitor values in theory, the ESR ( Equivalent Series Resistance ) is greater for larger capacitors. For optimal filtering minimize the sum of the ESR and theoretical impedance of the capacitor. It is therefore recommended to provide two capacitors of very different sizes for the best filtering. 1 µF and 100 pF are typical values. The small capacitor should be placed as close as possible to the pin. The power down state of the LMX2487 is controlled by many factors. The one factor that overrides all other factors is the CE pin. If this pin is low, the part will be powered down. Asserting a high logic level on this pin is necessary to power up the chip, however, there are other bits in the programming registers that can override this and put the PLL back in a power down state. Provided that the voltage on the CE pin is high, programming the RF_PD and IF_PD bits to zero ensures that the part will be powered up. Programming either one of these bits to one will power down the appropriate section of the synthesizer, provided that the ATPU bit does not override this. Table 9. Powerdown Modes CE PIN RF_PD ATPU BIT ENABLED + N COUNTER WRITE Low X X Powered Down (Asynchronous) High X Yes Powered Up High 0 No Powered Up High 1 No Powered Down ( Asynchronous ) PLL STATE Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 25 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 8.5 Programming 8.5.1 General Programming Information The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program the R counter, the N counter, and the internal mode control latches. The data format of a typical 24-bit data register is shown in Table 10. The control bits CTL [3:0] decode the register address. On the rising edge of LE, data stored in the shift register is loaded into one of the appropriate latches (selected by address bits). Data is shifted in MSB first. NOTE It is best to program the N counter last, because doing so initializes the digital lock detector and Fastlock circuitry. Initialize means it resets the counters, but it does NOT program values into these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program the R7 register. Table 10. Register Structure MSB LSB DATA [21:0] CTL [3:0] 23 4 3 2 1 0 8.5.1.1 Register Location Truth Table The control bits CTL [3:0] decode the internal register address. Table 11 shows how the control bits are mapped to the target control register. Table 11. Programmable Registers C3 26 C2 C1 C0 DATA LOCATION x x x 0 R0 0 0 1 1 R1 0 1 0 1 R2 0 1 1 1 R3 1 0 0 1 R4 1 0 1 1 R5 1 1 0 1 R6 1 1 1 1 R7 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 8.5.1.2 Control Register Content Map Because the LMX2487 registers are complicated, they are organized into two groups, basic and advanced. The first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that optimize spur, phase noise, and lock time performance. The next page shows these registers. Although it is highly recommended that the user eventually take advantage of all the modes of the LMX2487, the quick start register map is shown in order for the user to get the part up and running quickly using only those bits critical for basic functionality. The following default conditions for this programming state are a third order deltasigma modulator in 12-bit mode with no dithering and no Fastlock. Table 12. Quick Start Register Map REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 DATA[19:0] ( Except for the RF_N Register, which is [22:0] ) R0 RF_N[10:0] R1 RF_ PD R2 IF_P D R3 R4 RF_ P 2 1 0 C2 C1 C0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 RF_FN[11:0] RF_R[5:0] 0 RF_FD[11:0] IF_N[18:0] 0001 0 3 C3 0 RF_CPG[3:0] 1 0 0 0 0 IF_R[11:0] 0 1 1 0 0 0 1 1 1 0 0 0 0 The complete register map shows all the functionality of all registers, including the last five. Table 13. Complete Register Map REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 DATA[19:0] ( Except for the RF_N Register, which is [22:0] ) R0 RF_N[10:0] R1 RF_ PD R2 IF_P D R3 R4 RF_ P 1 RF_CPG[3:0] 0 R5 0 0 IF_R[11:0] DITH [1:0] FM [1:0] 0 OSC _2X OSC _OU T IF_ CPP RF_FD[21:12] R6 CSR[1:0] R7 0 0 0 0 RF_ CPP IF_P MUX [3:0] RF_FN[21:12] RF_CPF[3:0] 0 RF_TOC[13:0] 0 1 0 C1 C0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 RF_FD[11:0] IF_N[18:0] 0 2 C2 RF_FN[11:0] RF_R[5:0] ACCESS[3:0] ATP U 3 C3 0 0 0 0 DIV4 0 1 0 0 1 IF_ RST RF_ RST IF_ CPT RF_ CPT Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 27 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 8.6 Register Maps 8.6.1 R0 Register NOTE This register has only one control bit, so the N counter value to be changed with a single write statement to the PLL. Table 14. R0 Register REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA[22:0] R0 C0 RF_N[10:0] RF_FN[11:0] 0 8.6.1.1 RF_FN[11:0] – Fractional Numerator for RF PLL Refer to Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] } for a more detailed description of this control word. 8.6.1.2 RF_N[10:0] – RF N Counter Value The RF N counter contains an 16/17/20/21 and a 32/33/36/37 prescaler. The N counter value can be calculated by Equation 6: N = RF_P × RF_C + 4 × RF_B + RF_A (6) RF_C ≥Max{RF_A, RF_B} , for N-2FM-1 ... N+2FM is a necessary condition. This rule is slightly modified in the case where the RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for the purposes of modulation. Consult Table 15 and Table 16 for valid operating ranges for each prescaler. Table 15. Operation With the 16/17/20/21 Prescaler (RF_P=0) RF_N [10:0] RF_N RF_C [5:0] RF_B [2:0] 1023 N values above 1023 are prohibited. Table 16. Operation With the 32/33/36/37 Prescaler (RF_P=1) RF_N [10:0] RF_N RF_B [2:0] RF_A [1:0] 2045 N values greater than 2045 are prohibited. 8.6.2 R1 Register Table 17. R1 Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 C2 C1 C0 0 0 1 1 REGISTER DATA[19:0] RF_P D R1 RF_ P RF_R[5:0] RF_FD[11:0] 8.6.2.1 RF_FD[11:0] – RF PLL Fractional Denominator The function of these bits are described in Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], ACCESS[1]}. 8.6.2.2 RF_R [5:0] – RF R Divider Value The RF R Counter value is determined by this control word. NOTE This counter does allow values down to one. Table 18. RF PLL R Divider R VALUE RF_R[5:0] 1 0 0 0 0 0 1 ... . . . . . . 63 1 1 1 1 1 1 8.6.2.3 RF_P – RF Prescaler bit The prescaler used is determined by this bit. Table 19. RF PLL Prescaler RF_P PRESCALER MAXIMUM FREQUENCY 0 16/17/20/21 4000 MHz 1 32/33/36/37 6000 MHz 8.6.2.4 RF_PD – RF Power Down Control Bit When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and the RF Charge pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions, and will override the RF_PD bit. The order of precedence is as follows. First, if the CE pin is LOW, then the PLL will be powered down. Provided this is not the case, the PLL will be powered up if the ATPU bit says to do so, regardless of the state of the RF_PD bit. After the CE pin and the ATPU bit are considered, then the RF_PD bit then takes control of the power down function for the RF PLL. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 29 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 8.6.3 R2 Register Table 20. R2 Register REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 DATA[19:0] R2 IF_ PD 3 2 1 0 C3 C2 C1 C0 0 1 0 1 IF_N[18:0] 8.6.3.1 IF_N[18:0] – IF N Divider Value Table 21. IF_N Counter Programming with the 8/9 Prescaler (IF_P=0) IF_N[18:0] N VALUE IF_B IF_A ≤23 N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required. 24-55 Legal divide ratios in this range are: 24-27, 32-36, 40-45, 48-54 56 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 57 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 ... . . . . . . . . . . . . . . . . . . . 262143 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 Table 22. Operation With the 16/17 Prescaler (IF_P=1) N VALUE IF_B IF_A ≤47 N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required. 48-239 Legal divide ratios in this range are: 48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238 240 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 241 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 ... . . . . . . . . . . . . . . . . . . . 524287 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8.6.3.2 IF_PD – IF Power Down Bit When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be powered down, overriding the IF_PD bit. 8.6.4 R3 Register Table 23. R3 Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 C2 C1 C0 0 1 1 1 REGISTER DATA[19:0] R3 30 ACCESS[3:0] RF_CPG[3:0] IF_R[11:0] Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 8.6.4.1 IF_R[11:0] – IF R Divider Value For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for IF_R is 3. Table 24. IF PLL R Divider R VALUE IF_R[11:0] 3 0 0 0 0 0 0 0 0 0 0 1 1 ... . . . . . . . . . . . . 4095 1 1 1 1 1 1 1 1 1 1 1 1 8.6.4.2 RF_CPG – RF PLL Charge Pump Gain This is used to control the magnitude of the RF PLL charge pump in steady-state operation. Table 25. RF PLL Charge Pump Gain TYPICAL RF CHARGE PUMP CURRENT AT 3 V (µA) RF_CPG CHARGE PUMP STATE 0 1X 95 1 2X 190 2 3X 285 3 4X 380 4 5X 475 5 6X 570 6 7X 665 7 8X 760 8 9X 855 9 10X 950 10 11X 1045 11 12X 1140 12 13X 1235 13 14X 1330 14 15X 1425 15 16X 1520 8.6.4.3 Access – Register Access word It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional. The ACCESS[3:0] bits determine which additional registers need to be programmed. Any one of these registers can be individually programmed. According to Table 26, when the state of a register is in default mode, all the bits in that register are forced to a default state and it is not necessary to program this register. When the register is programmable, it needs to be programmed through the MICROWIRE. Using this register access technique, the programming required is reduced up to 37%. Table 26. Access word ACCESS BIT REGISTER LOCATION REGISTER CONTROLLED ACCESS[0] R3[20] Must be set to 1 ACCESS[1] R3[21] R5 ACCESS[2] R3[22] R6 ACCESS[3] R3[23] R7 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 31 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com The default conditions the registers is shown in Table 27: Table 27. Default Register Settings REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Data[19:0] R4 3 2 1 0 C3 C2 C1 C0 R4 Must be programmed manually. R5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 R6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 R7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 1 This corresponds to the following bit settings. Table 28. Default Word Settings REGISTER BIT LOCATION BIT NAME BIT DESCRIPTION BIT VALUE BIT STATE R4[23] ATPU Autopowerup 0 Disabled R4[17:16] DITH Dithering 2 Strong R4[15:16] FM Modulator Order 3 3rd Order R4[23] OSC_2X Oscillator Doubler 0 Disabled R4[23] OSC_OUT OSCout Pin Enable 0 Disabled R4[23] IF_CPP IF Charge Pump Polarity 1 Positive R4[23] RF_CPP RF Charge Pump Polarity 1 Positive R4 R4[23] IF_P IF PLL Prescaler 1 16/17 R4[7:4] MUX Ftest/LD Output 0 Disabled R5[23:14] RF_FD[21:12] Extended Fractional Denominator 0 Disabled R5[13:4] RF_FN[21:12] Extended Fractional Numerator 0 Disabled R6[23:22] CSR Cycle Slip Reduction 0 Disabled R6[21:18] RF_CPF Fastlock Charge Pump Current 0 Disabled R6[17:4] RF_TOC RF Timeout Counter 0 Disabled R7[13] DIV4 Lock Detect Adjustment 0 Disabled (Fcomp ≤ 20 MHz) R7[7] IF_RST IF PLL Counter Reset 0 Disabled RF_RST RF PLL Counter Reset 0 Disabled R5 R6 R7 R7[6] R7[5] IF_CPT IF PLL Tri-State 0 Disabled R7[4] RF_CPT RF PLL Tri-State 0 Disabled 8.6.5 R4 Register This register controls the conditions for the RF PLL in Fastlock. Table 29. R4 Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 C2 C1 C0 1 0 0 1 REGISTER DATA[19:0] R4 32 ATP U 0 1 0 0 0 DITH [1:0] FM [1:0] 0 OSC _2X OSC _OU T IF_ CPP Submit Documentation Feedback RF_ CPP IF_P MUX [3:0] Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 8.6.5.1 MUX[3:0] Frequency Out & Lock Detect MUX These bits determine the output state of the Ftest/LD pin. Table 30. Ftest/LD Programming MUX[3:0] OUTPUT TYPE OUTPUT DESCRIPTION 0 0 0 0 High Impedance Disabled 0 0 0 1 Push-Pull General-purpose output, Logical “High” State 0 0 1 0 Push-Pull General-purpose output, Logical “Low” State 0 0 1 1 Push-Pull RF & IF Digital Lock Detect 0 1 0 0 Push-Pull RF Digital Lock Detect 0 1 0 1 Push-Pull IF Digital Lock Detect 0 1 1 0 Open Drain RF & IF Analog Lock Detect 0 1 1 1 Open Drain RF Analog Lock Detect 1 0 0 0 Open Drain IF Analog Lock Detect 1 0 0 1 Push-Pull RF & IF Analog Lock Detect 1 0 1 0 Push-Pull RF Analog Lock Detect 1 0 1 1 Push-Pull IF Analog Lock Detect 1 1 0 0 Push-Pull IF R Divider divided by 2 1 1 0 1 Push-Pull IF N Divider divided by 2 1 1 1 0 Push-Pull RF R Divider divided by 2 1 1 1 1 Push-Pull RF N Divider divided by 2 8.6.5.2 IF_P – IF Prescaler When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used. Table 31. IF PLL Prescaler IF_P IF PRESCALER MAXIMUM FREQUENCY 0 8/9 800 MHz 1 16/17 800 MHz 8.6.5.3 RF_CPP – RF PLL Charge Pump Polarity Table 32. RF PLL Charge Pump Polarity RF_CPP RF CHARGE PUMP POLARITY 0 Negative 1 Positive (Default) Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 33 LMX2487 SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 8.6.5.4 IF_CPP – IF PLL Charge Pump Polarity For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase detector polarity. Table 33. IF PLL Charge Pump Polarity IF_CPP IF CHARGE PUMP POLARITY 0 Negative 1 Positive 8.6.5.5 OSC_OUT Oscillator Output Buffer Enable Table 34. OSCout Pin Settings OSC_OUT OSCout PIN 0 Disabled (High Impedance) 1 Buffered output of OSCin pin 8.6.5.6 OSC2X – Oscillator Doubler Enable When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF R counters is equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency presented to the RF R counter is doubled. Phase noise added by the doubler is negligible. Table 35. OSCin Doubler OSC2X FREQUENCY PRESENTED TO RF R COUNTER FREQUENCY PRESENTED TO IF R COUNTER 0 fOSCin fOSCin 1 2 x fOSCin 8.6.5.7 FM[1:0] – Fractional Mode Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least one greater than the order of the delta-sigma modulator in order to allow for sufficient roll-off. Table 36. Programmable Modulator Order Settings FM FUNCTION 0 Fractional PLL mode with a 4th order delta-sigma modulator 1 Disable the delta-sigma modulator. Recommended for test use only. 2 Fractional PLL mode with a 2nd order delta-sigma modulator 3 Fractional PLL mode with a 3rd order delta-sigma modulator 8.6.5.8 DITH[1:0] – Dithering Control Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific. Enabling the dithering may also increase the phase noise. In most cases where the fractional numerator is zero, dithering usually degrades performance. Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often occurs when the loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends not to impact the main fractional spurs much, but has a much larger impact on the sub-fractional spurs. If it is decided that dithering will be used, best results will be obtained when the fractional denominator is at least 1000. 34 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: LMX2487 LMX2487 www.ti.com SNAS322C – FEBRUARY 2006 – REVISED JANUARY 2016 Table 37. Dithering Settings DITH DITHERING MODE USED 0 Disabled 1 Weak Dithering 2 Strong Dithering 3 Reserved 8.6.5.9 ATPU – PLL Automatic Power Up When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0 register is written to, the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case is when the CE pin is low. In this case, the ATPU function is disabled. 8.6.6 R5 Register Table 38. R5 Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 C2 C1 C0 1 0 1 1 REGISTER DATA[19:0] R5 RF_FD[21:12] RF_FN[21:12] 8.6.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] } In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12] bits become do not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the fractional numerator is expanded from 12 to 22-bits. Table 39. Fractional Numerator Determination FRACTIONAL RF_FN[21:12] NUMERATOR (These bits only apply in 22-bit mode) RF_FN[11:0] 0 In 12-bit mode, these are do not care. In 22-bit mode, for N