OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
LMX2505 PLLatinum™ Dual Frequency Synthesizer System with Integrated VCOs
Check for Samples: LMX2505
FEATURES
APPLICATIONS
•
•
1
23
•
•
•
•
•
•
•
Small Size
– 5.0 mm X 5.0 mm X 0.75 mm 28-Pin WQFN
Package
RF Synthesizer System
– Two Integrated VCOs
– Integrated Loop Filter
– Low Spurious, Low Phase Noise FractionalN RF PLL Based on 10-Bit Delta Sigma
Modulator
– Frequency Resolution Down to 20 kHz
Supports Various Reference Frequencies
– 12.6/14.4/25.2/26.0 MHz
Fast Lock Time: 300 µs
Low Current Consumption
– 10 mA at 2.8 V in PDC800 Mode
2.5 V to 3.3 V Operation
Digital Filtered Lock Detect Output
Hardware and Software Power Down Control
Japan PDC Systems at 800 MHz and 1500 MHz
Frequency Bands
DESCRIPTION
LMX2505 is a highly integrated, high performance,
low power frequency synthesizer system optimized
for dual-band Japan PDC mobile handsets. Using a
proprietary digital phase locked loop technique,
LMX2505 generates very stable, low noise local
oscillator signals for up and down conversion in
wireless communications devices.
LMX2505 includes dual voltage controlled oscillators
(VCOs) for the upper and lower Japan PDC
frequency bands, a loop filter, and a fractional-N RF
PLL based on a delta sigma modulator. In concert
these blocks form a closed loop RF synthesizer
system. The RF synthesizer system supports two
frequency bands: PDC1500 and PDC800.
Serial data is transferred to the device via a threewire MICROWIRE interface (DATA, LE, CLK).
Operating supply voltage ranges from 2.5 V to 3.3 V.
LMX2505 features low current consumption: 10 mA at
2.8 V when operating in the PDC800 mode.
LMX2505 is available in a 28-pin WQFN package.
Functional Block Diagram
RF R
Divider
OSCin
RF
Phase
Detector
Loop
Filter
RF1out
RF1 VCO
RF2out
VCC
VDD
CE
RF2 VCO
Power
Down
Control
CLK
DATA
Serial
Interface
RF N/(N+1)
Divider
Band
Select
Delta Sigma
Control
LE
BS
Lock
Detect
LD
GND
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PLLatinum is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
OBSOLETE
LMX2505
SNWS008D – MAY 2004 – REVISED MAY 2004
www.ti.com
VCC
LD
BS
CE
CLK
DATA
LE
28
27
26
25
24
23
22
Connection Diagram
OSCin
1
21
VCC
GND
2
20
GND
VDD
3
19
VCC
GND
4
18
GND
NC
5
17
VDD
NC
6
16
RF2out
VDD
7
15
VDD
10
11
12
13
14
L2
NC
VDD
RF1out
9
L1
NC
8
NC
GND
NOTE: Analog ground connected through exposed die attached pad.
Figure 1. 28-Pin 5x5 WQFN (NJB0028A) Package
PIN DESCRIPTIONS
2
Pin Number
Name
I/O
1
OSCin
I
Description
Reference frequency input
2
GND
—
Ground for digital circuitry
3
VDD
—
Supply voltage for analog circuitry
4
GND
—
Ground for analog circuitry
5
NC
—
Do not connect to any node on the printed circuit board.
6
NC
—
Do not connect to any node on the printed circuit board.
7
VDD
—
Supply voltage for RF analog circuitry
8
NC
—
Do not connect to any node on the printed circuit board.
9
L1
—
RF2 VCO tank pin. An external inductor is required between pins L1 and L2 to
set the resonant frequency of RF2 VCO (PDC800).
10
L2
—
RF2 VCO tank pin. An external inductor is required between pins L1 and L2 to
set the resonant frequency of RF2 VCO (PDC800).
11
NC
—
Do not connect to any node on the printed circuit board.
12
NC
—
Do not connect to any node on the printed circuit board.
13
VDD
—
Supply voltage for RF analog circuitry
14
RF1out
O
RF output of RF1 VCO for PDC1500
15
VDD
—
Supply voltage for RF analog circuitry
16
RF2out
O
RF output of RF2 VCO for PDC800
17
VDD
—
Supply voltage for analog circuitry
18
GND
—
Ground for digital circuitry
19
VCC
—
Supply voltage for digital circuitry
20
GND
—
Ground for digital circuitry
21
VCC
—
Supply voltage for digital circuitry
22
LE
I
MICROWIRE Latch Enable
23
DATA
I
MICROWIRE Data
24
CLK
I
MICROWIRE Clock
25
CE
I
Chip enable control pin
26
BS
I
Band select control pin
27
LD
O
Lock detect pin
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
PIN DESCRIPTIONS (continued)
Pin Number
Name
I/O
Description
28
VCC
—
Supply voltage for digital circuitry
Typical Application Circuit
30
0.1 PF
0.1 PF
1 PF
47 pF
RF2out
0.1 PF
1
+
16
RF2out
15
VDD
17
19
20
18
GND
VDD
NC
VDD
7
VCC
VIN
10 PF
VCC
LD
NC
28
100
100 pF
L1
L1 9
NC 8
6
LD
BS
5
27
LMX2505
GND
26
CE
4
CE
NC 12
NC 11
L2 10
CLK
VDD
25
RF1out
DD
GND
24
CLK
DATA
3
DATA
47 pF
RF1out 14
13
V
LE
OSCin
23
2
22
LE
GND
VCC
21
100 pF
1PF
100 pF
100 pF
OSCin
0.1 PF
Refer to RF2 VCO Tuning Range vs. External Inductance plot to aid in selecting the appropriate external inductance,
PCB trace and L1, for the desired frequency range.
Figure 2. Typical Application Circuit
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
(3) (4)
Parameter
Symbol
Ratings
Supply Voltage
VCC, VDD
-0.5 to 3.6
V
Voltage on any pin to GND
VI
-0.3 to VCC+0.3
V
Storage Temperature
Range
(1)
(2)
(3)
(4)
TSTG
Units
-0.3 to VDD+0.3
V
-65 to 150
°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed
specifications and test conditions, refer to the Electrical Characteristics section. The guaranteed specifications apply only for the
conditions listed.
This device is a high performance RF integrated circuit with an ESD rating < 2 kV and is ESD sensitive. Handling and assembly of this
device should be done at ESD protected workstations.
GND = 0 V.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
3
OBSOLETE
LMX2505
SNWS008D – MAY 2004 – REVISED MAY 2004
www.ti.com
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Temperature
TA
-30
25
85
°C
Supply Voltage (to GND)
VCC, VDD
2.5
3.3
V
Electrical Characteristics (1)
(VIN = 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are for TA = 25 °C; Limits in boldface type apply
over the operating temperature range from -20 °C ≤ TA ≤ 75 °C unless otherwise noted.)
Symbol
Parameter
Condition
Min
Typ
Max
Units
OB_CRL [1:0] = 11
11.5
13.0
13.3
mA
OB_CRL [1:0] = 00
10.0
11.5
11.8
mA
OB_CRL [1:0] = 11
16.0
17.5
17.8
mA
OB_CRL [1:0] = 00
14.2
15.6
15.9
mA
20
µA
14.4
26.0
MHz
0.5
VCC
Vp-p
1394.95
MHz
ICC PARAMETERS
ICC + IDD
ICC + IDD
IPD
Supply Current (2)
Supply Current (3)
Power Down Current
CE = LOW or
RF_PD = 1
REFERENCE OSCILLATOR PARAMETERS
fOSCin
Reference Oscillator Input Frequency (4)
VOSCin
Reference Oscillator Input Sensitivity
12.6/14.4/25.2/26.0 MHz are
supported.
12.6
RF1 VCO for PDC1500
fRF1out
Frequency Range (5)
RF1 VCO for PDC1500
PRF1out
Output Power
OB_CRL [1:0] = 11
-5
-2
1
dBm
OB_CRL [1:0] = 10
-7
-4
-1
dBm
OB_CRL [1:0] = 01
-10
-7
-4
dBm
OB_CRL [1:0] = 00
-13
-10
Lock Time
1270.22
-7
dBm
Full frequency span within each
band in High Speed Mode.
300 (6)
µs
Between bands High Speed
Mode.
300 (6)
µs
Full frequency span within each
band in Normal Mode.
500 (6)
µs
375 (7)
µs
(6)
µs
Between bands in Normal
Mode.
RMS Phase Error
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
500
400 (7)
1.3
µs
degrees
All limits are ensured. All electrical characteristics having room temperature limits are tested during production with TA = 25 °C or
correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are ensured by correlating the electrical characteristics
to process and temperature variations and applying statistical process control.
RF PLL and VCO in PDC800 mode.
RF PLL and VCO in PDC1500 mode.
The reference frequency must also be programmed using the OSC_FREQ control bit. For other reference frequencies, please contact
Texas Instruments.
For other frequency ranges, please contact Texas Instruments.
Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency
remains within +/-1 kHz of the final frequency.
Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency
remains within +/-3 kHz of the final frequency.
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
Electrical Characteristics(1) (continued)
(VIN = 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are for TA = 25 °C; Limits in boldface type apply
over the operating temperature range from -20 °C ≤ TA ≤ 75 °C unless otherwise noted.)
Symbol
Parameter
Condition
Typ
Max
Units
L(f)RF1out
Phase Noise when RF1 VCO for
PDC1500 is activated in Normal Mode.
@ 25 kHz offset
Min
-95
-93
-91
dBc/Hz
@ 50 kHz offset
-106
-103
-101
dBc/Hz
@ 100 kHz offset
-115
-113
-111
dBc/Hz
-135
-133
dBc/Hz
-25
dBc
@ 1 MHz offset
2nd Harmonic Suppression
3rd Harmonic Suppression
Spurious Tones
-20
dBc
@ ≤ 25 kHz offset
-45
dBc
@ 25 kHz < offset ≤ 50 kHz
-60
dBc
@ 50 kHz < offset ≤ 100 kHz
-69
dBc
@ offset > 100 kHz
-75
dBc
RF2 VCO for PDC800
fRF2out
Frequency Range (5)
RF2 VCO for PDC800
768
MHz
PRF2out
Output Power
OB_CRL [1:0] = 11
-6
-3
0
dBm
OB_CRL [1:0] = 10
-9
-6
-3
dBm
OB_CRL [1:0] = 01
-11
-8
-5
dBm
OB_CRL [1:0] = 00
-15
-12
Lock Time
633.15
-9
dBm
Full frequency span within each
band in High Speed Mode.
300 (6)
µs
Between bands High Speed
Mode.
300 (6)
µs
Full frequency span within each
band in Normal Mode.
500 (6)
µs
375 (7)
µs
(6)
µs
Between bands in Normal
Mode.
500
400 (7)
RMS Phase Error
L(f)RF2out
Phase Noise when RF2 VCO for
PDC800 is activated in Normal Mode.
1.3
µs
degrees
@ 25 kHz offset
-95
-93
-91
dBc/Hz
@ 50 kHz offset
-106
-103
-101
dBc/Hz
@ 100 kHz offset
-115
-113
-111
dBc/Hz
-135
-133
dBc/Hz
2nd Harmonic Suppression
-25
dBc
3rd Harmonic Suppression
-20
dBc
@ ≤ 25 kHz offset
-45
dBc
@ 25 kHz < offset ≤ 50 kHz
-60
dBc
@ 50 kHz < offset ≤ 100 kHz
-69
dBc
@ offset > 100 kHz
-75
dBc
0.8 VCC
VCC
V
0.8 VDD
VDD
V
-0.3
0.2 VCC
V
-0.3
0.2 VDD
V
-10
10
µA
@ 1 MHz offset
Spurious Tones
DIGITAL INTERFACE (DATA, CLK, LE, LD, CE, BS)
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
5
OBSOLETE
LMX2505
SNWS008D – MAY 2004 – REVISED MAY 2004
www.ti.com
Electrical Characteristics(1) (continued)
(VIN = 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are for TA = 25 °C; Limits in boldface type apply
over the operating temperature range from -20 °C ≤ TA ≤ 75 °C unless otherwise noted.)
Symbol
Parameter
IIL
Low-Level Input Current
VOH
VOL
Condition
Min
Typ
-10
Max
Units
10
µA
Input Capacitance
3
pF
Rise/Fall Time
30
ns
High-Level Output Voltage
VCC - 0.4
V
VDD - 0.4
V
Low-Level Output Voltage
Output Capacitance
0.4
V
5
pF
MICROWIRE INTERFACE TIMING
tCS
Data to Clock Set Up Time
50
ns
tCH
Data to Clock Hold Time
10
ns
tCWH
Clock Pulse Width HIGH
50
ns
tCWL
Clock Pulse Width LOW
50
ns
tES
Clock to Latch Enable Set Up Time
50
ns
tEW
Latch Enable Pulse Width
50
ns
Figure 3. Microwire Interface Timing Diagram
6
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
Typical Performance Characteristics (1)
900
850
Typical Maximum Frequency
FREQUENCY (MHz)
800
750
700
Minimum Maximum Frequency
Maximum Minimum Frequency
650
600
550
Typical Minimum Frequency
500
2.0
2.5
3.0
3.5
4.0
EXTERNAL INDUCTANCE (nH)
The frequency range is defined as the difference between the highest frequency and the lowest frequency of a given unit. For a chosen
external inductance, the typical frequency range equals the difference between the Typical Maximum Frequency and the Typical Minimum
Frequency. Typical frequency range may be assumed on any unit with that chosen external inductance, even if the unit has worst case
Maximum Frequency or worst case Minimum Frequency.
Figure 4. RF2 VCO Tuning Range vs. External Inductance VIN = 2.8 V
(1)
Typical performance characteristics do not ensure specific performance limits. For ensured specifications, refer to the Electrical
Characteristics section.
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
7
OBSOLETE
LMX2505
SNWS008D – MAY 2004 – REVISED MAY 2004
www.ti.com
FUNCTIONAL DESCRIPTION
GENERAL
The LMX2505 is a highly integrated frequency synthesizer system for Japan PDC wireless communication
systems. The LMX2505 supports dual band operation for 800 MHz and 1500 MHz.
The LMX2505 includes all functional blocks for the RF PLL including RF VCOs, frequency dividers, PFDs, and
loop filters. Only external passive elements for the RF2 VCO tank and supply bypassing are required to complete
the RF synthesizer.
The LMX2505 uses a patent pending Fractional-N synthesizer architecture based on a delta sigma modulator to
support fine frequency resolution. Four of the most common reference frequencies for PDC applications, 12.6
MHz, 14.4 MHz, 25.2 MHz and 26.0 MHz, are supported. The unique feature of this architecture is its low
spurious modulation effect.
The use of a fractional synthesizer based on delta sigma modulator allows for fast lock-up and system set-up
times, which reduces system power consumption. The loop filter is included in the circuit to minimize the external
noise coupling and reduce the form factor applicable to the board level application. Only one of the two RF VCOs
is activated at a given time, and each output is provided through its own output pin.
RF_PLL SECTION
Frequency Selection
The divide ratio can be calculated using the following equations:
fVCO = {8 x RF_B + RF_A + (RF_FN / FD)} x (fOSC / R) where (RF_A < RF_B) for PDC1500
fVCO = {4 x RF_B + RF_A + (RF_FN / FD)} x (fOSC / R) where (RF_A < RF_B) for PDC800
where
•
•
•
•
•
•
•
fVCO: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable counter (2 ≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤ RF_A ≤ 7 for PDC1500 and 0 ≤ RF_A ≤ 3 for
PDC800)
RF_FN: Preset numerator of binary 10-bit modulus counter (0 ≤ RF_FN < FD)
FD: Preset denominator for modulus counter (FD = fOSC/(R X fCH) where fCH is the channel spacing)
fOSC: Reference oscillator frequency
R: Internal reference oscillator frequency divider (1 for 12.6 MHz and 14.4 MHz, 2 for 25.2 MHz and 26.0 MHz)
The denominator, FD, in the above equation is dependent on the channel spacing and reference oscillator
frequency. The channel spacing will change based on the Rx/Tx and BS bits. Table 8 in the R0 Register section
summarizes the values of FD.
VCO Frequency Tuning
The center frequency of the RF VCOs is determined by the resonant frequency of the tank circuit, illustrated in
Figure 5. With an internal fixed bonding-wire inductor and an external inductance, the center frequency of the
VCO is given as follows:
fcenter =
1
2S
( L fixed + L external ) ˜ C total
where Ctotal is the total capacitance of the VCO, including the parasitic capacitance and the nominal self-tuning
capacitance. Note, the external inductance consists of the PCB traces and lumped element inductor. The output
frequency tuning range can be optimized for the specific application by selecting the appropriate external
inductance. Refer to RF2 VCO Tuning Range vs. External Inductance plot to aid in selecting the appropriate
external inductance. Care should be taken to ensure proper frequency coverage when choosing the tolerance of
the lumped element inductor. For the 1500 MHz band, the internal bonding-wires provide the necessary
inductance to set the VCO center frequency.
8
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
LMX2505
Board
Lfixed
2
Active
Device
Ctotal
Lexternal
Lfixed
2
Figure 5. External Inductor Connection
In real implementation, the inductance of Lfixed and Lexternal can vary from its nominal value. The LMX2505 utilizes
a built-in tracking algorithm to compensate for variations up to ±15% and tunes the VCO to the required
frequency. During the frequency acquisition period, the loop bandwidth is extended to achieve the frequency
lock. After the frequency lock, the loop bandwidth of the PLL is set to the nominal value and the phase lock is
achieved. The transition between the two operating modes is very smooth and extremely fast to meet the
stringent PDC requirements for lock time and phase noise.
POWER DOWN MODE
The LMX2505 includes the power down mode to reduce the power consumption. The LMX2505 enters the power
down mode either by taking the CE pin LOW or by setting the RF_PD bit in the R0 register. If the CE pin is set
LOW, the circuit is powered down regardless of the register values. When the CE pin is HIGH, the RF_PD bit
controls power to the RF circuitry. Data can be written to the registers even when the CE pin is set LOW. The
following truth table summarizes the power down logic.
Table 1. Power Down Modes
CE Pin
RF_PD Bit
Mode
HIGH
0
Active
HIGH
1
Not Active
LOW
0
Not Active
LOW
1
Not Active
BAND SELECT MODE
The BS pin and BS bit can be used to select one of the two RF VCO outputs. When using the BS pin, the BS bit
must be set to 0, and when using the BS bit, the BS pin must be tied to ground. When using the BS pin, the state
of the input must exceed the minimum band select set up time prior to the LE signal transition. The truth table
summarizing the band select logic is as follows:
Table 2. Band Select Modes
BS Pin
BS Bit
Mode
HIGH
0
PDC1500
LOW
0
PDC800
LOW
1
PDC1500
LOCK DETECT MODE
The LD output can be used to indicate the lock status of the PLL. Bit 6 in Register R1 determines the signal that
appears on the LD pin. When the PLL is not locked, the LD pin remains LOW. After obtaining phase lock, the LD
pin will have a logical HIGH level. The LD output is always LOW when the LD register bit is 0 and in power down
mode.
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
9
OBSOLETE
LMX2505
SNWS008D – MAY 2004 – REVISED MAY 2004
www.ti.com
Table 3. Lock Detect Modes
LD Bit
Mode
0
Disable (GND)
1
Enable
Table 4. Lock Detect Logic
RF PLL Section
LD Output
Locked
HIGH
Not Locked
LOW
fR/64
fN/64
't > tW1
't > tW2
LD
(1)
LD output becomes LOW when the phase error is larger than tW2.
(2)
LD output becomes HIGH when the phase error is less than tW1 for four or more consecutive cycles.
(3)
Phase Error is measured on leading edge. Only errors greater than tW1 and tW2 are labeled.
(4)
tW1 is 5 ns for PDC1500 and 10 ns for PDC800. tW2 is 10 ns for both bands.
(5)
The lock detect comparison occurs with every 64th cycle of fR and fN.
Figure 6. Lock Detect Timing Diagram Waveform
10
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
START
LD = LOW
(Not Locked)
NO
Phase Error < tW1
YES
NO
Phase Error < tW1
YES
NO
Phase Error < tW1
YES
NO
Phase Error < tW1
YES
LD = HIGH
(Locked)
NO
YES
Phase Error > tW2
Figure 7. Lock Detect Flow Diagram
HIGH SPEED LOCK-UP MODE
Two frequency-locking modes are provided: a Normal mode and a High Speed mode for faster lock times. The
HS bit in register R0 controls the locking mode.
Table 5. Lock-up Modes
HS Bit
Mode
0
Normal mode
1
High Speed mode
MICROWIRE INTERFACE
The programmable register set is accessed via the MICROWIRE serial interface. The interface is comprised of
three signal pins: CLK, DATA, and LE (Latch Enable). Serial data is clocked into the 24-bit shift register on the
rising edge of the clock. The last bits decode the internal control register address. When the latch enable (LE)
transitions from LOW to HIGH, data stored in the shift registers is loaded into the corresponding control register.
The data is loaded MSB first.
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
11
OBSOLETE
LMX2505
SNWS008D – MAY 2004 – REVISED MAY 2004
www.ti.com
Programming Description
GENERAL PROGRAMMING INFORMATION
The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming data is
first loaded into the shift register from MSB to LSB. The data is shifted at the rising edge of the clock signal.
When the latch enable signal transitions from LOW to HIGH, the data stored in shift register is transferred to the
proper register depending on the address bit setting. The selection of the particular register is determined by the
control bits indicated in boldface text.
At initial start-up, the MICROWIRE loading requires three default words (registers R2, loaded first, to R0, loaded
last). After the device has been initially programmed, the RF VCO frequency can be changed using a single
register (R0).
The control register content map describes how the bits within each control register are allocated to the specific
control functions.
12
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
Table 6. COMPLETE REGISTER MAP (1) (2)
Regi
ster
MSB
18
17
16
15
14
22
21
20
19
RF_
PD
HS
0
BS
R1
SPI_
(Defa DEF
ult)
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
LD
OB_
CRL
[1:0]
R2
1
(Defa
ult)
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
R3
1
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
R4
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
1
R5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RF_B
[3:0]
13
12
11
10
9
LSB
R0
RX/
(Defa TX
ult)
(1)
(2)
23
SHIFT REGISTER BIT LOCATION
8
7
RF_A
[2:0]
6
5
4
3
2
1
0
0
0
0
1
1
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
1
RF_FN
[9:0]
OSC_
FREQ
[1:0]
NOTE: R0 control register will be used when hot start frequency change.
NOTE: Boldface text represent address bits.
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
13
OBSOLETE
LMX2505
SNWS008D – MAY 2004 – REVISED MAY 2004
www.ti.com
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The Rx/Tx bit selects between receive and transmit modes and, in conjunction with the band select bit (BS), the
channel spacing to be synthesized.
The RF_PD bit selects the power down mode of the RF PLL and selected VCO.
The HS bit selects between normal and high speed locking mode.
The BS bit determines which of the two internal VCOs (PDC800 or PDC1500) is active.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A
counter) and the 10-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values
are presented below.
Table 7. R0 REGISTER
Register
MS
B
23
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
LS
B
7
6
5
4
3
2
Data Field
R0
(Default)
RX
/
TX
RF
_
PD
HS
0
BS
RF_B
[3:0]
RF_A
[2:0]
RF_FN
[9:0]
Functions
RX/TX
RX/TX Mode
0 = Rx
1 = Tx
RF_PD
Power Down of RF Synthesizer
0 = RF synthesizer on (Active mode)
1 = RF synthesizer powered down
HS
Locking Mode
0 = Normal Mode
1 = High Speed Mode
BS
Band Select
1 = RF1 VCO (PDC1500)
0 = RF2 VCO (PDC800)
RF_B [3:0]
RF_B Counter
4-bit programmable counter
0 ≤ RF_B ≤ 15 for both bands
RF_A [2:0]
RF_A Counter
3-bit swallow counter
0 ≤ RF_A ≤ 7 for PDC1500
0 ≤ RF_A ≤ 3 for PDC800
RF_FN [9:0]
RF_FN Counter
10-bit modulus counter
0 ≤ RF_FN < FD See Table 8 for FD values.
Counter Name
Symbol
Functions
Modulus Counter
RF_FN
Programmable Counter
RF_B
Swallow Counter
RF_A
RF N Divider
N = 8 x RF_B + RF_A + RF_FN/FD
(PDC1500)
N = 4 x RF_B + RF_A + RF_FN/FD
(PDC800)
Submit Documentation Feedback
0
Address
Field
Name
14
1
0
0
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
PULSE SWALLOW FUNCTION
fVCO = {8 x RF_B + RF_A + (RF_FN / FD)} x fOSC / R where (RF_A < RF_B) for PDC1500
fVCO = {4 x RF_B + RF_A + (RF_FN / FD)} x fOSC / R where (RF_A < RF_B) for PDC800
fVCO: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable counter (2 ≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤ RF_A ≤ 7 for PDC1500 and 0 ≤ RF_A ≤ 3 for
PDC800)
RF_FN: Preset numerator of binary 10-bit modulus counter (0 ≤ RF_FN < FD)
FD: Preset denominator for modulus counter (FD = fOSC/(R x fCH) where fCH is the channel spacing)
fOSC: Reference oscillator frequency
R: Internal reference oscillator frequency divider
OSC_FREQ [1:0]
Reference Oscillator Frequency (MHz)
R Divider
00
12.6
1
01
14.4
1
10
25.2
2
11
26.0
2
The value of the denominator (FD) is depended on the channel spacing and reference oscillator frequency.
Table 8 summarizes the denominator values based on the settings of the Rx/Tx, BS, and OSC_FREQ [1:0] bits.
Table 8. Demonimator Values
Rx/Tx
BS
OSC_FREQ [1:0]
Reference
Oscillator
Frequency (MHz)
R
fCH (kHz)
Denominator
(FD)
0
0
00
12.6
1
25.0
504
0
0
01
14.4
1
25.0
576
0
0
10
25.2
2
25.0
504
0
0
11
26.0
2
25.0
520
0
1
00
12.6
1
25.0
504
0
1
01
14.4
1
25.0
576
0
1
10
25.2
2
25.0
504
0
1
11
26.0
2
25.0
520
1
0
00
12.6
1
20.0
630
1
0
01
14.4
1
20.0
720
1
0
10
25.2
2
20.0
630
1
0
11
26.0
2
20.0
650
1
1
00
12.6
1
22.22
567
1
1
01
14.4
1
22.22
648
1
1
10
25.2
2
22.22
567
1
1
11
26.0
2
22.22
585
R1 REGISTER
The R1 register address bits (R1 [1:0]) are “01”.
The SPI_DEF bit allows for the programming of words R3 to R5. Under most circumstances, the SPI_DEF bit
should be set to 1.
The LD bit sets the function of the lock detect pin. Enabling the lock detect function provides a digital lock detect
output of the active RF synthesizer at the LD pin.
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
15
OBSOLETE
LMX2505
SNWS008D – MAY 2004 – REVISED MAY 2004
www.ti.com
The OB_CRL [1:0] bits determine the power level of the RF output buffer. The power level can be adjusted to
best meet the system requirement.
The reference frequency selection bits, OSC_FREQ [1:0], are used to set the reference clock and R divider for
use with one of the following reference frequencies: 12.6 MHz, 14.4 MHz, 25.2 MHz or 26.0 MHz. The LMX2505
uses the OSC_FREQ bits along with the BS and RX/TX bits to determine the correct divide ratios needed to
meet the required channel spacing for the mode of operation selected. Refer to Table 8 for a summary of
denominator values.
Table 9. R1 REGISTER
Register
MS
B
23
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
LS
B
7
6
5
4
3
2
Data Field
R1
(Default)
SPI 0
_
DE
F
0
1
0
0
1
0
1
0
0
0
1
0
Address
Field
0
0
0
1
0
LD
OB_
CRL
[1:0]
Name
Functions
SPI_DEF
Default Register Selection
0 = OFF (Use values set in R0 to R5)
1 = ON (Use default values set in R0 to R2)
LD
Lock Detect
0 = Disable (GND)
1 = Enable
OB_CRL [1:0]
Output Buffer Control
PDC1500, PDC800
00 = -10 dBm, -12 dBm
01 = -7 dBm, -8 dBm
10 = -4 dBm, -6 dBm
11 = -2 dBm, -3 dBm
OSC_FREQ [1:0]
Reference Frequency Selection
00 = 12.6 MHz
01 = 14.4 MHz
10 = 25.2 MHz
11 = 26.0 MHz
OSC_
FREQ
[1:0]
0
1
R2 REGISTER
The R2 register address bits (R2 [1:0]) are “10”.
Table 10. R2 REGISTER
Register
MS
B
23
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
LS
B
7
6
5
4
3
2
Data Field
R2
(Default)
16
1
1
0
0
1
0
0
0
0
1
1
1
1
0
Address
Field
1
0
Submit Documentation Feedback
0
0
0
0
0
0
0
1
1
0
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
OBSOLETE
LMX2505
www.ti.com
SNWS008D – MAY 2004 – REVISED MAY 2004
R3 REGISTER
The R3 register address bits (R3 [2:0]) are “011”. This register is only written to if the SPI_DEF bit is set to 0.
Table 11. R3 REGISTER
Register
MS
B
23
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
LS
B
7
6
5
4
3
Data Field
R3
1
0
0
0
0
1
1
0
1
0
0
0
2
1
0
Address
Field
0
0
0
0
0
0
0
1
1
0
1
1
R4 REGISTER
The R4 register address bits (R4 [3:0]) are “0111”. This register is only written to if the SPI_DEF bit is set to 0.
Table 12. R4 REGISTER
Register
MS
B
23
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
LS
B
7
6
5
4
Data Field
R4
0
0
0
0
0
0
1
1
1
0
1
3
2
1
0
1
1
Address
Field
0
0
0
1
1
0
0
1
0
0
1
R5 REGISTER
The R5 register address bits (R5 [4:0]) are “01111”. This register is only written to if the SPI_DEF bit is set to 0.
Table 13. R5 REGISTER
Register
MS
B
23
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
LS
B
7
6
5
Data Field
R5
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
1
1
Address Field
0
0
0
0
0
0
0
0
0
1
1
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LMX2505
17
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
