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LMX2615-SP
SNAS739D – JUNE 2018 – REVISED MAY 2020
LMX2615-SP Space Grade 40-MHz to 15-GHz Wideband Synthesizer With Phase
Synchronization and JESD204B Support
1 Features
3 Description
•
The LMX2615-SP is a high performance wideband
phase-locked loop (PLL) with integrated voltage
controlled oscillator (VCO) and voltage regulators that
can output any frequency from 40 MHz and 15.2 GHz
without a doubler, which eliminates the need for ½
harmonic filters. The VCO on this device covers an
entire octave so the frequency coverage is complete
down to 40 MHz. The high performance PLL with a
figure of merit of –236 dBc/Hz and high phase
detector frequency can attain very low in-band noise
and integrated jitter.
1
•
•
•
•
•
•
•
•
•
•
•
•
Radiation specifications:
– Single event latch-up >120 MeV-cm2/mg
– Total ionizing dose to 100 krad(Si)
– SMD 5962R1723601VXC
40-MHz to 15.2-GHz output frequency
–110-dBc/Hz phase noise at 100-kHz offset with
15-GHz carrier
45 fs RMS jitter at 8 GHz (100 Hz to 100 MHz)
Programmable output power
PLL key specifications:
– Figure of merit: –236 dBc/Hz
– Normalized 1/f noise: –129 dBc/Hz
– Up to 200-MHz phase detector frequency
Synchronization of output phase across multiple
devices
Support for SYSREF with 9-ps resolution
programmable delay
3.3-V single power supply operation
71 pre-selected pin modes
11 × 11 mm² 64-lead CQFP ceramic package
Operating temperature range: –55°C to +125°C
Supported by PLLatinum™ Simulator design tool
The LMX2615-SP allows users to synchronize the
output of multiple instances of the device. This means
that deterministic phase can be obtained from a
device in any use case including the one with
fractional engine or output divider enabled. It also
adds support for either generating or repeating
SYSREF (compliant to JESD204B standard), making
it an ideal low-noise clock source for high-speed data
converters.
This device is fabricated in Texas Instruments'
advanced BiCMOS process and is available in a 64lead CQFP ceramic package.
Device Information (1)
PART NUMBER
2 Applications
•
•
•
•
Space communications
Space radar systems
Phased array antennas and beam forming
High-speed data converter clocking (supports
JESD204B)
GRADE
PACKAGE
LMX2615-MKT-MS
Mechanical Sample (2)
64-lead CQFP
LMX2615W-MPR
Engineering Model (3)
64-lead CQFP
5962R1723601VXC
Flight Model
64-lead CQFP
(1)
(2)
(3)
For all available packages, see the orderable addendum at
the end of the data sheet.
These units are package only and contain no die; they are
intended for mechanical evaluation only.
These units are not suitable for production or flight use; they
are intended for engineering evaluation only.
Simplified Schematic
External loop filter
Vtune
CPout
OSCinP
OSCin
Buffer
Phase
Detector
OSCin
Douber
Input
signal
Pre-R
Divider
Post-R
Divider
I
RFoutAP
MUX
Charge
Pump
OSCinM
Vcc
RFoutAM
Channel
Divider
RFoutBM
Vcc
MUX
Sigma-Delta
Modulator
CSB)
SCK
SDI
Serial Interface
Control
N Divider
RFoutBP
SYSREF
Synchronization
and Delay
Output
Buffer
MUXout
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMX2615-SP
SNAS739D – JUNE 2018 – REVISED MAY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 12
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
16
17
17
35
36
7.6 Register Maps ......................................................... 37
8
Application and Implementation ........................ 55
8.1 Application Information............................................ 55
8.2 Typical Application .................................................. 59
9 Power Supply Recommendations...................... 61
10 Layout................................................................... 61
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Footprint Example on PCB Layout........................
Radiation Environments .......................................
61
62
63
63
11 Device and Documentation Support ................. 64
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
64
64
64
64
64
12 Mechanical, Packaging, and Orderable
Information ........................................................... 64
12.1 Engineering Samples ........................................... 64
12.2 Package Mechanical Information.......................... 65
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2018) to Revision D
Page
•
Added SMD number and orderable part ................................................................................................................................ 1
•
Deleted LMX2615W-MLS from the Device Information table................................................................................................. 1
•
Deleted sentence "See application section on phase noise due to the charge pump." from PLL Phase Detector and
Charge Pump section ........................................................................................................................................................... 18
•
Changed Typical Application Schematic graphic ................................................................................................................. 59
•
Changed Layout Example graphic ...................................................................................................................................... 62
Changes from Revision B (June 2018) to Revision C
Page
•
Changed device status from Advanced Information to Production Data ............................................................................... 1
•
Changed output power, VCO Calibration time, and harmonics. ........................................................................................... 7
•
Added Typical Performance Characteristics ....................................................................................................................... 12
•
Changed Updated Max Frequencies for higher divides to be based on 11.5 GHz, not 15.2 GHz ..................................... 23
•
Added FS7 Pin description .................................................................................................................................................. 33
•
Added Typical Application .................................................................................................................................................... 59
•
Added more details including capacitor requirements for Vtune pin. ................................................................................... 61
•
Added Layout Example ........................................................................................................................................................ 62
Changes from Revision A (June 2018) to Revision B
Page
•
Changed Typical jitter to 45 fs ............................................................................................................................................... 1
•
Added Max Digital pin and OSCin Voltage............................................................................................................................. 7
•
Changed Typical VCO Gain ................................................................................................................................................... 9
•
Changed readback timing diagram and added tCD. ........................................................................................................... 11
2
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SNAS739D – JUNE 2018 – REVISED MAY 2020
•
Changed VCO Frequency range to 7600 to 15200 MHz .................................................................................................... 16
•
Changed VCO calibration updated to new VCO range of 7600 to 15200 MHz .................................................................. 20
•
Changed Ordering of VCOs in calibration time table .......................................................................................................... 21
•
Added Watchdog feature description ................................................................................................................................... 21
•
Changed RECAL feature description .................................................................................................................................. 22
•
Changed VCO Gain table .................................................................................................................................................... 22
•
Changed Channel divider description and picture ............................................................................................................... 22
•
Changed Channel Divider usage for VCO frequency .......................................................................................................... 22
•
Changed 5 GHz, not 5 MHz ................................................................................................................................................ 23
•
Added information on what to do with unused pins ............................................................................................................. 24
•
Changed Case of Fosc%Fout=0 is now category 2 ............................................................................................................ 27
•
Changed Recommendation for CAL and RECAL_EN ........................................................................................................ 33
•
Changed RECAL_EN to CAL pin ........................................................................................................................................ 33
•
Changed pin mode 17 to not be used. ................................................................................................................................. 33
•
Added 10 ms delay to recommended initial power up sequence and more details on what registers to program.............. 36
•
Added Register Map Table .................................................................................................................................................. 37
Changes from Original (May 2017) to Revision A
Page
•
Changed the //ESD Ratings// table ....................................................................................................................................... 7
•
Changed ambient temperature parameter to case temperature in the //Recommended Operating Conditions// table ......... 7
•
Deleted the junction temperature parameter from the //Recommended Operating Conditions// table .................................. 7
•
Changed the supply voltage minimum value from: 3.15 V to: 3.2 V ...................................................................................... 8
•
Changed the test conditions to the supply current parameter................................................................................................ 8
•
Changed the power on reset current typical value for the RESET=1 test condition from: 270 mA to: 289 mA..................... 8
•
Changed the power on reset current typical value for the POWERDOWN=1 test condition from: 5 mA to: 6 mA................ 8
•
Changed the test conditions and added minimum values to the reference input voltage parameter .................................... 8
•
Added phase detector frequency test conditions ................................................................................................................... 8
•
Changed the text toclarify that output power assumes that load is matched and losses are de-embedded......................... 8
•
Changed VCO phase noise test conditions and typical values.............................................................................................. 9
•
Changed the Assisting the VCO Calibration Speed and the MINIMUM VCO_SEL for Partial Assist tables ....................... 21
•
Added Typical Calibration times for fOSC = fPD = 100 MHz based on VCO_SEL table ........................................................ 21
•
Changed the MASH_SEED considerations in the Phase Adjust section............................................................................. 28
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SNAS739D – JUNE 2018 – REVISED MAY 2020
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5 Pin Configuration and Functions
4
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC
GND
GND
VregVCO
NC
VccVCO
VrefVCO
Vtune
GND
VbiasVARAC
NC
GND
NC
NC
47
FS0
NC
46
4
FS1
RECAL_EN
45
5
CAL
VrefVCO2
44
6
GND
SysRefReq
43
7
VbiasVCO
VbiasVCO2
42
8
GND
VccVCO2
41
9
SYNC
GND
40
10
GND
CSB
39
11
VccDIG
GND
38
12
OSCinP
RFoutAP
37
13
OSCinM
RFoutAM
36
14
VregIN
GND
35
15
FS2
VccBUF
34
16
FS3
NC
33
VccMASH
SCK
SDI
GND
RFoutBM
25
26
27
28
29
MUXout
GND
24
32
GND
23
GND
CPout
22
31
VccCP
21
RFoutBP
FS7
20
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30
FS6
DAP
(Die Attach Pad)
19
3
63
NC
FS5
NC
NC
48
18
2
64
NC
FS4
NC
17
1
NC
HBD Package
64-Pin CQFP
Top View
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SNAS739D – JUNE 2018 – REVISED MAY 2020
Pin Functions
CQFP Package (QFN) Pin Functions
PIN
I/O
TYPE
NC
—
—
No connection. Pin may be grounded or left unconnected.
2
NC
—
—
No connection. Pin may be grounded or left unconnected.
3
FS0
I
—
Parallel pin control. This is the LSB.
4
FS1
I
—
Parallel pin control
5
CAL
I
—
Chip enable. In Pin Mode (not SPI Mode), rising edges presented to this pin activate
the VCO calibration.
6
GND
—
—
Ground
7
VbiasVCO
—
—
VCO bias. Requires connecting 10-µF capacitor to ground. Place close to pin.
8
GND
—
—
Ground
9
SYNC
I
—
Phase synchronization input pin.
10
GND
—
—
Ground
11
VccDIG
—
—
Digital supply. Recommend connecting 0.1-µF capacitor to ground.
12
OSCinP
I
—
Complimentary Reference input clock pins. High input impedance. Requires connecting
series capacitor (0.1 µF recommended).
13
OSCinM
I
—
Complimentary pin to OSCinP.
14
VregIN
—
—
Input reference path regulator decoupling. Requires connecting 1-µF capacitor to
ground. Place close to pin.
15
FS2
I
—
Parallel pin control
16
FS3
I
—
Parallel pin control
17
FS4
I
—
Parallel pin control
18
FS5
I
—
Parallel pin control
19
FS6
I
—
Parallel pin control
20
FS7
I
—
Parallel pin control. This is the MSB. Controls output state in pin mode. When this pin
is low, only RFoutA is active, otherwise both outputs are active.
21
VccCP
—
—
Charge pump supply. Recommend connecting 0.1-µF capacitor to ground.
22
CPout
O
—
Charge pump output. Recommend connecting C1 of loop filter close to charge pump
pin.
23
GND
—
Ground
Ground
24
GND
—
Ground
Ground
25
VccMASH
—
—
Digital supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
26
SCK
I
—
SPI input clock. High impedance CMOS input. 1.8 – 3.3V logic.
27
SDI
I
—
SPI input data. High impedance CMOS input. 1.8 – 3.3V logic.
28
GND
—
Ground
29
RFoutBM
O
—
Complementary pin for RFoutBP
30
RFoutBP
O
—
Differential output B Pair. Requires connecting a 50-Ω resistor pullup to VCC as close
as possible to pin. Can be used as a synthesizer output or SYSREF output.
31
GND
—
Ground
32
MUXout
O
—
Multiplexed output pin. Can output: lock detect, SPI readback and diagnostics.
33
NC
—
—
No connection. Leave Unconnected.
34
VccBUF
—
—
Output buffer supply. Requires connecting 0.1-µF capacitor to ground.
35
GND
—
Ground
36
RFoutAM
O
—
Complementary pin for RFoutAP
37
RFoutAP
O
—
Differential output B Pair. Requires connecting a 50-Ω resistor pullup to VCC as close
as possible to pin.
38
GND
—
Ground
39
CSB
I
—
40
GND
—
Ground
NO.
1
NAME
DESCRIPTION
Ground
Ground
Ground
Ground
SPI chip select bar. High impedance CMOS input. 1.8 – 3.3-V logic.
Ground
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CQFP Package (QFN) Pin Functions (continued)
PIN
NO.
NAME
I/O
TYPE
DESCRIPTION
41
VccVCO2
—
—
VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
42
VbiasVCO2
—
—
VCO bias. Requires connecting 1-µF capacitor to ground.
43
SysRefReq
I
—
SYSREF request input for JESD204B support.
44
VrefVCO2
—
—
VCO supply reference. Requires connecting 10-µF capacitor to ground.
45
RECAL_EN
I
—
Enables the automatic recalibration feature.
46
NC
—
—
No connection. Pin may be grounded or left unconnected.
47
NC
—
—
No connection. Pin may be grounded or left unconnected.
48
NC
—
—
No connection. Pin may be grounded or left unconnected.
49
NC
—
—
No connection. Pin may be grounded or left unconnected.
50
NC
—
—
No connection. Pin may be grounded or left unconnected.
51
GND
—
Ground
52
NC
—
—
No connection. Pin may be grounded or left unconnected.
53
VbiasVARAC
—
—
VCO Varactor bias. Requires connecting 10-µF capacitor to ground.
54
GND
—
Ground
55
Vtune
I
—
VCO tuning voltage input.
56
VrefVCO
—
—
VCO supply reference. Requires connecting 10-µF capacitor to ground.
57
VccVCO
—
—
VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
58
NC
—
—
No connection. Leave Unconnected.
59
VregVCO
—
—
VCO regulator node. Requires connecting 1-µF capacitor to ground.
60
GND
—
Ground
Ground
61
GND
—
Ground
Ground
62
NC
—
—
No connection. Pin may be grounded or left unconnected.
63
NC
—
—
No connection. Pin may be grounded or left unconnected.
64
NC
—
—
No connection. Pin may be grounded or left unconnected.
6
Ground
Ground
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SNAS739D – JUNE 2018 – REVISED MAY 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VCC
Power supply voltage (1)
–0.3
3.6
VDIG
Digital pin voltage (FS0-FS7, SYNC, SysRefReq, RECAL_EN, CAL)
−0.3
VCC+0.3
|VOSCin|
Differential AC voltage between OSCinP and OSCinN
TJ
Junction temperature
Tstg
Storage temperature
(1)
UNIT
V
V
2.1
VPP
–55
150
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±1000
V
JEDEC document JEP155 states that 500 V HBM allows safemanufacturing with a standard ESD control process. Manufacturing with
less than 500 V HBM ispossible with the necessary precautions. Pins listed as ±XXX V may actually have higherperformance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Power supply voltage
3.2
3.3
3.45
V
TC
Case temperature
–55
25
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
CQFP
64 PINS
UNIT
22.7
°C/W
7.3
°C/W
Junction-to-board thermal resistance
7.6
°C/W
ψJT
Junction-to-top characterization parameter
2.2
°C/W
ψJB
Junction-to-board characterization parameter
7.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
(2)
(2)
For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
DAP
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6.5 Electrical Characteristics
3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TC ≤ +125°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.2
3.3
3.45
V
POWER SUPPLY
VCC
Supply voltage
Supply current
OUTA_PD = 0, OUTB_PD = 1
OUTA_MUX = OUTB_MUX = 1
OUTA_PWR = 31, CPG = 7
fOSC = fPD = 100 MHz, fVCO = fOUT = 14.5 GHz
360
Power on reset current
RESET = 1
289
Power down current
POWERDOWN = 1
ICC
mA
6
OUTPUT CHARACTERISTICS
Single-ended output power (1) (2)
pOUT
50-Ω resistor pullup
OUTx_PWR = 31
fOUT = 8 GHz
6
fOUT = 15 GHz
4
dBm
INPUT SIGNAL PATH
fOSCin
Reference input frequency
vOSCin
Reference input voltage
OSC_2X = 0
5
1000
OSC_2X = 1
5
200
fOSCin ≥ 20 MHz
0.4
2
10 MHz ≤ fOSCin < 20 MHz
0.8
2
5 MHz ≤ fOSCin < 10 MHz
1.6
2
MASH_ORDER = 0
0.125
250
MASH_ORDER > 0
5
200
Single-ended AC coupled
sine wave input with
complementary side AC
coupled to ground with 50 Ω
resistor
MHz
VPP
PHASE DETECTOR AND CHARGE PUMP
Phase detector frequency (3)
fPD
Charge-pump leakage current
Effective charge pump current. This
is the sum of the up and down
currents
ICPout
CPG = 0
15
CPG = 4
3
CPG = 1
6
CPG = 5
9
CPG = 3
12
CPG = 7
PNPLL_1/f
Normalized PLL 1/f noise
PNPLL_FOM
Normalized PLL noise floor
(1)
(2)
(3)
(4)
8
fPD = 100 MHz, fVCO = 12 GHz (4)
MHz
nA
mA
15
–129
dBc/Hz
–236
dBc/Hz
Single ended output power obtained after de-embeddingmicrostrip trace losses and matching with a manual tuner. Unused port
terminated to 50-Ωload.
Output power, spurs, and harmonics can vary based on boardlayout and components.
For lower VCO frequencies, the N divider minimum value canlimit the phase-detector frequency.
The PLL noise contribution is measured using a clean referenceand a wide loop bandwidth and is composed into flicker and flat
components. PLL_flat = PLL_FOM + 20× log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_1/f + 20 × log(Fvco / 1GHz) –
10× log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculatedas PLL_Noise = 10 × log(10
PLL_Flat / 10
+ 10 PLL_flicker /10 )
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SNAS739D – JUNE 2018 – REVISED MAY 2020
Electrical Characteristics (continued)
3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TC ≤ +125°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
15200
MHz
VCO CHARACTERISTICS
fVCO
VCO frequency
7600
VCO1
fVCO = 8.1 GHz
VCO2
fVCO = 9.3 GHz
VCO3
fVCO = 10.4 GHz
PNVCO
VCO phase noise
VCO4
fVCO = 11.4 GHz
VCO5
fVCO = 12.5 GHz
VCO6
fVCO = 13.6 GHz
VCO7
fVCO = 14.7 GHz
tVCOCAL
KVCO
VCO calibration time, switch across
the entire frequency band, fOSC =
100 MHz, fPD = 100 MHz, fVCO = 7.9
GHz, VCO_SEL = 7
VCO Gain
100 kHz
−105
1 MHz
−127
10 MHz
−148
100 MHz
−155
100 kHz
−103
1 MHz
−125
10 MHz
−146
100 MHz
−153
100 kHz
−103
1 MHz
−125
10 MHz
−147
100 MHz
−158
100 kHz
−101
1 MHz
−124
10 MHz
−146
100 MHz
−158
100 kHz
−102
1 MHz
−126
10 MHz
−147
100 MHz
−156
100 kHz
−101
1 MHz
−124
10 MHz
−146
100 MHz
−160
100 kHz
−101
1 MHz
−124
10 MHz
−146
100 MHz
−157
Partial assist
dBc/Hz
650
8.1 GHz
94
9.3 GHz
106
10.4 GHz
122
11.4 GHz
148
12.5 GHz
185
13.6 GHz
202
14.7 GHz
233
|ΔTCL|
Allowable temperature drift when
VCO is not re-calibrated
H2
VCO second harmonic
fVCO = 8 GHz, divider disabled
–30
H3
VCO third harmonic
fVCO = 8 GHz, divider disabled
−25
µs
MHz/V
125
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dBc
9
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Electrical Characteristics (continued)
3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TC ≤ +125°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INTERFACE (Applies to SCK, SDI, CSB, CAL, RECAL_EN, MUXout, SYNC, SysRefReq)
VIH
High-level input voltage
VIL
Low-level input voltage
1.6
IIH
High-level input current
IIL
Low-level input current
VOH
High-level output voltage
VOL
Low-level output voltage
Load current = –5 mA
MUXout pin
V
0.4
V
–100
100
µA
–100
100
µA
VCC – 0.6
V
Load current = 5 mA
0.6
V
6.6 Timing Requirements
(3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TA ≤ +125°C, except as specified. Nominal values are at VCC = 3.3 V, TA = 25°C)
MIN
NOM
MAX
UNIT
2
MHz
DIGITAL INTERFACE WRITE SPECIFICATIONS
fSPIWrite
SPI write speed
tCE
Clock to enable low time
50
ns
tCS
Data to clock setup time
50
ns
tCH
Data to clock hold time
50
ns
tCWH
Clock pulse width high
200
ns
tCWL
Clock pulse width low
200
ns
tCES
Enable to clock setup time
100
ns
tEWH
Enable pulse width high
100
ns
See Figure 1
DIGITAL INTERFACE READBACK SPECIFICATIONS
fSPIReadback
SPI readback speed
tCE
Clock to enable low time
50
2
ns
tCS
Clock to data wait time
50
ns
tCWH
Clock pulse width high
200
ns
tCWL
Clock pulse width low
200
ns
tCES
Enable to clock setup time
50
ns
tEWH
Enable pulse width high
100
ns
tCD
Falling clock edge to data wait time
200
ns
See Figure 2
MSB
SDI
MHz
LSB
R/W
A5
A0
D15
D14
D0
SDK
tCES
tCS
tCH
tCWH
tCE
tCWL
CSB
tEWH
Figure 1. Serial Data Input Timing Diagram
There are several other considerations for writing on the SPI:
• The R/W bit must be set to 0.
• The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.
• The CSB must be held low for data to be clocked. Device will ignore clock pulses if CSB is held high.
• The CSB transition from high to low must occur when SCK is low.
• When SCK and SDI lines are shared between devices, TI recommends hold the CSB line high on the device
that is not to be clocked.
10
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LSB
tCD
A6
A5
A0
tCWL
R/W
tCWH
MSB
SDI
RB14
RB0
tCD
RB15
MUXout
tCES
tCS
SCK
tCE
CSB
tEWH
Figure 2. Serial Data Readback Timing Diagram
There are several other considerations for SPI readback:
• The R/W bit must be set to 1.
• The MUXout pin will always be low for the address portion of the transaction.
• The data on MUXout becomes available momentarily after the falling edge of SCK and therefore should be
read back on the rising edge of SCK.
• The data portion of the transition on the SDI line is always ignored.
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6.7 Typical Characteristics
-60
Phase Noise (dBc/Hz)
-80
-80
-90
-100
-110
-120
-130
-90
-100
-110
-120
-130
-140
-140
-150
-150
8.1 GHz
4.9 dBm
-160
100 Hz
1 kHz
10 kHz
fOSC = 100 MHz
fPD = 200 MHz
100 kHz 1 MHz
Offset (Hz)
100 Hz -88.8 dBc/Hz 1 MHz -121.9 dBc/Hz
1 kHz -95.1 dBc/Hz 10 MHz -146.0 dBc/Hz
10 kHz -104.9 dBc/Hz 20 MHz -150.9 dBc/Hz
100 kHz -111.4 dBc/Hz 95 MHz -154.0 dBc/Hz
-70
Phase Noise (dBc/Hz)
-70
-60
100 Hz -90.0 dBc/Hz 1 MHz -123.5 dBc/Hz
1 kHz -96.5 dBc/Hz 10 MHz -147.6 dBc/Hz
10 kHz -106.8 dBc/Hz 20 MHz -151.9 dBc/Hz
100 kHz -113.6 dBc/Hz 95 MHz -154.1 dBc/Hz
9.3 GHz
3.6 dBm
-160
100 Hz
1 kHz
10 kHz
10 MHz 100 MHz
tc_P
Jitter = 53.0 fs (100 Hz – 100 MHz)
fOSC = 100 MHz
100 kHz 1 MHz
Offset (Hz)
10 MHz 100 MHz
tc_P
Jitter = 56.7 fs (100 Hz – 100
MHz)
fPD = 200 MHz
Figure 3. Closed-Loop Phase Noise at 8.1 GHz
Figure 4. Closed-Loop Phase Noise at 9.3 GHz
-60
Phase Noise (dBc/Hz)
-80
100 Hz -87.7 dBc/Hz 1 MHz -120.8 dBc/Hz
1 kHz -94.2 dBc/Hz 10 MHz -145.1 dBc/Hz
10 kHz -103.3 dBc/Hz 20 MHz -146.0 dBc/Hz
100 kHz -110.4 dBc/Hz 95 MHz -154.8 dBc/Hz
-80
-90
-100
-110
-120
-130
-140
-90
-100
-110
-120
-130
-140
-150
10.4 GHz
-160
100 Hz
1 kHz
fOSC = 100 MHz
fPD = 200 MHz
-150
4.9 dBm
10 kHz
100 kHz 1 MHz
Offset (Hz)
10 MHz 100 MHz
10.4 GHz
-160
100 Hz
1 kHz
tc_P
Jitter = 57.6 fs (100 Hz – 100 MHz)
Figure 5. Closed-Loop Phase Noise at 10.4 GHz
12
100 Hz -86.9 dBc/Hz 1 MHz -119.7 dBc/Hz
1 kHz -93.2 dBc/Hz 10 MHz -144.4 dBc/Hz
10 kHz -102.8 dBc/Hz 20 MHz -149.9 dBc/Hz
100 kHz -109.7 dBc/Hz 95 MHz -157.0 dBc/Hz
-70
Phase Noise (dBc/Hz)
-70
-60
fOSC = 100 MHz
fPD = 200 MHz
2.1 dBm
10 kHz
100 kHz 1 MHz
Offset (Hz)
10 MHz 100 MHz
grap
tc_P
Jitter = 57.8 fs (100 Hz – 100 MHz)
Figure 6. Closed-Loop Phase Noise at 11.4 GHz
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Typical Characteristics (continued)
-60
Phase Noise (dBc/Hz)
-80
-80
-90
-100
-110
-120
-130
-140
-90
-100
-110
-120
-130
-140
-150
12.5 GHz
-160
100 Hz
1 kHz
-150
0.0 dBm
10 kHz
fOSC = 100 MHz
fPD = 200 MHz
100 kHz 1 MHz
Offset (Hz)
13.6 GHz
-160
100 Hz
1 kHz
10 MHz 100 MHz
Jitter = 62.4 fs (100 Hz – 100 MHz)
100 kHz 1 MHz
Offset (Hz)
10 MHz 100 MHz
tc_P
fOUT = 14 GHz/2 = 3.5 GHz
Jitter = 64.2 fs (100 Hz – 100 MHz)
Figure 8. Closed-Loop Phase Noise at 13.6 GHz
-90
100 Hz -84.9 dBc/Hz 1 MHz -114.3 dBc/Hz
1 kHz -91.6 dBc/Hz 10 MHz -140.4 dBc/Hz
10 kHz -100.8 dBc/Hz 20 MHz -146.7 dBc/Hz
100 kHz -107.2 dBc/Hz 95 MHz -154.2 dBc/Hz
-80
Measurement
Flicker Noise
Flat Noise
Modeled Phase Noise
-95
Phase Noise (dBc/Hz)
-70
-90
-100
-110
-120
-130
-100
-105
-110
-115
-120
-125
-140
-150
14.7 GHz
-160
100 Hz
1 kHz
-130
-3.6 dBm
10 kHz
fOSC = 100 MHz
fPD = 200 MHz
100 kHz 1 MHz
Offset (Hz)
-135
100 Hz
10 MHz 100 MHz
Jitter = 65.5 fs (100 Hz – 100 MHz)
8
fVCO = 10 GHz
FOM = –237.5
CHANGE in Phase Noise (dBc/Hz)
5
4
3
2
1
0
300
400
500
Slew Rate (v/Ps)
600
fOSC = 200 MHz
700
100 kHz
1 MHz
tc_P
fPD = 200 MHz
Flicker = –130.5
Figure 10. Calculation of PLL Noise Metrics
6
200
10 kHz
Offset (Hz)
7.5
Flicker Degrade
FOM Degrade
7
1 kHz
tc_P
Figure 9. Closed-Loop Phase Noise at 14.7 GHz
DEGRADATION in PLL Noise Metric (dB)
10 kHz
fOSC = 100 MHz
fPD = 200 MHz
fVCO = 14 GHz
-60
-1
100
-1.2 dBm
tc_P
Figure 7. Closed-Loop Phase Noise at 12.5 GHz
Phase Noise (dBc/Hz)
100 Hz -85.5 dBc/Hz 1 MHz -115.4 dBc/Hz
1 kHz -92.3 dBc/Hz 10 MHz -141.6 dBc/Hz
10 kHz -100.9 dBc/Hz 20 MHz -147.7 dBc/Hz
100 kHz -108.0 dBc/Hz 95 MHz -154.3 dBc/Hz
-70
Phase Noise (dBc/Hz)
-70
-60
100 Hz -86.5 dBc/Hz 1 MHz -115.9 dBc/Hz
1 kHz -93.2 dBc/Hz 10 MHz -142.6 dBc/Hz
10 kHz -102.4 dBc/Hz 20 MHz -148.7 dBc/Hz
100 kHz -109.3 dBc/Hz 95 MHz -155.2 dBc/Hz
800
4.5
3
1.5
0
-1.5
-3
-4.5
-6
-7.5
10 kHz
tc_P
fVCO = 14.8 GHz
Figure 11. PLL Phase Noise Metrics vs. Fosc Slew Rate
Ta=-55C
Ta=25C
Ta=85C
Ta=125C
6
100 kHz
1 MHz
Offset (Hz)
fVCO = 10 GHz, Narrow Loop
Bandwidth ( 12500
33
2
≤ 10000
30
1
10000 – 12500
34
2
>12250
38
3
≤ 4000 (SYNC Mode)
31
1
4000-7500 (SYNC Mode)
31
2
7500 – 10000
32
2
>10000
36
3
1
2
3
4
≤ 4000 (SYNC Mode)
33
1
4000-7500 (SYNC Mode)
37
2
7500 – 10000
41
3
>10000
45
4
≤ 4000 (SYNC Mode)
45
3
4000-7500 (SYNC Mode)
49
4
7500 – 10000
53
5
>10000
57
6
7.3.6 MUXout Pin
The MUXout pin can be configured as lock detect indicator for the PLL or as an serial data output (SDO) for the
SPI interface to readback registers. Field MUXOUT_LD_SEL (register R0[2]) configures this output.
Table 3. MUXout Pin Configurations
MUXOUT_LD_SEL
FUNCTION
0
Serial data output for readback
1
Lock detect indicator
When lock detect indicator is selected, there are two types of indicator and they can be selected with the field
LD_TYPE (register R59[0]). The first indicator is called “VCOCal” (LD_TYPE=0) and the second indicator is
called “Vtune and VCOCal” (LD_TYPE=1).
7.3.6.1 Serial Data Output for Readback
In this mode, the MUXout pin become the serial data output of the SPI interface. This output cannot be tri-stated
so no line sharing is possible. Details of this pin operation are described with the serial interface description.
Readback is very useful when a device is used is full assist mode and VCO calibration data are retrieve and
saved for future use. It can also be used to read back the lock detect status using the field
rb_LD_VTUNE(register R110[10:9]).
7.3.6.2 Lock Detect Indicator Set as Type “VCOCal”
In this mode the MUXout pin is will be low when the VCO is being calibrated or the lock detect delay timer is
running, otherwise it will be high. The programmable timer (LD_DLY, register R60[15:0]) adds an additional delay
after the VCO calibration finishes before the lock detect indicator is asserted high. LD_DLY is a 16 bit unsigned
quantity that corresponds to the number of phase detector cycles in absolute delay. For example, a phase
detector frequency of 100 MHz and the LD_DLY=10000 will add a delay of 100 usec before the indicator is
asserted. This indicator will remain in its current state (high or low) until register R0 is programmed with
FCAL_EN=1 with a valid input reference. In other words, if the PLL goes out of lock or the input reference goes
away when the current state is high, then the current state will remain high.
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7.3.6.3 Lock Detect Indicator Set as Type “Vtune and VCOCal”
In this mode the MUXout pin is will be high when the VCO calibration has finished, the lock detect delay timer is
finished running, and the PLL is locked. This indicator may remain in its current state (high or low) if the OSCin
signal is lost. The true status of the indicator will be updated and resume its operation only when a valid input
reference to the OSCin pin is returned. An alternative method to monitor the OSCin of the PLL is recommended.
This indicator is reliable as long as the reference to OSCin is present.
The output of the device can be automatically muted when lock detect indicator “Vtune and VCOCal” is low. This
feature is enabled with the field OUT_MUTE (register R0[9]) asserted.
7.3.7 VCO (Voltage-Controlled Oscillator)
The LMX2615 includes a fully integrated VCO. The VCO takes the voltage from the loop filter and converts this
into a frequency. The VCO frequency is related to the other frequencies as shown in Equation 3:
fVCO = fPD × N divider × N Included Divide
(3)
7.3.7.1 VCO Calibration
To reduce the VCO tuning gain and therefore improve the VCO phase-noise performance, the VCO frequency
range is divided into several different frequency bands. The entire range, 7600 to 15200 MHz, covers an octave
that allows the divider to take care of frequencies below the lower bound. This creates the need for frequency
calibration to determine the correct frequency band given a desired output frequency. The frequency calibration
routine is activated any time that the R0 register is programmed with the FCAL_EN = 1. It is important that a
valid OSCin signal must present before VCO calibration begins.
The VCO also has an internal amplitude calibration algorithm to optimize the phase noise which is also activated
any time the R0 register is programmed.
The optimum internal settings for this are temperature dependent. If the temperature is allowed to drift too much
without being re-calibrated, some minor phase noise degradation could result. The maximum allowable drift for
continuous lock, ΔTCL, is stated in the electrical specifications. For this device, a number of 125°C means the
device never loses lock if the device is operated under recommended operating conditions.
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The LMX2615 allows the user to assist the VCO calibration. In general, there are three kinds of assistance, as
shown in Table 4:
Table 4. Assisting the VCO Calibration Speed
ASSIST
ANCE
LEVEL
DESCRIPTION
No
assist
User does nothing to improve VCO calibration speed.
Partial
assist
Upon every frequency change, before the FCAL_EN bit is
checked, the user provides the initial starting VCO_SEL
Full
assist
The user forces the VCO core (VCO_SEL), amplitude
settings (VCO_DACISET), and frequency band
(VCO_CAPCTRL) and manually sets the value.
VCO_SEL
VCO_SEL_FORCE
VCO_CAPCTRL_FO
RCE
VCO_DACISET_FOR
CE
VCO_CAPCTRL
VCO_DACISET
7
0
Dont Care
Choose by table
0
Don't Care
Choose by
readback
1
Choose by readback
For the no assist method, just set VCO_SEL=7 and this is done. For partial assist, the VCO calibration speed
can be improved by changing the VCO_SEL bit according to the frequency. Note that the frequency is not the
actual VCO core range, but actually favors choosing the VCO. This is not only optimal for VCO calibration speed,
but required for reliable locking.
Table 5. Minimum VCO_SEL for Partial Assist
fVCO
VCO CORE (MIN)
7600 - 8740 MHz
VCO1
8740 - 10000 MHz
VCO2
10000 - 10980 MHz
VCO3
10980 -12100 MHz
VCO4
12100 - 13080 MHz
VCO5
13080 - 14180 MHz
VCO6
14180 - 15200 MHz
VCO7
For fastest calibration time, it is ideal to use the minimum VCO core as recommended in the previous table. The
following table shows typical VCO calibration times for this choice in bold as well as showing how long the
calibration time is increased if a higher than necessary VCO core is chosen. Realize that these calibration times
are specific to these fOSC and fPD conditions specified and at the boundary of two cores, sometimes the
calibration time can be increased.
Table 6. Typical Calibration Times for fOSC = fPD = 100 MHz Based on VCO_SEL
fVCO
VCO_SEL
VCO7
VCO6
VCO5
VCO4
VCO3
VCO2
VCO1
8.1 GHz
650
540
550
440
360
230
110
9.3 GHz
610
530
540
430
320
220
Invalid
10.4 GHz
590
520
530
430
240
11.4 GHz
340
290
280
180
12.5 GHz
270
170
120
13.6 GHz
240
130
14.7 GHz
160
Invalid
Invalid
Invalid
Invalid
Invalid
7.3.7.2 Watchdog Feature
The watchdog feature is used to the scenario when radiation during VCO calibration from causes the VCO
calibration to fail. When this feature is enabled, the watchdog timer will run during VCO calibration. If this timer
runs out before the VCO calibration is finished, then the VCO calibration will be re-started. The WD_DLY word
sets how many times this calibration may be restarted by the watchdog feature.
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7.3.7.3 RECAL Feature
The RECAL feature is used to mitigate the scenario when the VCO is in lock, but then radiation causes it to go
out of lock. When the RECAL_EN pin is high, if the PLL loses lock and stays out of lock for a time specified by
the LD_DLY word, then it will trigger a VCO re-calibration.
7.3.7.4 Determining the VCO Gain
The VCO gain varies between the seven cores and is the lowest at the lowest end of the band and highest at the
highest end of each band. For a more accurate estimation, use Table 7:
Table 7. VCO Gain
f1
f2
Kvco1
Kvco2
7600
8740
78
114
8740
10000
91
125
10000
10980
112
136
10980
12100
136
168
12100
13080
171
206
13080
14180
188
218
14180
15200
218
248
Based in this table, the VCO gain can be estimated for an arbitrary VCO frequency of fVCO as Equation 4:
Kvco = Kvco1 + (Kvco2-Kvco1) × (fVCO – f1) / (f2 – f1)
(4)
7.3.8 Channel Divider
To go below the VCO lower bound of 7600 MHz, the channel divider can be used. The channel divider consists
of four segments, and the total division value is equal to the multiplication of them. Therefore, not all values are
valid.
VCO
1/2
Divide by
2 or 3
Divide by
2 or 4
Divide by
2,4, or 8
MUX
RFoutA
MUX
RFoutB
MUX
Figure 23. Channel Divider
When the channel divider is used, there are limitations on the values. Table 8 shows how these values are
implemented and which segments are used.
22
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Table 8. Channel Divider Segments
EQUIVALENT
DIVISION
VALUE
FREQUENCY
LIMITATION
OutMin (MHz)
OutMax (MHz)
CHDIV[4:0]
SEG0
SEG1
SEG2
SEG3
3800
7600
0
2
1
1
1
1900
3800
1
2
2
1
1
1266.667
2533.333
2
2
3
1
1
2
4
None
6
8
950
1437.5
3
2
2
2
1
12
633.333
958.333
4
2
3
2
1
16
475
718.75
5
2
2
4
1
24
316.667
469.167
6
2
3
4
1
32
237.5
359.375
7
2
2
8
1
158.333
239.583
8
2
3
8
1
64
118.75
179.688
9
2
2
8
2
72
105.556
159.722
10
2
3
6
2
96
79.167
119.792
11
2
3
8
2
128
59.375
89.844
12
2
2
8
4
39.583
59.896
13
2
3
8
4
n/a
n/a
14 - 31
n/a
n/a
n/a
n/a
fVCO ≤ 11.5 GHz
48
192
Invalid
n/a
The channel divider is powered up whenever an output (OUTx_MUX) is selected to the channel divider or
SysRef, regardless of whether it is powered down or not. When an output is not used, TI recommends selecting
the VCO output to ensure that the channel divider is not unnecessarily powered up.
Table 9. Channel Divider
OUTA MUX
OUTB MUX
CHANNEL DIVIDER
Channel Divider
X
Powered up
X
Channel Divider or SYSREF
Powered up
All Other Cases
Powered down
7.3.9 Output Buffer
The RF output buffer type is open collector and requires an external pullup to VCC. This component may be a 50Ω resistor or an inductor. The inductor has less controlled impedance, but higher power. For the inductor case, it
is often helpful to follow this with a resistive pad. The output power can be programmed to various levels or
disabled while still keeping the PLL in lock. If using a resistor, limit OUTx_PWR setting to 31; higher than this
tends to actually reduce power. Note that states 32 through 47 are redundant and should be ignored. In other
words, after state 31, the next higher power setting is 48.
Table 10. OUTx_PWR Recommendations
fOUT
Restrictions
Comments
10 MHz ≤ fOUT ≤ 5 GHz
None
At lower frequencies, the output buffer impedance is high, so the 50-Ω pullup will make
the output impedance look somewhat like 50-Ω. Typically, maximum output power is
near a setting of OUTx_PWR=50.
5 GHz < fOUT ≤ 10 GHz
OUTx_PWR ≤ 31
In this range, parasitic inductances have some impact, so the output setting is
restricted.
10 GHz < fOUT
OUTx_PWR ≤ 20
At these higher frequency ranges, it is best to keep below 20 for highest power and
optimal noise floor.
7.3.10 Powerdown Modes
The LMX2615 can be powered up and down using the CAL Pin or the POWERDOWN bit. When the device
comes out of the powered down state, either by resuming the POWERDOWN bit to zero or by pulling back CAL
Pin HIGH (if it was powered down by CAL Pin), register R0 must be programmed with FCAL_EN high again to
re-calibrate the device.
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7.3.11 Treatment of Unused Pins
This device has several pins for many features and there is a preferred way to treat these pins if not needed. For
the input pins, a series resistor is recommend, but they can be directly shorted.
Table 11. Recommended Treatment of Pins
Pins
SPI Mode
Pin Mode
Recommended Treatment if NOT Used
FS0,FS1,FS2,FS3,F
S4,FS5,FS6,FS7
Never Used Always Used
GND with 1 kΩ.
CAL
Never Used Sometimes
Used
VCC with 1 kΩ
SYNC, SysRefReq
Sometimes
Used
Never Used
GND with 1 kΩ
OSCinP,OSCinM
Always
Used
Always Used
GND with 50 Ω to ground after the AC-coupling capacitor. If one side of complimentary
side is used and other side is not, impedance looking out should be similar for both of
these pins.
SCK, SDI
Always
Used
Never Used
GND with 1 kΩ
CSB
Always
Used
Never Used
VCC with 1 kΩ
RECAL_EN
Sometimes
Used
Sometimes
Used
Internally pulled to VCC with 200 kΩ
RFoutXX
Sometimes
Used
Sometimes
Used
VCC with 50 Ω. If one side of complimentary side is used and the other side is not,
impedance looking out should be similar for both of these pins.
MUXOUT
Sometimes
Used
Sometimes
Used
GND with 10 kΩ
7.3.12 Phase Synchronization
7.3.12.1 General Concept
The SYNC pin allows one to synchronize the LMX2615 such that the delay from the rising edge of the OSCin
signal to the output signal is deterministic. Initially, the devices are locked to the input, but are not synchronized.
The user sends a synchronization pulse that is reclocked to the next rising edge of the OSCin pulse. After a
given time, t1, the phase relationship from OSCin to fOUT will be deterministic. This time is dominated by the sum
of the VCO calibration time, the analog setting time of the PLL loop, and the MASH_RST_CNT if used in
fractional mode.
24
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...
Device 1
SYNC
...
Device 2
...
...
fOSC
t2
t1
Figure 24. Devices Are Now Synchronized to OSCin Signal
When the SYNC feature is enabled, part of the channel divide may be included in the feedback path.
Table 12. IncludedDivide With VCO_PHASE_SYNC = 1
OUTx_MUX
CHANNEL DIVIDER
OUTA_MUX = OUTB_MUX = 1 ("VCO")
All Other Valid Conditions
IncludedDivide
Don't Care
1
Divisible by 3, but NOT 24 or 192
SEG0 × SEG1 = 6
All other values
SEG0 × SEG1 = 4
External loop filter
OSCin
Doubler
Pre-R
Divider
XM
R
Divider
I
Charge
Pump
MUX
RFoutA
MUX
RFoutB
SEG0
SEG2
SEG1
SEG3
N Divider
Figure 25. Phase SYNC Diagram
7.3.12.2 Categories of Applications for SYNC
The requirements for SYNC depend on certain setup conditions. In cases that the SYNC is not timing critical, it
can be done through software by toggling the VCO_PHASE_SYNC bit from 0 to 1. The Figure 26 gives the
different categories. When it is timing critical, then it must be done through the pin and the setup and hold times
for the OSCin pin are critical. For timing critical sync (Category 3) ONLY, adhere to the following guidelines.
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Table 13. SYNC Pin Timing Characteristics for Category 3 SYNC
26
Parameter
Description
fOSC
Input reference Frequency
tSETUP
Setup time between SYNC and OSCin rising edges
2.5
ns
tHOLD
Hold time between SYNC and OSCin rising edges
2.5
ns
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Min
Max
Unit
40
MHz
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NO
, /s G 128
?
YES
CHDIV = 1,2,4,6
This means the channel divider after the
VCO is either bypassed,2,4, or 6. In this
case, SYNC mode will put it in the loop.
NO
CHDIV = 1,2,4,6
?
NO
Category 4
Device can NOT be reliably
used in SYNC mode
YES
YES
OSC_2X=0
?
fOUT and fOSC related by integer multiple?
NO
This means that the output (fOUT) and
input frequencies (fOSC) are related.
In other words:
(fOUT % fOSC=0) OR (fOSC % fOUT=0)
NO
fOSC G 50 MHz
?
YES
NO
fOUT%(2| (OSC)=0
YES
Category 3
x SYNC Required
x SYNC Timing Critical
x Limitations on fOSC
NO
CHDIV = 1,2,4, 6
?
Category 2
x SYNC Required
x SYNC Timing NOT critical
x No limitations on fOSC
Integer Mode
This is asking if the device is
in integer mode, which
would mean the fractional
numerator is zero.
YES
CHDIV = 1,2,4,6
This means the channel
divider after the VCO is either
bypassed,2,4, or 6. In this
case, SYNC mode will put it in
the loop.
YES
fOUT and fOSC
related by integer
multiple
?
YES
NO
CHDIV=1?
Integer Mode
?
NO
Category 1
x SYNC Mode Required
x No Software/Pin SYNC Pulse required
Category 1
x SYNC Mode Not required at all
x No limitations on fOSC
Figure 26. Determining the SYNC Category
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7.3.12.3 Procedure for Using SYNC
This procedure must be used to put the device in SYNC mode.
1. Use the flowchart to determine the SYNC category.
2. Make determinations for OSCin and using SYNC based on the category
1. If Category 4, SYNC cannot be performed in this setup.
2. If category 3, ensure that the maximum fOSC frequency for SYNC is not violated and there are hardware
accommodations to use the SYNC pin.
3. If the channel divide is used, determine the included channel divide value which will be 2 × SEG1 of the
channel divide:
1. If OUTA_MUX is not channel divider and OUTB_MUX is not channel divider or SysRef, then
IncludedDivide = 1.
2. Otherwise, IncludedDivide = 2 × SEG1. In the case that the channel divider is 2, then IncludedDivide=4.
4. If not done already, divide the N divider and fractional values by the included channel divide to account for
the included channel divide.
5. Program the device with the VCO_PHASE_SYNC = 1. Note that this does not count as applying a SYNC to
device (for category 2).
6. Apply the SYNC, if required
1. If category 2, VCO_PHASE_SYNC can be toggled from 0 to 1. Alternatively, a rising edge can be sent to
the SYNC pin and the timing of this is not critical.
2. If category 3, the SYNC pin must be used, and the timing must be away from the rising edge of the
OSCin signal.
7.3.12.4 SYNC Input Pin
The SYNC input pin can be driven either in CMOS. However, if not using SYNC mode (VCO_PHASE_SYNC =
0), then the INPIN_IGNORE bit must be set to one, otherwise it causes issues with lock detect. If the pin is
desired for to be used and VCO_PHASE_SYNC=1, then set INPIN_IGNORE = 0.
7.3.13 Phase Adjust
The MASH_SEED word can use the sigma-delta modulator to shift output signal phase with respect to the input
reference. If a SYNC pulse is sent (software or pin) or the MASH is reset with MASH_RST_N, then this phase
shift is from the initial phase of zero. If the MASH_SEED word is written to, then this phase is added. The phase
shift is calculated as Equation 5.
Phase shift in degrees = 360 × ( MASH_SEED / PLL_DEN) × ( IncludedDivide/CHDIV )
(5)
Example:
Mash seed = 1
Denominator = 12
Channel divider = 16
Phase shift ( VCO_PHASE_SYNC=0) = 360 × (1/12) × (1/16) = 1.875 degrees
Phase Shift (VCO_PHASE_SYNC=1) = 360 × (1/12) × (4/16) = 7.5 degrees
There are several considerations when using MASH_SEED
• Phase shift can be done with a FRAC_NUM=0, but MASH_ORDER must be greater than zero. For
MASH_ORDER=1, the phase shifting only occurs when MASH_SEED is a multiple of PLL_DEN.
• For the 2nd order modulator, PLL_N≥45, for the 3rd order modulator, PLL_N≥49, and for the fourth order
modulator, PLL_N≥54.
When using MASH_SEED in the case where IncludedDivide>1, there are several additional considerations in
order to get the phase shift to be monotonically increasing with MASH_SEED.
• It is recommended to use MASH_ORDER 247
Invalid
Invalid
Invalid
Invalid
Invalid
7.3.15.1 Programmable Fields
Table 16 has the programmable fields for the SYSREF functionality.
Table 16. SYSREF Programming Fields
FIELD
SYSREF_EN
PROGRAMMING
0 = Disabled
1 = enabled
DEFAULT
0
DESCRIPTION
Enables the SYSREF mode. SYSREF_EN
must be 1 if and only if OUTB_MUX=2
(SysRef)
SYSREF_DIV_PRE
1: DIV1
2: DIV2
4: DIV4
Other states: invalid
SYSREF_REPEAT
0 = Master mode
1 = Repeater mode
0
In master mode, the device creates a series
of SYSREF pulses. In repeater mode,
SYSREF pulses are generated with the
SysRefReq pin.
0 = Continuous mode
1 = Pulsed mode
0
Continuous mode continuously makes
SYSREF pulses, where pulsed mode makes
a series of SYSREF_PULSE_CNT pulses
0 to 15
4
In the case of using pulsed mode, this is the
number of pulses. Setting this to zero is an
allowable, but not practical state.
0: Divide by 4
1: Divide by 6
2: Divide by 8
...
2047: Divide by 4098
0
The SYSREF frequency is at the VCO
frequency divided by this value.
SYSREF_PULSE
SYSREF_PULSE_CNT
SYSREF_DIV
The output of this divider is the
fINTERPOLATOR.
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7.3.15.2 Input and Output Pin Formats
7.3.15.2.1 SYSREF Output Format
The SYSREF output comes in differential format through RFoutB. This will have a minimum voltage of about 2.3
V and a maximum of 3.3 V. If DC coupling cannot be used, there are two strategies for AC coupling.
3.3 V
SysRefOutP
Data
Converter
SysRefOutN
LMX2594
3.3 V
Copyright © 2017, Texas Instruments Incorporated
Figure 28. SYSREF Output
1. Send a series of pulses to establish a DC-bias level across the AC-coupling capacitor.
2. Establish a bias voltage at the data converter that is below the threshold voltage by using a resistive divider.
7.3.15.3 Examples
The SysRef can be used in a repeater mode, which just echos the input, after being re-clocked to the
fINTERPOLATOR frequency and then RFout, or it can be used in a repeater. In repeater mode, it can repeat 1,2,4,8,
or infinite (continuous) pulses. The frequency for repeater mode is equal to the RFout frequency divided by the
SYSREF divider.
OSCinM
OSCinP
SysRefReq
t1
RFoutAM
RFoutAP
RFoutBP
RFoutBM
t2
I
t1
I t2
Figure 29. SYSREF Out In Repeater Mode
In master mode, the SysRefReq pin is pulled high to allow the SysRef output.
OSCinM
OSCinP
SysRefReq
RFoutAM
RFoutAP
RFoutBP
RFoutBM
I
I
Figure 30. Figure 1. SYSREF Out In Pulsed/Continuous Mode
32
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7.3.15.4 SYSREF Procedure
To
1.
2.
3.
use SYSREF, do the these steps:
Put the device in SYNC mode using the procedure already outlined.
Figure out IncludedDivide the same way it is done for SYNC mode.
Calculate the SYSREF_DIV_PRE value such that the interpolator frequency (fINTERPOLATOR) is in the range of
800 to 1500 MHz. fINTERPOLATOR = fVCO/IncludedDivide/SYSREF_DIV_PRE. Make this frequency a multiple of
fOSC if possible.
4. If using master mode (SYSREF_REPEAT = 0), ensure SysRefReq pin is high, ensure the SysRefReq pin is
high.
5. If using repeater mode (SYSREF_REPEAT = 1), set up the pulse count if desired. Pulses are created by
toggling the SysRefReq pin.
6. Adjust the delay between the RFoutA and RFoutB signal using the JESD_DACx_CTL fields.
7.3.16 Pin Modes
The LMX2615-SP has 8 pins that can be used to program pre-selected modes. A few rules of operation for these
pin modes are as follows:
• Set the pin mode as desired. Pin Mode 0 is SPI mode
• If a single frequency is desired, tie CAL should be tied to supply through 1-kΩ resistance and RECAL_EN
should be left open.
• The rise time for the supply needs to be
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