LMZ10500
SNVS723H – OCTOBER 2011 – REVISED OCTOBER 2023
LMZ10500 650-mA Nano Module With 5.5-V Maximum Input Voltage
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Point of load conversions from 3.3-V and 5-V rails
Space constrained applications
Low output noise applications
3 Description
The LMZ10500 nano module is an easy-to-use stepdown DC/DC design capable of driving up to 650-mA
load in space-constrained applications. Only an input
capacitor, an output capacitor, a small VCON filter
capacitor, and two resistors are required for basic
operation. The nano module comes in an 8-pin µSiP
footprint package with an integrated inductor. Internal
current limit based soft-start function, current overload
protection, and thermal shutdown are also provided.
Package Information
PART NUMBER
LMZ10500
(1)
(2)
PACKAGE(1)
PACKAGE SIZE(2)
SIL (µSiP, 8)
3.00 mm × 2.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
100
80
90
70
EN 55022 Class B Limit
60
EN 55022 Class A Limit
Radiated Emissions (dBµV/m)
•
•
•
•
•
80
EFFICIENCY (%)
•
Output current up to 650 mA
2.7-V to 5.5-V input voltage range
0.6-V to 3.6-V output voltage range
Efficiency up to 95%
Integrated Inductor
8-pin microSiP footprint
–40°C to 125°C junction temperature range
Adjustable output voltage
2-MHz fixed PWM switching frequency
Integrated compensation
Soft-start function
Current limit protection
Thermal shutdown protection
Input voltage UVLO for power-up, power-down,
and brownout conditions
Only 5 external components — resistor divider and
3 ceramic capacitors
Small design size
Low output voltage ripple
Easy component selection and simple PCB layout
High efficiency reduces system heat generation
Create a custom design using the LMZ10500 with
the WEBENCH® Power Designer
70
60
50
VOUT=1.2V
VOUT=1.8V
VOUT=2.5V
VOUT=3.3V
40
30
20
0
Typical Efficiency at VIN = 3.6 V
50
40
30
20
10
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
Evaluation Board
C009
0
200
400
600
Frequency (MHz)
800
1000
C001
Radiated EMI (CISPR22) VIN = 5 V, VOUT = 1.8 V, IOUT
= 650 mA
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ10500
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SNVS723H – OCTOBER 2011 – REVISED OCTOBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 System Characteristics............................................... 6
6.7 Typical Characteristics................................................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................11
8 Application and Implementation.................................. 13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
8.3 Power Supply Recommendations.............................19
8.4 Layout....................................................................... 20
9 Device and Documentation Support............................23
9.1 Device Support......................................................... 23
9.2 Documentation Support............................................ 23
9.3 Receiving Notification of Documentation Updates....23
9.4 Support Resources................................................... 23
9.5 Trademarks............................................................... 23
9.6 Electrostatic Discharge Caution................................23
9.7 Glossary....................................................................23
10 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (July 2018) to Revision H (October 2023)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated trademark information........................................................................................................................ 23
Changes from Revision F (February 2015) to Revision G (July 2018)
Page
• editorial rebranding for SEO............................................................................................................................... 1
• Added links for Webench ...................................................................................................................................1
• Move storage temperature spec to Abs Max table ............................................................................................ 4
• Changed "Handling" to "ESD" Ratings .............................................................................................................. 4
• Added Section 9.1 ........................................................................................................................................... 23
• Changed SIL package drawing to SIL0008G .................................................................................................. 24
Changes from Revision E (September 2014) to Revision F (February 2015)
Page
• Switched Figure 8-4 and Figure 8-5 ................................................................................................................ 14
Changes from Revision D (January 2014) to Revision E (September 2014)
Page
• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
2
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5 Pin Configuration and Functions
SIDE VIEW
TOP VIEW
BOTTOM VIEW
1
8
8
VREF
2
7
7
VIN
EN
1
VCON
2
FB
3
SGND
4
PAD
3
6
6
PGND
4
5
5
VOUT
(SGND)
Figure 5-1. SIL Package, 8-Pin µSIP
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE(1)
DESCRIPTION
1
EN
I
Enable input. Set this digital input higher than 1.2 V for normal operation. For shutdown, set low.
Pin is internally pulled up to VIN and can be left floating for always-on operation.
2
VCON
I
Output voltage control pin. Connect to analog voltage from resisitve divider or DAC/controller to set
the VOUT voltage. VOUT = 2.5 × VCON. Connect a small (470 pF) capacitor from this pin to SGND
to provide noise filtering.
3
FB
I
Feedback of the error amplifier. Connect directly to output capacitor to sense VOUT.
4
SGND
I
Ground for analog and control circuitry. Connect to PGND at a single point.
5
VOUT
O
Output Voltage. Connected to one pin of the integrated inductor. Connect output filter capacitor
between VOUT and PGND.
6
PGND
I
Power ground for the power MOSFETs and gate-drive circuitry.
7
VIN
I
Voltage supply input. Connect ceramic capacitor between VIN and PGND as close as possible to
these two pins. Typical capacitor values are between 4.7 µF and 22 µF.
8
VREF
O
2.35 V voltage reference output. Typically connected to VCON pin through a resistive divider to set
the output voltage.
—
PAD
I
The center pad underneath the SIL0008A package is internally tied to SGND. Connect this pad to
the ground plane for improved thermal performance.
(1)
I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
VIN, VREF to SGND
PGND to SGND
MIN
MAX
–0.2
6
UNIT
V
−0.2
0.2
V
EN, FB, VCON
(SGND − 0.2) to (VIN + 0.2)
6
V
VOUT
(PGND − 0.2) to (VIN + 0.2)
6
V
–40
125
°C
260
°C
150
°C
Junction temperature (TJ-MAX)
Maximum lead temperature
Storage temperature, Tstg
(1)
(2)
–65
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Section 6.3 are conditions under which
operation of the device is intended to be functional. For specified specifications and test conditions, see the Section 6.5.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
Recommended load current
Junction temperature (TJ)
MIN
MAX
2.7
5.5
UNIT
V
0
650
mA
–40
125
°C
6.4 Thermal Information
LMZ10500
THERMAL METRIC(1)
SIL (µSIP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
45.8
°C/W
Junction-to-case (top) thermal resistance
25
°C/W
Junction-to-board thermal resistance
9.2
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
9.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
25
°C/W
(1)
4
SIL0008G Package
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 3.6 V, VEN = 1.2 V, TJ = 25°C(1)
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1)
UNIT
SYSTEM PARAMETERS
VREF × GAIN
Reference voltage × VCON to FB VIN = VEN = 5.5 V, VCON = 1.44 V
Gain
5.7575
5.875
5.9925
V
GAIN
VCON to FB Gain
2.4375
2.5
2.575
V/V
VINUVLO
VIN rising threshold
2.24
2.41
2.64
V
VINUVLO HYST
VIN UVLO Hysteresis
120
165
200
mV
ISHDN
Shutdown supply current
VIN = 3.6 V, VEN = 0.5 V(3)
Iq
DC bias current into VIN
VIN = 5.5 V, VCON = 1.6 V, IOUT = 0 A
RDROPOUT
VIN to VOUTresistance
IOUT = 200 mA
I LIM
DC Output Current Limit
VCON = 1.72 V(4)
FOSC
VIH,ENABLE
VIL,ENABLE
Enable logic LOW voltage
TSD
Thermal shutdown
TSD-HYST
Thermal shutdown hysteresis
DMAX
Maximum duty cycle
TON-MIN
Minimum on-time
18
µA
9.5
mA
305
575
mΩ
1000
Internal oscillator frequency
1.75
2
Enable logic HIGH voltage
1.2
θJA
(2)
(3)
(4)
11
6.5
800
Package Thermal Resistance
(1)
VIN = 5.5 V, VCON = 1.44 V
mA
2.25
V
0.5
Rising Threshold
MHz
V
150
°C
20
°C
100%
50
20-mm x 20-mm board
2 layers, 2 oz copper, 0.5W, no airlow
77
15 mm x 15 mm board
2 layers, 2 oz copper, 0.5W, no airlow
88
10 mm x 10 mm board
2 layers, 2 oz copper, 0.5W, no airlow
107
ns
°C/W
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate the Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
Shutdown current includes leakage current of the high side PFET.
Current limit is built-in, fixed, and not adjustable.
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6.6 System Characteristics
The following specifications are specified by design providing the component values in Figure 8-1 are used (CIN = COUT = 10
µF, 6.3 V, 0603, TDK C1608X5R0J106K). These parameters are not specified by production testing. Unless otherwise stated
the following conditions apply: TA = 25°C.
PARAMETER
MIN
TYP
Output Voltage Regulation
Over Line Voltage and Load
Current
VOUT = 0.6 V
ΔVIN =2.7 V to 4.2 V
ΔIOUT = 0 A to 650 mA
±1.23%
ΔVOUT/VOUT
Output Voltage Regulation
Over Line Voltage and Load
Current
VOUT = 1.5 V
ΔVIN = 2.7 V to 5.5 V
ΔIOUT = 0 A to 650 mA
±0.56%
ΔVOUT/VOUT
Output Voltage Regulation
Over Line Voltage and Load
Current
VOUT = 3.6 V
ΔVIN = 4.0 V to 5.5 V
ΔIOUT = 0 A to 650 mA
±0.24%
VREF TRISE
Rise time of reference voltage
EN = Low to High, VIN = 4.2 V
VOUT = 2.7 V, IOUT = 650 mA
10
MAX
UNIT
µs
VIN = 5.0 V, VOUT = 3.3 V
IOUT = 200 mA
95%
Full Load Efficiency
VIN = 5.0 V, VOUT = 3.6 V
IOUT = 650 mA
93%
VOUT Ripple
Output voltage ripple
VIN = 5.0 V, VOUT = 1.8 V
IOUT = 650 mA (1)
8
mV pkpk
Line Transient
Line transient response
VIN = 2.7 V to 5.5 V,
TR = TF= 10 µs,
VOUT = 1.8 V, IOUT = 650 mA
25
mV pkpk
Load Transient
Load transient response
VIN = 5.0 V
TR = TF = 40 µs,
VOUT = 1.8 V
IOUT = 65 mA to 650 mA
25
mV pkpk
Peak Efficiency
η
(1)
6
TEST CONDITIONS
ΔVOUT/VOUT
Ripple voltage must be measured across COUT on a well-designed PC board using the suggested capacitors.
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6.7 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 3.6 V, TA = 25°C
0.30
DROPOUT VOLTAGE (V)
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
10mV/Div
0.25
0.20
0.15
0.10
VIN=2.7V
VIN=3V
VIN=3.3V
VIN=3.6V
0.05
0.00
250MHz BW
0
1µs/Div
0.7
0.7
0.6
0.6
0.5
0.4
0.3
0.2
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
0.1
0.0
60
70
0.4
0.3
0.2
90
100
110
120
130
60
0.6
OUTPUT CURRENT (A)
0.6
0.4
0.3
0.2
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
60
70
100
110
120
130
120
130
C002
0.3
0.2
VIN=4V
VIN=4.5V
VIN=5V
VIN=5.5V
60
70
80
90
100
110
120
130
AMBIENT TEMPERATURE (ƒC)
C003
Figure 6-5. Thermal Derating VOUT = 2.5 V, θJA = 77°C/W
110
0.4
0.0
90
AMBIENT TEMPERATURE (ƒC)
100
0.5
0.1
80
90
Figure 6-4. Thermal Derating VOUT = 1.8 V, θJA = 77°C/W
0.7
0.5
80
AMBIENT TEMPERATURE (ƒC)
0.7
0.0
70
C001
Figure 6-3. Thermal Derating VOUT = 1.2 V, θJA = 77°C/W
0.1
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
0.0
80
C010
0.5
0.1
AMBIENT TEMPREATURE (ƒC)
OUTPUT CURRENT (A)
LOAD CURRENT (A)
Figure 6-2. Dropout Voltage vs Load Current and Input Voltage
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 6-1. Output Voltage Ripple VIN = 5 V, VOUT = 1.8 V, IOUT =
650 mA
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
C004
Figure 6-6. Thermal Derating VOUT = 3.3 V, RθJA = 77°C/W
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6.7 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 3.6 V, TA = 25°C
100
Evaluation Board
70
EN 55022 Class B Limit
60
EN 55022 Class A Limit
50
40
30
20
10
Peak Emissions
Quasi Peak Limit
Average Limit
90
Radiated Emissions (dBµV/m)
Radiated Emissions (dBµV/m)
80
80
70
60
50
40
30
20
10
0
0
0
200
400
600
800
Frequency (MHz)
VIN = 5 V
1000
0.1
1
VOUT = 1.8 V
IOUT = 650 mA
Figure 6-7. Radiated EMI (CISPR22) Default Evaluation Board
BOM
10
Frequency (MHz)
C001
VIN = 5 V
VOUT = 1.8 V
100
C001
IOUT = 650 mA
Figure 6-8. Conducted EMI Default Evaluation Board BOM With
Additional 2.2µh 1µf LC Input Filter
VCON
500 mV/Div
200 mA/Div
IL
200 mA/Div
IOUT
500 mV/Div
VOUT
10 µs/Div
Figure 6-9. Startup
8
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7 Detailed Description
7.1 Overview
The LMZ10500 nano module is an easy-to-use step-down DC/DC solution capable of driving up to 650 mA load
in space-constrained applications. Only an input capacitor, an output capacitor, a small VCON filter capacitor,
and two resistors are required for basic operation. The nano module comes in 8-pin LLP footprint package with
an integrated inductor. The LMZ10500 operates in fixed 2-MHz PWM (Pulse Width Modulation) mode, and is
designed to deliver power at maximum efficiency. The output voltage is typically set by using a resistive divider
between the built-in reference voltage VREF and the control pin VCON. The VCON pin is the positive input to the
error amplifier. The output voltage of the LMZ10500 can also be dynamically adjusted between 0.6 V and 3.6 V
by driving the VCON pin externally. Internal current limit based soft-start function, current overload protection, and
thermal shutdown are also provided.
7.2 Functional Block Diagram
VREF
VIN
UVLO
REFERENCE
VOLTAGE
VCON
ERROR
AMPLIFIER
FB
COMP
CURRENT
COMP
CURRENT SENSE
L
VOUT
MOSFET
CONTROL
LOGIC
Integrated
Inductor
VIN
UVLO
EN
MAIN CONTROL
TSD
OSCILLATOR
SGND
PGND
7.3 Feature Description
7.3.1 Current Limit
The LMZ10500 current limit feature protects the module during an overload condition. The circuit employs
positive peak current limit in the PFET and negative peak current limit in the NFET switch. The positive peak
current through the PFET is limited to 1.2 A (typical). When the current reaches this limit threshold the PFET
switch is immediately turned off until the next switching cycle. This behavior continues on a cycle-by-cycle basis
until the overload condition is removed from the output. The typical negative peak current limit through the NFET
switch is –0.6A (typical).
The ripple of the inductor current depends on the input and output voltages. This means that the DC level of the
output current when the peak current limiting occurs will also vary over the line voltage and the output voltage
level. Refer to the DC Output Current Limit plots in the Section 6.7 section for more information.
7.3.2 Start-up Behavior and Soft Start
The LMZ10500 features a current limit based soft-start circuit to prevent large in-rush current and output
overshoot as VOUT is ramping up. This is achieved by gradually increasing the PFET current limit threshold
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to the final operating value as the output voltage ramps during startup. The maximum allowed current in the
inductor is stepped up in a staircase profile for a fixed number of switching periods in each step. Additionally, the
switching frequency in the first step is set at 450 kHz and is then increased for each of the following steps until
it reaches 2MHz at the final step of current limiting. This current limiting behavior is illustrated in Figure 7-1 and
allows for a smooth VOUT ramp up.
VCON
500 mV/Div
200 mA/Div
IL
200 mA/Div
500 mV/Div
IOUT
VOUT
10 µs/Div
Figure 7-1. Start-Up Behavior of Current Limit Based Soft Start
The soft start rate is also limited by the VCON ramp up rate. The VCON pin is discharged internally through a pull
down device before startup occurs. This is done to deplete any residual charge on the VCON filter capacitor and
allow the VCON voltage to ramp up from 0V when the part is started. The events that cause VCON discharge are
thermal shutdown, UVLO, EN low, or output short circuit detection. The minimum recommended capacitance on
VCON is 220 pF and the maximum is 1 nF. The duration of startup current limiting sequence takes approximately
75 µs. After the sequence is completed, the feedback voltage is monitored for output short circuit events.
7.3.3 Output Short Circuit Protection
In addition to cycle by cycle current limit, the LMZ10500 features a second level of short circuit protection. If the
load pulls the output voltage down and the feedback voltage falls to 0.375 V, the output short circuit protection
will engage. In this mode the internal PFET switch is turned OFF after the current limit comparator trips and
the beginning of the next cycle is inhibited for approximately 230 µs. This forces the inductor current to ramp
down and limits excessive current draw from the input supply when the output of the regulator is shorted. The
synchronous rectifier is always OFF in this mode. After 230 µs of non-switching a new startup sequence is
initiated. During this new startup sequence the current limit is gradually stepped up to the nominal value as
illustrated in the Section 7.3.2 section. After the startup sequence is completed again, the feedback voltage is
monitored for output short circuit. If the short circuit is still persistent after the new startup sequence, switching
will be stopped again and there will be another 230 µs off period. A persistent output short condition results in a
hiccup behavior where the LMZ10500 goes through the normal startup sequence, then detects the output short
at the end of startup, terminates switching for 230 µs, and repeats this cycle until the output short is released.
This behavior is illustrated in Figure 7-2.
VOUT
IIN
IL
VCON
1V/Div
100 µs/Div
50 mA/Div
0.3A/Div
1V/Div
Figure 7-2. Hiccup Behavior With Persistent Output Short Circuit
Because the output current is limited during normal startup by the softstart function, the current charging the
output capacitor is also limited. This results in a smooth VOUT ramp up to nominal voltage. However, using
10
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excessively large output capacitance or VCON capacitance under normal conditions can prevent the output
voltage from reaching 0.375 V at the end of the startup sequence. In such cases the module will maintain the
described above hiccup mode and the output voltage will not ramp up to final value. To cause this condition, one
can have to use unnecessarily large output capacitance for 650mA load applications. See the Section 8.2.2.5
section for guidance on maximum capacitances for different output voltage settings.
7.3.4 Thermal Overload Protection
The junction temperature of the LMZ10500 must not be allowed to exceed its maximum operating rating of
125°C. Thermal protection is implemented by an internal thermal shutdown circuit which activates at 150°C (typ).
When this temperature is reached, the device enters a low power standby state. In this state switching remains
off causing the output voltage to fall. Also, the VCON capacitor is discharged to SGND. When the junction
temperature falls back below 130°C (typ) normal startup occurs and VOUT rises smoothly from 0 V. Applications
requiring maximum output current can require derating at elevated ambient temperature. See Section 6.7 for
thermal derating plots for various output voltages.
7.4 Device Functional Modes
7.4.1 Circuit Operation
The LMZ10500 is a synchronous Buck power module using a PFET for the high side switch and an NFET for
the synchronous rectifier switch. The output voltage is regulated by modulating the PFET switch on-time. The
circuit generates a duty-cycle modulated rectangular signal. The rectangular signal is averaged using a low pass
filter formed by the integrated inductor and an output capacitor. The output voltage is equal to the average of
the duty-cycle modulated rectangular signal. In PWM mode, the switching frequency is constant. The energy
per cycle to the load is controlled by modulating the PFET on-time, which controls the peak inductor current. In
current mode control architecture, the inductor current is compared with the slope compensated output of the
error amplifier. At the rising edge of the clock, the PFET is turned ON, ramping up the inductor current with a
slope of (VIN – VOUT) / L. The PFET is ON until the current signal equals the error signal. Then the PFET is
turned OFF and NFET is turned ON, ramping down the inductor current with a slope of VOUT / L. At the next
rising edge of the clock, the cycle repeats. An increase of load pulls the output voltage down, resulting in an
increase of the error signal. As the error signal goes up, the peak inductor current is increased, elevating the
average inductor current and responding to the heavier load. To specify stability, a slope compensation ramp is
subtracted from the error signal and internal loop compensation is provided.
7.4.2 Input Undervoltage Detection
The LMZ10500 implements an under voltage lock out (UVLO) circuit to specify proper operation during startup,
shutdown and input supply brownout conditions. The circuit monitors the voltage at the VIN pin to specify that
sufficient voltage is present to bias the regulator. If the under voltage threshold is not met, all functions of the
controller are disabled and the controller remains in a low power standby state.
7.4.3 Shutdown Mode
To shutdown the LMZ10500, pull the EN pin low (< 0.5 V). In the shutdown mode all internal circuits are turned
OFF.
7.4.4 EN Pin Operation
The EN pin is internally pulled up to VIN through a 790 kΩ (typical) resistor. This allows the nano module to be
enabled by default when the EN pin is left floating. In such cases VIN will set EN high when VIN reaches 1.2 V.
As the input voltage continues to rise, operation will start after VIN exceeds the under-voltage lockout (UVLO)
threshold. To set EN high externally, pull it up to 1.2 V or higher. Note that the voltage on EN must remain at less
than VIN + 0.2 V due to absolute maximum ratings of the device.
7.4.5 Internal Synchronous Rectification
The LMZ10500 uses an internal NFET as a synchronous rectifier to minimize the switch voltage drop and
increase efficiency. The NFET is designed to conduct through its intrinsic body diode during the built-in dead
time between the PFET on-time and the NFET on-time. This eliminates the need for an external diode. The
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dead time between the PFET and NFET connection prevents shoot through current from VIN to PGND during the
switching transitions.
7.4.6 High Duty Cycle Operation
The LMZ10500 features a transition mode designed to extend the output regulation range to the minimum
possible input voltage. As the input voltage decreases closer and closer to VOUT, the off-time of the PFET gets
smaller and smaller and the duty cycle eventually must reach 100% to support the output voltage. The input
voltage at which the duty cycle reaches 100% is the edge of regulation. When the LMZ10500 input voltage is
lowered, such that the off-time of the PFET reduces to less than 35ns, the LMZ10500 doubles the switching
period to extend the off-time for that VIN and maintain regulation. If VIN is lowered even more, the off-time of the
PFET will reach the 35ns mark again. The LMZ10500 will then reduce the frequency again, achieving less than
100% duty cycle operation and maintaining regulation. As VIN is lowered even more, the LMZ10500 will continue
to scale down the frequency, aiming to maintain at least 35ns off time. Eventually, as the input voltage decreases
further, 100% duty cycle is reached. This behavior of extending the VIN regulation range is illustrated in Figure
7-3.
1V/Div
INPUT VOLTAGE
1V/Div
SWITCH NODE
20 MHz BW
5 µs/Div
Figure 7-3. High Duty Cycle Operation and Switching Frequency Reduction
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
This section describes a simple design procedure. Alternatively, WEBENCH® can be used to create and
simulate a design using the LMZ10501. The WEBENCH® tool can be accessed from the LMZ10500 product
folder at http://www.ti.com/product/lmz10500. For designs with typical output voltages (1.2 V, 1.8 V, 2.5 V, 3.3 V),
jump to the Section 8.2.3 section for quick reference designs.
8.2 Typical Application
EN
VREF
RT
VCON
RB
CVC
FB
VIN
CIN
10PF
PGND
SGND
VOUT
COUT
10PF
Figure 8-1. Typical Application Circuit
8.2.1 Design Requirements
The detailed design procedure is based on the required input and output voltage specifications for the design.
The input voltage range of the LMZ10500 is 2.7 V to 5.5 V. The output voltage range is 0.6 V to 3.6 V. The output
current capability is 650 mA.
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ10500 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
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8.2.2.2 Setting the Output Voltage
The LMZ10500 provides a fixed 2.35-V VREF voltage output. As shown in Figure 8-1 above, a resistive divider
formed by RT and RB sets the VCON pin voltage level. The VOUT voltage tracks VCON and is governed by the
following relationship:
VOUT = GAIN × VCON
(1)
where
•
GAIN is 2.5 V/V from VCON to VFB.
This equation is valid for output voltages between 0.6 V and 3.6 V and corresponds to VCON voltage between
0.24 V and 1.44 V, respectively.
8.2.2.2.1 RT and RB Selection for Fixed VOUT
The parameters affecting the output voltage setting are the RT, R B, and the product of the VREF voltage × GAIN.
The VREF voltage is typically 2.35 V. Because VCON is derived from VREF through RT and RB,
VCON = VREF × RB/ (RB + RT)
(2)
After substitution,
VOUT = VREF × GAIN × RB/ (RB + RT)
(3)
RT = ( GAIN × VREF / VOUT – 1 ) x RB
(4)
The ideal product of GAIN × VREF = 5.875 V.
Choose RT to be between 80 kΩ and 300 kΩ. Then, RB can be calculated using Equation 5.
RB = ( VOUT / (5.875V – VOUT) ) x RT
(5)
Note that the resistance of RT must be ≥ 80 kΩ. This ensures that the VREF output current loading is not
exceeded and the reference voltage is maintained. The current loading on VREF must not be greater than 30 µA.
8.2.2.2.2 Output Voltage Accuracy Optimization
Each nano module is optimized to achieve high VOUT accuracy. Equation 1 shows that, by design, the output
voltage is a function of the VCON voltage and the gain from VCON to VFB. The voltage at VCON is derived from
VREF. Therefore, as shown in Equation 3, the accuracy of the output voltage is a function of the VREF × GAIN
product as well as the tolerance of the RT and RB resistors. The typical VREF × GAIN product by design is
5.875V. Each nano module's VREF voltage is trimmed so that this product is as close to the ideal 5.875V value as
possible, achieving high VOUT accuracy. See Section 6.5 for the VREF × GAIN product tolerance limits.
8.2.2.3 Dynamic Output Voltage Scaling
The VCON pin on the LMZ10500 can be driven externally by a DAC to scale the output voltage dynamically. The
output voltage VOUT = 2.5 V/V x VCON. When driving VCON with a source different than VREF place a 1.5 kΩ
resistor in series with the VCON pin. Current limiting the external VCON helps to protect this pin and allows the
VCON capacitor to be fully discharged to 0 V after fault conditions.
8.2.2.4 Integrated Inductor
The LMZ10500 includes an inductor with over 1.2A DC current rating and soft saturation profile for up to 2 A.
This inductor allows for low package height and provides an easy to use, compact solution with reduced EMI.
8.2.2.5 Input and Output Capacitor Selection
The LMZ10500 is designed for use with low ESR multi-layer ceramic capacitors (MLCC) for its input and output
filters. Using a 10-µF 0603 or 0805 with 6.3-V or 10-V rating ceramic input capacitor typically provides sufficient
VIN bypass. Use of multiple 4.7-µF or 2.2-µF capacitors can also be considered. Ceramic capacitors with X5R
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and X7R temperature characteristics are recommended for both input and output filters. These provide an
optimal balance between small size, cost, reliability, and performance for space sensitive applications.
The DC voltage bias characteristics of the capacitors must be considered when selecting the DC voltage rating
and case size of these components. The effective capacitance of an MLCC is typically reduced by the DC
voltage bias applied across its terminals. For example, a typical 0805 case size X5R 6.3-V 10-µF ceramic
capacitor can only have 4.8 µF left in it when a 5.0-V DC bias is applied. Similarly, a typical 0603 case size X5R
6.3-V 10-µF ceramic capacitor can only have 2.4 µF at the same 5.0-V DC. Smaller case size capacitors can
have even larger percentage drop in value with DC bias.
The optimum output capacitance value is application dependent. Too small output capacitance can lead to
instability due to lower loop phase margin. On the other hand, if the output capacitor is too large, it can prevent
the output voltage from reaching the 0.375V required voltage level at the end of the startup sequence. In such
cases, the output short circuit protection can be engaged and the nano module will enter a hiccup mode as
described in the Section 7.3.3 section. Table 8-1 sets the minimum output capacitance for stability and maximum
output capacitance for proper startup for various output voltage settings. Note that the maximum COUT value in
Table 8-1 assumes that the filter capacitance on VCON is the maximum recommended value of 1nF and the RT
resistor value is less than 300kΩ. Lower VCON capacitance can extend the maximum COUT range. There is no
great performance benefit in using excessive COUT values.
Table 8-1. Output Capacitance Range
OUTPUT VOLTAGE
MINIMUM
COUT
SUGGESTED
COUT
MAXIMUM
COUT
0.6 V
4.7 µF
10 µF
33 µF
1V
3.3 µF
10 µF
33 µF
1.2V
3.3 µF
10 µF
33 µF
1.8 V
3.3 µF
10 µF
47 µF
2.5 V
3.3 µF
10 µF
68 µF
3.3V
3.3 µF
10 µF
68 µF
Use of multiple 4.7-µF or 2.2-µF output capacitors can be considered for reduced effective ESR and smaller
output voltage ripple. In addition to the main output capacitor, small 0.1-µF – 0.01-µF parallel capacitors can be
used to reduce high frequency noise.
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8.2.3 Application Curves
8.2.3.1 VOUT = 1.2 V
VIN
100
1.2V
VOUT
CIN
VIN
EN
90
VOUT
80
FB
VCON
RB
EFFICIENCY (%)
VREF
RT
PGND
COUT
SGND
CVC
70
60
50
VIN=2.7V
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
40
CIN
COUT
CVC
RT
RB
10 P) 8 6.3V
10 PF 8 6.3V
470 pF 8 6.3V
243 k: 1%
63.4 k: 1%
0805 X7R or X5R
0805 X7R or X5R
0603 X7R or X5R
0603
0603
30
20
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
Figure 8-2. Schematic VOUT = 1.2 V
C001
Figure 8-3. Efficiency VOUT = 1.2 V
COUT = 10 F 10V 0805 X5R
50mV/Div
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
OUTPUT VOLTAGE
10mV/Div
LOAD CURRENT
500mA/Div
250MHz BW
1µs/Div
20 MHz BW
Figure 8-4. Output Ripple VOUT = 1.2 V
1.8
VIN=2.7V
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
1.23
Typical DC Current Limit (A)
OUTPUT VOLTAGE (V)
1.24
1.22
1.21
1.6
1.4
1.2
1.0
0.8
0.6
1.20
0
2.5
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
3.0
3.5
4.0
4.5
Input Voltage (V)
C002
Figure 8-6. Line and Load Regulation VOUT = 1.2 V
16
500 µs/Div
Figure 8-5. Load Transient VOUT = 1.2 V
5.0
5.5
C001
Figure 8-7. DC Current Limit VOUT = 1.2 V
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8.2.3.2 VOUT = 1.8 V
VIN
100
1.8V
VOUT
CIN
EN
VIN
90
VOUT
80
FB
VCON
RB
EFFICIENCY (%)
VREF
RT
PGND
COUT
SGND
CVC
70
60
50
VIN=2.7V
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
40
CIN
COUT
CVC
RT
RB
10 P) 8 6.3V
10 PF 8 6.3V
470 pF 8 6.3V
187 k: 1%
82.5 k: 1%
0805 X7R or X5R
0805 X7R or X5R
0603 X7R or X5R
0603
0603
30
20
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
Figure 8-8. Schematic VOUT = 1.8 V
C003
Figure 8-9. Efficiency VOUT = 1.8 V
COUT = 10 F 10V 0805 X5R
50mV/Div
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
OUTPUT VOLTAGE
10mV/Div
LOAD CURRENT
500mA/Div
250MHz BW
1µs/Div
20 MHz BW
Figure 8-10. Output Ripple VOUT = 1.8 V
Figure 8-11. Load Transient VOUT = 1.8 V
1.8
VIN=2.7V
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
1.80
Typical DC Current Limit (A)
OUTPUT VOLTAGE (V)
1.81
500 µs/Div
1.79
1.78
1.6
1.4
1.2
1.0
0.8
0.6
1.77
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
2.5
Figure 8-12. Line and Load Regulation VOUT = 1.8 V
3.0
3.5
4.0
4.5
Input Voltage (V)
C004
5.0
5.5
C001
Figure 8-13. DC Current Limit VOUT = 1.8 V
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8.2.3.3 VOUT = 2.5 V
VIN
100
2.5V
VOUT
CIN
EN
VIN
90
VOUT
80
FB
VCON
RB
EFFICIENCY (%)
VREF
RT
PGND
COUT
SGND
CVC
70
60
50
40
CIN
COUT
CVC
RT
RB
10 P) 8 6.3V
10 PF 8 6.3V
470 pF 8 6.3V
150 k: 1%
118 k: 1%
0805 X7R or X5R
0805 X7R or X5R
0603 X7R or X5R
0603
0603
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
30
20
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
Figure 8-14. Schematic VOUT = 2.5 V
C005
Figure 8-15. Efficiency VOUT = 2.5 V
COUT = 10 F 10V 0805 X5R
50mV/Div
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
OUTPUT VOLTAGE
10mV/Div
LOAD CURRENT
500mA/Div
250MHz BW
1µs/Div
20 MHz BW
Figure 8-17. Load Transient VOUT = 2.5 V
Figure 8-16. Output Ripple VOUT = 2.5 V
1.8
Typical DC Current Limit (A)
OUTPUT VOLTAGE (V)
2.65
2.60
2.55
2.50
VIN=3.3V
VIN=3.6V
VIN=5V
VIN=5.5V
2.45
0
1.6
1.4
1.2
1.0
0.8
0.6
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
C006
Figure 8-18. Line and Load Regulation VOUT = 2.5 V
18
500 µs/Div
5.0
5.5
C001
Figure 8-19. DC Current Limit VOUT = 2.5 V
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8.2.3.4 VOUT = 3.3 V
VIN
100
3.3V
VOUT
CIN
EN
VIN
90
VOUT
80
FB
VCON
RB
EFFICIENCY (%)
VREF
RT
PGND
COUT
SGND
CVC
70
60
50
40
CIN
COUT
CVC
RT
RB
10 P) 8 6.3V
10 PF 8 6.3V
470 pF 8 6.3V
118 k: 1%
150 k: 1%
0805 X7R or X5R
0805 X7R or X5R
0603 X7R or X5R
0603
0603
VIN=4V
VIN=4.5V
VIN=5V
VIN=5.5V
30
20
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
Figure 8-20. Schematic VOUT = 3.3 V
C007
Figure 8-21. Efficiency VOUT = 3.3 V
COUT = 10 F 10V 0805 X5R
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
50mV/Div
OUTPUT VOLTAGE
10mV/Div
LOAD CURRENT
500mA/Div
250MHz BW
1µs/Div
20 MHz BW
Figure 8-22. Output Ripple VOUT = 3.3 V
Figure 8-23. Load Transient VOUT = 3.3 V
1.8
3.30
Typical DC Current Limit (A)
3.29
OUTPUT VOLTAGE (V)
500 µs/Div
3.28
3.27
3.26
3.25
3.24
VIN=4V
VIN=4.5V
VIN=5V
VIN=5.5V
3.23
3.22
0
1.4
1.2
1.0
0.8
0.6
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
LOAD CURRENT (A)
1.6
2.5
3.5
4.0
4.5
5.0
Input Voltage (V)
C008
Figure 8-24. Line and Load Regulation VOUT = 3.3 V
3.0
5.5
C001
Figure 8-25. DC Current Limit VOUT = 3.3 V
8.3 Power Supply Recommendations
8.3.1 Voltage Range
The voltage of the input supply must not exceed the Section 6.1 and the Section 6.3 of the LMZ10500.
8.3.2 Current Capability
The input supply must be able to supply the required input current to the LMZ10500 converter. The required
input current depends on the application's minimum required input voltage (VIN-MIN), the required output power
(VOUT × IOUT-MAX), and the converter efficiency (η).
IIN = VOUT × IOUT-MAX / (VIN-MIN × η)
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For example, for a design with 5-V minimum input voltage,1.8-V output, and 0.5-A maximum load, considering
90% conversion efficiency, the required input current at steady state is 0.2 A.
8.3.3 Input Connection
Long input connection cables can cause issues with the normal operation of any buck converter.
8.3.3.1 Voltage Drops
Using long input wires to connect the supply to the input of any converter adds impedance in series with the
input supply. This impedance can cause a voltage drop at the VIN pin of the converter when the output of the
converter is loaded. If the input voltage is near the minimum operating voltage, this added voltage drop can
cause the converter to drop out or reset. If long wires are used during testing, it is recommended to add some
bulk (i.e. electrolytic) capacitance at the input of the converter.
8.3.3.2 Stability
The added inductance of long input cables together with the ceramic (and low ESR) input capacitor can result
in an under damped RLC network at the input of the Buck converter. This can cause oscillations on the input
and instability. If long wires are used, it is recommended to add some electrolytic capacitance in parallel with the
ceramic input capacitor. The electrolytic capacitor's ESR will improve the damping.
Use an electrolytic capacitor with CELECTROLYTIC≥ 4 × CCERAMIC and ESRELECTROLYTIC≈ √ (LCABLE / CCERAMIC)
For example, two cables (one for VIN and one for GND), each 1 meter (~3 ft) long with ~1 mm diameter
(18AWG), placed 1 cm (~0.4 in) apart will form a rectangular loop resulting in about 1.2 µH of inductance. The
inductance in this example can be decreased to almost half if the input wires are twisted. Based on a 10-µF
ceramic input capacitor, the recommended parallel CELECTROLYTIC is ≥ 40 µF. Using a 47-µF capacitor will be
sufficient. The recommended ESRELECTROLYTIC≈ 0.35 Ω or larger, based on about 1.2 µH of inductance and 10
µF of ceramic input capacitance.
See application note SNVA489 for more details on input filter design.
8.4 Layout
8.4.1 Layout Guidelines
The board layout of any DC/DC switching converter is critical for the optimal performance of the design. Bad
PCB layout design can disrupt the operation of an otherwise good schematic design. Even if the regulator
still converts the voltage properly, the board layout can mean the difference between passing or failing EMI
regulations. In a Buck converter, the most critical board layout path is between the input capacitor ground
terminal and the synchronous rectifier ground. The loop formed by the input capacitor and the power FETs is a
path for the high di/dt switching current during each switching period. This loop must always be kept as short as
possible when laying out a board for any Buck converter.
The LMZ10500 integrates the inductor and simplifies the DC/DC converter board layout. Refer to the example
layout in Figure 8-26. There are a few basic requirements to achieve a good LMZ10500 layout.
1. Place the input capacitor CIN as close as possible to the VIN and PGND pins. VIN (pin 7) and PGND (pin 6)
on the LMZ10500 are next to each other which makes the input capacitor placement simple.
2. Place the VCON filter capacitor CVC and the RB RT resistive divider as close as possible to the VCON and
SGND terminals.The CVC capacitor (not RB) must be the component closer to the VCON pin, as shown in
Figure 8-26. This allows for better bypass of the control voltage set at VCON.
3. Run the feedback trace (from VOUT to FB) away from noise sources.
4. Connect SGND to a quiet GND plane.
5. Provide enough PCB area for proper heatsinking. Refer to the Section 6.5 table for example θJA values for
different board areas. Also, refer to AN-2020 for additional thermal design hints.
Refer to the evaluation board user's guide LMZ10501SIL and LMZ10500SIL SIMPLE SWITCHER® Nano
Module Evaluation Board for a complete board layout example.
20
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8.4.2 Layout Example
RB
RESISTOR
RT
RESISTOR
EN
HIGH di/dt LOOP
KEEP IT SMALL
VREF
VCON
VIN
FB
PGND
SGND
VOUT
VIN
PGND
INPUT
CAPACITOR
VOUT
FEEDBACK
TRACE
SGND CONNECTION TO
QUIET PGND PLANE
OUTPUT
CAPACITOR
VCON
CAPACITOR
Figure 8-26. Example Top Layer Board Layout
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8.4.3 Package Considerations
Use the following recommendations when using machine placement :
•
•
•
•
•
Use 1.06 mm (42 mil) or smaller nozzle size. The pickup area is the top of the inductor, which is 1.6 mm × 2
mm.
Soft tip pick and place nozzle is recommended.
Add 0.05 mm to the component thickness so that the device will be released 0.05 mm (2 mil) into the solder
paste without putting pressure or splashing the solder paste.
Slow the pick arm when picking the part from the tape and reel carrier and when depositing the IC on the
board.
If the machine releases the component by force, use minimum force or no more than 3 Newtons.
For manual placement:
•
•
•
•
•
22
Use a vacuum pick up hand tool with soft tip head.
If vacuum pick up tool is not available, use non-metal tweezers and hold the part by sides.
Use minimal force when picking and placing the module on the board.
Using hot air station provides better temperature control and better controlled air flow than a heat gun.
Go to the video section at www.ti.com/product/lmz10500 for a quick video on how to solder rework the
LMZ10500.
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ10500 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Documentation Support
9.2.1 Related Documentation
•
•
Texas Instruments, AN-2162 Simple Success With Conducted EMI From DC- DC Converters application
report
Texas Instruments, LMZ10501SIL and LMZ10500SIL SIMPLE SWITCHER® Nano Module Evaluation Board
user's guide
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® and SIMPLE SWITCHER® are registered trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
LMZ10500SILR
ACTIVE
uSiP
SIL
8
3000
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 125
500
0500 9821 DH
Samples
LMZ10500SILT
ACTIVE
uSiP
SIL
8
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 125
500
0500 9821 DH
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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