LMZ20501
SNVS874E – AUGUST 2012 – REVISED SEPTEMBER 2021
LMZ20501 1-A Nano Module
1 Features
3 Description
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•
•
•
•
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The LMZ20501 nano module regulator is an easyto-use synchronous step-down DC/DC converter
capable of driving up to 1 A of load from an input
of up to 5.5 V, with exceptional efficiency and output
accuracy in a very small solution size. The innovative
package contains the regulator and inductor in a
small 3.5 mm × 3.5 mm × 1.75 mm volume,
thus saving board space and eliminating the time
and expense of inductor selection. The LMZ20501
requires only five external components and has a pinout designed for simple, optimum PCB layout. The
device provides for an easy to use complete design
with a minimum number of external components
and the TI WEBENCH® design tool. TI's WEBENCH
tool includes features such as external component
calculation, electrical simulation, and WebTherm®.
For soldering information, see SNOA401.
2 Applications
•
•
Device Information
Point-of-load regulation
Space-constrained applications
PART NUMBER
LMZ20501
(1)
PACKAGE(1)
USIP (8)
BODY SIZE (NOM)
3.50 mm × 3.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
EN
VIN
VOUT
VOUT
3V
4.2V
5V
90
VIN
RFBT
LMZ20501
80
CFF
CIN
70
FB
GND
MODE
PG
COUT
RFBB
Efficiency (%)
•
Integrated inductor
Miniature 3.5-mm × 3.5-mm × 1.75-mm package
1-A maximum load current
Input voltage range of 2.7 V to 5.5 V
Adjustable output voltage range of 0.8 V to 3.6 V
± 1% feedback tolerance over temperature
2.4-µA (maximum) quiescent current in shutdown
3-MHz fixed PWM switching frequency
–40°C to 125°C junction temperature range
Power-good flag function
Pin-selectable switching modes
Internal compensation and soft start
Current limit, thermal shutdown, and UVLO
protection
Create a custom design using the LMZ20501 with
WEBENCH® Power Designer
60
50
40
30
20
Simplified Schematic
10
0
0.01
0.1
Output Current (A)
1
10
C003
Typical Efficiency for VOUT = 1.8 V Auto Mode
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 System Characteristics............................................... 6
6.7 Typical Characteristics................................................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................13
8 Application and Implementation.................................. 16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 16
8.3 Do's and Don'ts.........................................................23
9 Power Supply Recommendations................................23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 25
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 27
11.3 Receiving Notification of Documentation Updates.. 28
11.4 Support Resources................................................. 28
11.5 Trademarks............................................................. 28
11.6 Electrostatic Discharge Caution.............................. 28
11.7 Glossary.................................................................. 28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 29
12.1 Tape and Reel Information......................................29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2018) to Revision E (September 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Updated Figure 7-3 title.................................................................................................................................... 10
Changes from Revision C (April 2015) to Revision D (August 2018)
Page
• Deleted Simple Switcher branding; added links for WEBENCH ........................................................................1
2
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5 Pin Configuration and Functions
PG
EN
MODE
FB
1
8
2
7
VIN
NC
3
6
GND
4
5
VOUT
Figure 5-1. 8-Pins USIP Package (SIL) (Top View)
Table 5-1. Pin Functions
PIN
NUMBER
TYPE(1)
NAME
DESCRIPTION
PG
O
Power-good flag; open drain. Connect to logic supply through a resistor. High = power good; low =
power bad. If not used, leave unconnected.
EN
I
Enable input. High = On, Low = Off. A valid input voltage, on pin 8, must be present before EN is
asserted. Do not float.
3
MODE
I
Mode selection input. High = forced PWM. Low = AUTO mode with PFM at light load. Do not float.
4
FB
I
Feedback input to controller. Connect to output through feedback divider.
5
VOUT
P
Regulated output voltage. Connect to COUT.
6
GND
G
Ground for all circuitry. Reference point for all voltages
1
2
7
8
EP
(1)
NC
—
This pin must be left floating. Do not connect to ground or any other node.
VIN
P
Input supply to regulator. Connect to input capacitor(s) as close as possible to the VIN pin and GND
pin of the module.
EP
G
Ground and heat-sink connection. See Section 10.1 for more information.
G = Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
Under the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted) (1)
VIN to GND
EN, MODE, FB, PG, to
GND(2)
VOUT to GND(2)
MIN
MAX
UNIT
–0.2
6
V
–0.2
VIN+0.2
–0.2
VIN+0.2
Junction temperature
150
°C
Peak soldering reflow temperature for Pb(3)
240
°C
Peak soldering reflow temperature for
No-Pb(3)
260
Storage temperature range
(1)
(2)
(3)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The absolute maximum voltage on this pin must not exceed 6 V with respect to ground. Do not allow the voltage on the output pin to
exceed the voltage on the input pin by more than 0.2 V.
For soldering information, please refer to the following document: SNOA401.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Under the recommended operating junction temperature range of -40°C to 125°C (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
Input voltage
2.7
5.5
V
Output voltage programming
0.8
3.6
V
0
3.6
V
0
1
A
0
4
mA
-40
125
°C
Output voltage range
(2)
Load current
Power good flag current
Junction temperature
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Under no conditions should the output voltage be allowed to fall below zero volts.
6.4 Thermal Information
LMZ20501
THERMAL
METRIC(1)
USIP (SIL)
UNIT
8 PINS
4
RθJA
Junction-to-ambient thermal resistance
42.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.8
°C/W
RθJB
Junction-to-board thermal resistance
9.4
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
9.3
°C/W
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LMZ20501
THERMAL METRIC(1)
UNIT
USIP (SIL)
8 PINS
RθJC(bot)
(1)
Junction-to-case (bottom) thermal resistance
1.8
°C/W
The values given in this table are only valid for comparison with other packages and can not be used for design purposes. For
design information please see the Section 8.2.1.5 section. For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature range of –40°C to 125°C, unless otherwise noted.
Minimum and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 3.6 V
PARAMETER
TEST CONDITIONS
MIN (1)
TYP
MAX(1)
0.594
UNIT
VFB
Feedback voltage
VIN = 3.6 V
0.6
0.606
V
IQ_AUTO
Operating quiescent current in
AUTO mode
AUTO mode, VFB = 0.8 V
72
90
µA
IQ_PWM
Operating quiescent current in
forced PWM mode
PWM mode, VFB = 0.8 V
490
620
µA
IQ_off
Shutdown quiescent current(2)
VIN = 3.6 V, VEN = 0.0 V
0.7
1.5
VIN = 5.5 V, VEN = 0.0 V
1.0
2.4
Input supply undervoltage
lockout thresholds
Rising
2.5
Falling
2.3
High level input voltage
VIH
Low level input voltage
VIL
High level input voltage
VIH
Low level input voltage
VIL
VUVLO
VEN
VMODE
0.4
1.2
0.4
Peak switch current limit(3)
1.3
1.7
Fosc
Internal oscillator frequency
2.5
3.0
TON
Minimum switch on time(5)
Tss
Soft-start time(5)
RPG
Power-good flag pulldown
Rdson
VPG1
Power good flag, undervoltage % of feedback voltage, rising
trip(4)
92%
VPG2
Power good flag, undervoltage % of feedback voltage, falling
trip(4)
88%
VPG3
Power good flag, overvoltage
trip(4)
% of feedback voltage, rising
VPG4
Power good flag, overvoltage
trip(4)
% of feedback voltage, falling
TSD
Thermal shutdown(5)
Rising threshold
40
Thermal shutdown
hysteresis(5)
(1)
(2)
(3)
(4)
(5)
V
1.4
I LIM
µA
V
V
A
3.2
MHz
50
ns
800
µs
70
110
Ω
112%
108%
159
°C
15
°C
MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Shutdown current includes leakage current of the switching transistors.
This is the peak switch current limit measured with a slow current ramp. Due to inherent delays in the current limit comparator, the
peak current limit measured at 3MHz will be larger.
See Section 7.3.6 for explanation of voltage levels.
This parameter is not tested in production.
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6.6 System Characteristics
The following specifications apply to the circuit found in Figure 8-1 with the appropriate modifications from Table 8-1. These
parameters are not tested in production and represent typical performance only. Unless otherwise stated the following
conditions apply: TA = 25°C.
PARAMETER
Load
Regulation
Line
Regulation
VR-PWM
VR-PFM
Load
Transient
Line
Transient
6
TEST CONDITIONS
MIN
TYP
VOUT = 1.2 V,
VIN = 5 V, IOUT = 0 A to 1 A, PWM
0.14%
VOUT = 1.8 V
Percent output voltage change
for the given load current change VIN = 5 V, IOUT = 0 A to 1 A, PWM
0.15%
VOUT = 3.3 V
VIN = 5 V, IOUT = 0 A to 1 A, PWM
0.11%
VOUT = 1.2 V
IOUT = 1 A, VIN = 3 V to 5 V, PWM
0.16%
VOUT = 1.8 V
IOUT = 1 A, VIN = 3 V to 5 V, PWM
0.12%
VOUT = 3.3 V
IOUT = 1 A,VIN = 4 V to 5 V, PWM
0.1%
Percent output voltage change
for the given change in input
voltage
Output voltage ripple in PWM
Output voltage ripple in PFM
Output voltage deviation from
nominal due to a load current
step
Output voltage deviation due to
an input voltage step
VOUT = 1.2 V
IOUT = 1 A, VIN = 5 V, PWM
3.3
VOUT = 1.8 V
IOUT = 1 A, VIN = 5 V, PWM
3.3
VOUT = 3.3V
IOUT= 1 A, VIN = 5 V, PWM
4.2
VOUT = 1.2V
IOUT= 1 mA, VIN = 3 V, PFM
22
VOUT = 1.8 V
IOUT= 1 mA, VIN=3 V, PFM
22
VOUT = 3.3 V
IOUT = 1 mA, VIN = 5 V, PFM
40
VOUT = 1.2 V
VIN = 5 V, IOUT = 0 A to 1 A, Tr = Tf = 2 µs,
PWM
±60
VOUT = 1.8 V
VIN = 5 V, IOUT = 0 A to 1 A, Tr = Tf = 2 µs,
PWM
±50
VOUT = 3.3 V
VIN = 5 V, IOUT = 0 A to 1 A, Tr = Tf = 2 µs,
PWM
±60
VOUT = 1.2V
IOUT = 1 A, VIN = 3 V to 5 V, Tr = Tf = 50 µs,
PWM
25
VOUT = 1.8 V
IOUT = 1 A, VIN = 3 V to 5 V, Tr = Tf = 50 µs,
PWM
30
VOUT = 3.3 V
IOUT = 1 A, VIN = 4 V to 5 V, Tr = Tf = 50 µs,
PWM
20
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MAX
UNIT
mV pk-pk
mV pk-pk
mV
mV pk-pk
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The following specifications apply to the circuit found in Figure 8-1 with the appropriate modifications from Table 8-1. These
parameters are not tested in production and represent typical performance only. Unless otherwise stated the following
conditions apply: TA = 25°C.
PARAMETER
Peak efficiency
η
Full load efficiency
TEST CONDITIONS
MIN
TYP
VOUT = 1.2 V
VIN = 3 V
87%
VOUT = 1.8 V
VIN = 3 V
91%
VOUT = 3.3 V
VIN = 4.2 V
94%
VOUT = 1.2 V
VIN = 3 V, IOUT = 1 A
83%
VOUT = 1.8 V
VIN = 3 V, IOUT = 1 A
87%
VOUT = 3.3 V
VIN = 4.2 V, IOUT = 1 A
93%
MAX
UNIT
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6.7 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 3.6 V, TA = 25°C.
1.82
3.2
Iout = 0 A
Iout = 1 A
Switching Frequency (MHz)
Output Voltage (V)
1.81
-40°C
27°C
90°C
3.15
1.8
1.79
1.78
1.77
3.1
3.05
3
2.95
2.9
2.85
2.8
2.75
2.7
2.65
1.76
-40
2.6
-20
0
20
40
Temperature (°C)
VIN = 3.6 V
60
80
100
2
PWM Mode
VOUT = 1.8 V
Figure 6-1. Typical Output Voltage vs Temperature
3
3.5
4
4.5
Input Voltage (V)
VIN = 3.6 V
5
5.5
6
D002
IOUT = 0 A
PWM Mode
Figure 6-2. Switching Frequency in PWM Mode
1
1
Rising
Falling
MODE Input Thresholds (V)
0.9
EN Input Thresholds (V)
2.5
D001
0.8
0.7
0.6
0.5
0.4
-40
-20
0
20
40
Temperature (°C)
60
80
Rising
Falling
0.9
0.8
0.7
0.6
0.5
0.4
-40
100
-20
0
D003
VIN = 3.6 V
20
40
Temperature (°C)
60
80
100
D004
VIN = 3.6 V
Figure 6-3. EN Input Thresholds
Figure 6-4. MODE Input Thresholds
0.6
80
75
-40°C
27°C
90°C
0.55
Input Current (mA)
Input Current (µA)
70
65
60
55
0.5
0.45
0.4
50
-40°C
27°C
90°C
45
0.35
40
0.3
2
2.5
3
3.5
4
4.5
Input Voltage (V)
VFB = 0.8 V
5
5.5
6
AUTO Mode
2.5
3
VFB = 0.8 V
Figure 6-5. Non-Switching Input Current in AUTO
Mode
8
2
D005
3.5
4
4.5
Input Voltage (V)
5
5.5
6
D006
PWM Mode
Figure 6-6. Non-Switching Input Current in PWM
Mode
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7 Detailed Description
7.1 Overview
The LMZ20501 nano module is a voltage mode buck regulator with an integrated inductor. Input voltage
feedforward is used to compensate for loop gain variation with input voltage. Two operating modes allow
the user to tailor the regulator to their specific requirements. In forced PWM mode, the regulator operates as
a full synchronous device with a 3 MHz (typical) switching frequency and very low output voltage ripple. In
AUTO mode, the regulator moves into PFM when the load current drops below the mode change threshold
(see Section 8.2.2). In PFM, the device regulates the output voltage between wider ripple limits than in PWM.
This results in much smaller supply current than in PWM, at light loads, and high efficiency. A simplified block
diagram is shown in Section 7.2.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Nano Scale Package
The LMZ20501 incorporates world class package technology to provide a 1-A power supply with a total volume
of only 21 mm3 (excluding external components). All that is required for a complete power supply is the addition
of feedback resistors to set the output voltage and the input and output filter capacitors. Figure 7-1 and Figure
7-2 show the LMZ20501 package. The regulator die is embedded into a PCB substrate while the power inductor
is mounted on top. Vias and copper clad are used to make the connections to the die, inductor, and the external
components. This package is MSL3-compliant.
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Figure 7-1. Package Photo
INDUCTOR
EMBEDDED
REGULATOR
DIE
SUBSTRATE
PCB
Copper Clad
Via
Figure 7-2. Package Side View Drawing
7.3.2 Internal Synchronous Rectifier
The LMZ20501 uses an internal NMOS FET as a synchronous rectifier to minimize switch voltage drop and
increase efficiency. The NMOS is designed to conduct through its body diode during switch dead time. This dead
time is imposed to prevent supply current "shoot-through".
7.3.3 Current Limit Protection
The LMZ20501 incorporates cycle-by-cycle peak current limit on both the high- and low-side MOSFETs. This
feature limits the output current in case the output is overloaded. During the overload, the peak inductor current
is limited to that value found in Section 6.5 under the heading of "ILIM".
In addition to current limit, a short circuit protection mode is also implemented. When the feedback voltage is
brought down to less than 300 mV, but greater than 150 mV, by a short circuit, the synchronous rectifier is
turned off. This provides more voltage across the inductor to help maintain the required volt-second balance. If
a "harder" short brings the feedback voltage to below 150 mV, the current limit and switching frequency are both
reduced to approximately one half of the nominal values. In addition, when the current limit is tripped, the device
stops switching for approximately 85 µs. At the end of the time-out, switching resumes and the cycle repeats
until the short is removed.
The effect of both overload and short circuit protection can be seen in Figure 7-3. This graph demonstrates that
the device will supply slightly more than 1 A to the load when in overload and much less current during fold-back
mode. This is typical behavior for any regulator with this type of current limit protection.
10
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3.5
Output Voltage (V)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Output Current (A)
1.4
1.6
1.8
C001
Figure 7-3. Typical Current Limit Profile VIN = 5 V, VOUT = 3.3 V
7.3.4 Start-Up
Start-up and shutdown of the LMZ20501 is controlled by the EN input. The characteristics of this input are found
in Section 6.5. A valid input voltage must be present on VIN before the enable control is asserted. The maximum
voltage on the EN pin is 5.5 V or VIN, whichever is smaller. Do not allow this input to float.
The LMZ20501 features a current limit based soft start that prevents large inrush currents and output overshoots
as the regulator is starting up. The peak inductor current is stepped-up in a staircase fashion during the soft start
period. A typical start-up event is shown in Figure 7-4:
EN
Output Voltage
2V/div
PG
Input Current
0.5A/div
500µs/div
Figure 7-4. Typical Start-Up Waveforms, VIN = 5 V, VOUT = 3.3 V, IOUT = 1 A
7.3.5 Dropout Behavior
When the input voltage is close to the output voltage, the regulator will operate at very large duty cycles. Normal
time delays of the internal circuits prevents the attainment of controlled duty cycles near 100%. In this condition,
the LMZ20501 will skip switching cycles to maintain regulation with the highest possible input-to-output ratio.
Some increase in output voltage ripple can appear as the regulator skips cycles. As the input voltage gets closer
to the output voltage, the regulator will eventually reach 100% duty cycle, with the high side switch turned on.
The output will then follow the input voltage minus the drop across the high-side switch and inductor resistance.
Figure 7-5 and Figure 7-6 show typical dropout behavior for output voltages of 2.5 V and 3.3 V.
Since the internal gate drive levels of the LMZ20501 are dependent on input voltage, the Rdson of the
power FETs will increase at low input voltages. This will result in degraded efficiency at input voltages below
approximately 2.9 V. Also, combinations of low input voltage and high output voltage increase the effective
switch duty cycle, which can result in increased output voltage ripple.
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2.60
Output Voltage (V)
2.55
2.50
2.45
2.40
2.35
2.30
0A
0.5A
1A
2.25
2.20
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Input Voltage (V)
4.0
C009
Figure 7-5. Typical Dropout Behavior, VOUT = 2.5 V
3.6
Output Voltage (V)
3.4
3.2
3.0
2.8
2.6
2.4
0A
0.5A
1A
2.2
2.0
2.6
2.8
3.0
3.2
3.4
3.6
Input Voltage (V)
3.8
4.0
C008
Figure 7-6. Typical Dropout Behavior, VOUT = 3.3 V
12
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7.3.6 Power Good Flag Function
The operation of the power good flag function is described in the diagram shown in Figure 7-7.
VOUT
PG3 = 112%
PG4 = 108%
PG1 = 92%
PG2 = 88%
PGOOD
High = Good
Low = Bad
Figure 7-7. Typical Power Good-Flag Operation
This output consists of an open-drain NMOS with an Rdson of approximately 70 Ω. When used, the power-good
flag should be connected to a logic supply through a pullup resistor. It can also be pulled up to either VIN or VOUT
through an appropriate resistor, as desired. If this function is not needed, the PG output should be left floating.
The current through this flag pin should be limited to less than 4 mA. A pullup resistor of greater than or equal to
1.5 kΩ will satisfy this requirement. When the EN input is pulled low, the PG flag output will also be forced low,
assuming a valid input voltage is present at the VIN pin.
7.3.7 Thermal Shutdown
The LMZ20501 incorporates a thermal shutdown feature to protect the device from excessive die temperatures.
The device will stop switching when the internal die temperature reaches about 159°C. Switching will resume
when the die temperature drops to about 144°C.
7.4 Device Functional Modes
Please refer to Table 7-1 and the following paragraphs for a detailed description of the functional modes of the
LMZ20501. These modes are controlled by the MODE input as shown in Table 7-1. The maximum voltage on the
MODE pin is 5.5 V or VIN, whichever is smaller. This input must not be allowed to float.
Table 7-1. Mode Selection
MODE PIN VOLTAGE
OPERATION
> 1.2 V
Forced PWM: The regulator operates in constant frequency, PWM mode for all loads from
no-load to full load; no diode emulation is used.
< 0.4 V
AUTO Mode: The regulator operates in constant frequency mode for loads greater than
the mode change threshold. For loads less than the mode change threshold, the regulator
operates in PFM with diode emulation.
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7.4.1 PWM Operation
In forced PWM mode, the converter operates as a constant frequency voltage mode regulator with input voltage
feedforward. This provides excellent line and load regulation and low output voltage ripple. This operation is
maintained, even at no-load, by allowing the inductor current to reverse its normal direction. While in PWM
mode, the output voltage is regulated by switching at a constant frequency and modulating the duty cycle to
control the power to the load. This mode trades off reduced light load efficiency for low output voltage ripple
and constant switching frequency. In this mode, a negative current limit of approximately 750 mA is imposed to
prevent damage to the regulator power FETs.
7.4.2 PFM Operation
When in AUTO mode and at light loads, the device enters PFM. The regulator estimates the load current by
measuring both the high-side and low-side switch currents. This estimate is only approximate, and the exact
load current threshold, to trigger PFM, can vary greatly with input and output voltage. Section 8.2.2 shows mode
change thresholds for several typical operating points. When the regulator detects this threshold, the reference
voltage is increased by approximately 10 mV. This causes the output voltage to rise to meet the new regulation
point. When this point is reached, the converter stops switching and much of the internal circuitry is shut off,
while the reference is returned to the PWM value. This saves supply current while the output voltage naturally
starts to fall under the influence of the load current. When the output voltage reaches the PWM regulation point,
switching is again started and the reference voltage is again increased by approximately 10 mV, starting the next
cycle. Typical waveforms are shown in Figure 7-8.
Switch Voltage
2V/div
Output Voltage
50mV/div
20µs/div
Figure 7-8. Typical PFM Mode Waveforms: VIN = 3.6 V, VOUT = 1.8 V, IOUT = 10 mA
90
Input Supply Current (µA)
88
86
84
82
80
78
76
74
VOUT = 1.8 V
VOUT = 3.3 V
72
70
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
D007
Figure 7-9. Typical No Load Input Supply Current
The actual output voltage ripple will depend on the feedback divider ratio and on the delay in the PFM
comparator. The frequency of the PFM "bursts" will depend on the input voltage, output voltage, load, and
14
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output capacitor. Within each "burst", the device switches at 3 MHz (typical). If the load current increases above
the threshold, normal PWM operation is resumed. This mode provides high light load efficiency by reducing the
amount of supply current required to regulate the output at small load currents. This mode trades off very good
light load efficiency for larger output voltage ripple and variable switching frequency. An example of the typical
input supply current while regulating with no load is shown in Figure 7-9.
Because of normal part-to-part variation, the LMZ20501 may not switch into PFM mode at high input voltages.
This can be seen with output voltages of approximately 1.2 V and below, and at input voltages of approximately
4.2 V and above.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LMZ20501 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 1 A. The following design procedure can be used to select
components for the LMZ20501. Alternately, the WEBENCH design tool may be used to generate a complete
design. WEBENCH utilizes an iterative design procedure and has access to a comprehensive database of
components. This allows the tool to create an optimized design and allows the user to experiment with various
design options.
8.2 Typical Application
Figure 8-1 shows the minimum required application circuit for a 1.8-V output. Figure 8-2 shows a full featured
application circuit. Please refer to Figure 8-1 and Figure 8-2 during the following design procedures.
EN
VIN
VIN
2.7V to 5.5V
VOUT
VOUT
1.8V @ 1A
LMZ20501
RFBT
CIN
2x10µF
GND
MODE
PG
CFF
80.6kŸ
16pF
COUT
FB
10µF
RFBB
40.2kŸ
Figure 8-1. LMZ20501 Typical Application VOUT = 1.8 V
VIN
2.7V to 5.5V
2x10µF
100kŸ
CIN
VIN
RESET
PG
VOUT
µC
I/O
MODE
I/O
EN
LMZ20501
VOUT
1.8V @ 1A
RFBT
GND
CFF
80.6kŸ
16pF
COUT
FB
10µF
RFBB
40.2kŸ
Figure 8-2. LMZ20501 Full Featured Application
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8.2.1 Detailed Design Procedure
Please refer to Table 8-1 while following the detailed design procedure. This procedure applies to both Figure
8-1 and to Figure 8-2. Also, the Application Curves apply to both schematics.
Table 8-1. Recommended Component Values
VOUT (V)
RFBB (kΩ)
RFBT (kΩ)
COUT (µF)
EFFECTIVE COUT (µF)(2)
CFF (pF)
CIN (µF)(1)
EFFECTIVE CIN (µF)(2)
0.8
121
40.2
2 x 10
18 µF
39
2 x 10
14
1.2
30.1
30.1
10
8.8 µF
20
2 x 10
14
1.8
40.2
80.6
10
8.4 µF
16
2 x 10
14
2.5
47.5
150
10
7.8 µF
12
2 x 10
14
3.3
53.2
237
10
7.1 µF
82
2 x 10
14
3.6
53.2
267
10
6.8 µF
82
2 x 10
14
(1)
(2)
CIN = COUT = 10 µF, 16 V, 0805, X7R, Samsung CL21B106KOQNNNE. COUT measured at VOUT; CIN measured at 3.3 V.
The effective value takes into account the capacitor voltage coefficient.
8.2.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ20501 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2 Setting The Output Voltage
The LMZ20501 regulates its feedback voltage to 0.6 V (typical). A feedback divider, shown in Figure 8-1, is used
to set the desired output voltage. Equation 1 can be used to select RFBB.
R FBB
0.6
˜ R FBT
VOUT 0.6
(1)
For the best results, RFBT should be chosen between 30 kΩ and 300 kΩ. See Table 8-1 for recommended values
for typical output voltages.
8.2.1.3 Output and Feedforward Capacitors
The LMZ20501 is designed to work with low-ESR ceramic capacitors. The effective value of these capacitors is
defined as the actual capacitance under voltage bias and temperature. All ceramic capacitors have large voltage
coefficients, in addition to normal tolerances and temperature coefficients. Under D.C. bias, the capacitance
value drops considerably. Larger case sizes, higher voltage capacitors, or both are better in this regard. To
help mitigate these effects, multiple small capacitors can be used in parallel to bring the minimum effective
capacitance up to the desired value. This can also ease the RMS current requirements on a single capacitor.
Typically, 10-V, X5R, 0805 capacitors are adequate for the output, while 16-V capacitors can be used on
the input. Some recommended component values are provided in Table 8-1. Also, shown are the measured
values of effective input and output capacitance for the given capacitor. If smaller values of output capacitance
are used, CFF must be adjusted to give good phase margin. In any case, load transient response will be
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compromised with lower values of output capacitance. Values much lower than those found in Table 8-1 should
be avoided.
In practice, the output capacitor and CFF are adjusted for the best transient response and highest loop phase
margin. Load transient testing and Bode plots are the best way to validate any given design. The Optimizing
Transient Response of Internally Compensated DC-DC Converters Application Report should prove helpful when
optimizing the feedforward capacitor. Also, the AN-1889 How to Measure the Loop Transfer Function of Power
Supplies Application Report details a simple method of creating a Bode plot with basic laboratory equipment.
The values of CFF found in Table 8-1 provide a good starting point.
A careful study of the temperature and bias voltage variation of any candidate ceramic capacitor should be made
in order to make sure that the minimum values of effective capacitance are provided. The best way to obtain an
optimum design is to use the Texas Instruments WEBENCH tool.
The maximum value of total output capacitance should be limited to between 100 µF and 200 µF. Large values
of output capacitance can prevent the regulator from starting-up correctly and adversely affect the loop stability.
If values in the range given above, or larger, are to be used, then a careful study of start-up at full load and loop
stability must be performed.
8.2.1.4 Input Capacitors
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying ripple
current and isolating switching noise from other circuits. An effective value of at least 14 µF is normally sufficient
for the input capacitor. If the main input capacitor or capacitors cannot be placed close to the module, then a
small 10 nF to 100 nF capacitor should be placed directly at the module across the supply and ground pins.
Many times, it is desirable to use an electrolytic capacitor on the input, in parallel with the ceramics. This is
especially true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of
this capacitor can help damp any ringing on the input supply caused by long power leads. This method can also
help to reduce voltage spikes that can exceed the maximum input voltage rating of the LMZ20501. The use of
this additional capacitor will also help with voltage dips caused by input supplies with unusually high impedance.
Most of the switching current passes through the input ceramic capacitor or capacitors. The approximate RMS
value of this current can be calculated with Equation 2 and should be checked against the manufactures
maximum ratings.
I RMS |
I OUT
2
(2)
8.2.1.5 Maximum Ambient Temperature
As with any power conversion device, the LMZ20501 will dissipate internal power while operating. The effect
of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature is a function of the ambient temperature, the power loss, and the effective thermal resistance
RθJA of the device and PCB combination. The maximum internal die temperature for the LMZ20501 is 125°C,
thus establishing a limit on the maximum device power dissipation and, therefore, load current at high ambient
temperatures. Equation 3 shows the relationships between the important parameters.
I OUT
TJ TA
˜
R -$
1
˜
1
VOUT
(3)
It is easy to see that larger ambient temperatures and larger values of RθJA will reduce the maximum available
output current. As stated in the Semiconductor and IC Package Thermal Metrics Application Report, the values
given in the Thermal Information table are not valid for design purposes and must not be used to estimate the
thermal performance of the application. The values reported in that table were measured under a specific set of
conditions that never obtain in an actual application. The effective RθJA is a critical parameter and depends on
many factors such as the following:
• Power dissipation
18
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•
•
•
•
•
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Air temperature
PCB area
Copper heatsink area
Air flow
Adjacent component placement
The resources found in Table 11-1 can be used as a guide to estimate the RθJA for a given application
environment. A typical example of RθJA versus copper board area is shown in Figure 8-3. The copper area
in this graph is that for each layer; the inner layers are 1 oz (35µm). An RθJA of 44°C/W is the approximate
value for the LMZ20501 evaluation board. The efficiency found in Equation 3, η, should be taken at the elevated
ambient temperature. For the LMZ20501, the efficiency is approximately two to three percent lower at high
temperatures. Therefore, a slightly lower value than the typical efficiency can be used in the calculation. In this
way, Equation 3 can be used to estimate the maximum output current for a given ambient, or to estimate the
maximum ambient for a given load current.
A typical curve of maximum load current versus ambient temperature is shown in Figure 8-4. This graph
assumes a RθJA of 44°C/W and an input voltage of 5 V.
Thermal Resistance J-A (°C/W)
100
2-LAYER 70 µm (2 oz) Cu
4-LAYER 70 µm (2 oz) Cu
90
80
70
60
50
40
30
20
0
5
10
Copper Area (cm2)
15
20
D012
Figure 8-3. RθJA Versus Copper Board Area
1.2
Output Current (A)
1.0
0.8
0.6
0.4
1.2V
1.8V
3.3V
0.2
0.0
40
50
60
70
80
90
100 110 120 130 140
Ambient Temperature (C)
C001
Figure 8-4. Maximum Output Current Versus Ambient Temperature, RθJA = 44°C/W, VIN = 5 V
8.2.1.6 Options
The circuit in Figure 8-2 highlights the use of the features of the LMZ20501. The PG output is open drain, and
requires a pullup resistor to a logic supply that is commensurate with the system logic voltage levels. If a reset
function is not needed, the PG pin should be left open. The EN and MODE inputs are digital inputs, requiring
only simple logic levels for proper operation. If the system does not need to control these features, the inputs
should be connected to either VIN or GND, as appropriate. See Section 7.3 for details.
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8.2.2 Application Curves
The following specifications apply to the circuit found in Figure 8-1 or Figure 8-2 with the appropriate modifications from Table
8-1. These parameters are not tested and represent typical performance only. Unless otherwise stated the following
conditions apply: TA = 25°C.
100
3V
4.2V
5V
90
80
Efficiency (%)
70
Output Voltage
50mV/div
60
50
40
30
Output Current
0.5A/div
20
10
0
0.01
0.1
1
10
Output Current (A)
VOUT = 1.8 V
VIN = 4.2 V
Figure 8-6. Load Transient In PWM
Figure 8-5. Efficiency
1.812
Output Voltage (V)
20µs/div
C003
VOUT = 1.8 V
3V
4.2V
5V
1.807
Output Voltage
50mV/div
1.802
1.797
Output Current
0.5A/div
1.792
0.0
0.2
0.4
0.6
0.8
1.0
Output Current (A)
1.2
20µs/div
C002
VOUT = 1.8 V
VOUT = 1.8 V
VIN = 4.2 V
Figure 8-8. Load Transient In AUTO Mode
Figure 8-7. Regulation, AUTO Mode
0.35
EN
0.30
Output Current (A)
PWM
0.25
Output Voltage
1V/div
PFM
0.20
0.15
PG
0.10
Input Current
0.2A/div
0.05
0.00
2.5
3.0
3.5
4.0
4.5
5.0
Input Voltage (V)
5.5
C002
500µs/div
VOUT = 1.8 V
Figure 8-9. AUTO Mode Thresholds
VOUT = 1.8 V
VIN = 5 V
IOUT = 1 A
Figure 8-10. Start-Up
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100
3V
4.2V
5V
95
90
Efficiency (%)
85
80
Output Voltage
50mV/div
75
70
65
60
55
Output Current
0.5A/div
50
45
40
0.01
0.1
1
10
Output Current (A)
20µs/div
C004
VOUT = 1.2 V
VOUT = 1.2 V
Figure 8-12. Load Transients In PWM
Figure 8-11. Efficiency
1.204
3V
4.2V
5V
1.203
1.202
Output Voltage (V)
VIN = 4.2 V
1.201
Output Voltage
50mV/div
1.200
1.199
1.198
Output Current
0.5A/div
1.197
1.196
1.195
0.0
0.2
0.4
0.6
0.8
1.0
Output Current (A)
1.2
20µs/div
C005
VOUT = 1.2 V
VOUT = 1.2 V
VIN = 4.2 V
Figure 8-14. Load Transients In AUTO Mode
Figure 8-13. Regulation, AUTO Mode
0.30
EN
Output Current (A)
0.25
0.20
Output Voltage
1V/div
0.15
PG
PWM
0.10
PFM
Input Current
0.2A/div
0.05
0.00
2.5
3.0
3.5
4.0
4.5
5.0
Input Voltage (V)
5.5
500µs/div
C002
VOUT = 1.2 V
VOUT = 1.2 V
Figure 8-15. AUTO Mode Thresholds
VIN = 5 V
IOUT = 1 A
Figure 8-16. Start-Up
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100
4.2V
95
5V
90
Efficiency (%)
85
Output Voltage
50mV/div
80
75
70
65
60
Output Current
0.5A/div
55
50
45
40
0.01
0.1
1
10
Output Current (A)
VOUT = 3.3 V
VOUT = 3.3 V
VIN = 5 V
Figure 8-18. Load Transients In PWM Mode
Figure 8-17. Efficiency
3.270
4.2V
3.265
5V
3.260
Output Voltage (V)
50µs/div
C006
Output Voltage
50mV/div
3.255
3.250
3.245
Output Current
0.5A/div
3.240
3.235
3.230
0.0
0.2
0.4
0.6
0.8
1.0
Output Current (A)
1.2
50µs/div
C007
VOUT = 3.3 V
VOUT = 3.3 V
VIN = 5 V
Figure 8-20. Load Transients In AUTO Mode
Figure 8-19. Regulation, AUTO Mode
0.35
EN
0.30
Output Current (A)
PWM
0.25
Output Voltage
2V/div
0.20
PFM
0.15
PG
0.10
Input Current
0.5A/div
0.05
0.00
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
C009
500µs/div
VOUT = 3.3 V
Figure 8-21. AUTO Mode Thresholds
VOUT = 3.3 V
VIN = 5 V
IOUT = 1 A
Figure 8-22. Start-Up
space
space
space
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8.3 Do's and Don'ts
•
•
•
•
•
•
•
•
•
Don't: Exceed the Absolute Maximum Ratings.
Don't: Exceed the ESD Ratings.
Don't: Exceed the Recommended Operating Conditions.
Don't: Allow the EN or MODE input to float.
Don't: Allow the voltage on the EN or MODE input to exceed the voltage on the VIN pin.
Don't: Allow the output voltage to exceed the input voltage.
Don't: Use the thermal data given in the Thermal Information table to design your application.
Do: Follow all of the guidelines and suggestions found in this data sheet before committing your design to
production. TI Application Engineers are ready to help critique your design and PCB layout to help make your
project a success.
Do: Refer to the helpful documents found in Table 11-1 and Table 11-2
.
9 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and
Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable
of delivering the required input current to the loaded regulator. The average input current can be estimated with
Equation 4
I IN
VOUT ˜ I OUT
VIN ˜
(4)
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low ESR ceramic input
capacitors, can form an under-damped resonant circuit. This circuit can cause overvoltage transients at the VIN
pin, each time the input supply is cycled on and off. The parasitic resistance will cause the voltage at the VIN
pin to dip when the load on the regulator is switched on, or exhibits a transient. If the regulator is operating
close to the minimum input voltage, this dip can cause the device to shutdown, reset, or both. The best way to
solve these kinds of issues is to reduce the distance from the input supply to the regulator, use an aluminum or
tantalum input capacitor in parallel with the ceramics, or both. The moderate ESR of these types of capacitors
will help to damp the input resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to
100 µF is usually sufficient to provide input damping and help to hold the input voltage steady during large load
transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator module. This can lead
to instability, as well as some of the effects mentioned above, unless it is designed carefully. The following user
guide provides helpful suggestions when designing an input filter for any switching regulator: AN-2162 Simple
Success With Conducted EMI From DC-DC Converters Application Report.
In some cases, a Transient Voltage Suppressor (TVS) is used on the input of regulators. One class of this device
has a "snap-back" V-I characteristic (thyristor type). The use of a device with this type of characteristic is not
recommend. When the TVS "fires", the clamping voltage drops to a very low value. If this holding voltage is less
than the output voltage of the regulator, the output capacitors will be discharged through the regulator back to
the input. This uncontrolled current flow could damage the regulator.
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10 Layout
10.1 Layout Guidelines
The PCB layout of any DC-DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter, the
most critical PCB feature is the loop formed by the input capacitor and the module ground, as shown in Figure
10-1. This loop carries fast transient currents that can cause large transient voltages when reacting with the
trace inductance. These unwanted transient voltages will disrupt the proper operation of the converter. Because
of this, the traces in this loop should be wide and short, and the loop area as small as possible to reduce the
parasitic inductance. Figure 10-2 shows a recommended layout for the critical components of the LMZ20501;
the top side metal is shown in red. This PCB layout is a good guide for any specific application. The following
important guidelines should also be followed:
1. Place the input capacitor CIN as close as possible to the VIN and GND terminals. VIN (pin 8) and GND
(pin 6) are on the same side of the module, simplifying the input capacitor placement.
2. Place the feedback divider as close as possible to the FB pin on the module. The divider and CFF
should be close to the module, while the length of the trace from VOUT to the divider can be somewhat
longer. However, this latter trace should not be routed near any noise sources that can capacitively couple to
the FB input.
3. Connect the EP pad to the GND plane. This pad acts as a heat-sink connection and a ground connection
for the module. It must be solidly connected to a ground plane. The integrity of this connection has a direct
bearing on the effective RθJA.
4. Provide enough PCB area for proper heat-sinking. As stated in Section 8.2.1.5, enough copper
area must be used to provide a low RθJA, commensurate with the maximum load current and ambient
temperature. The top and bottom PCB layers should be made with two ounce copper; and no less than one
ounce.
5. The resources in Table 11-2 provide additional important guidelines.
VIN
CIN
GND
Figure 10-1. Current Loops With Fast Transient Currents
24
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10.2 Layout Example
GND
HEATSINK
TOP
VIEW
VIN
CIN
GND
EP
COUT
VOUT
CFF
RFBB
GND
HEATSINK
RFBT
Top Trace
Bottom Trace
Figure 10-2. Example PCB Layout
10.2.1 Soldering Information
Proper operation of the LMZ20501 requires that it be correctly soldered to the PCB. This is especially true
regarding the EP. This pad acts as a quiet ground reference for the device and a heatsink connection. Use the
following recommendations when utilizing machine placement of the device:
•
•
•
•
•
•
•
Dimension of area for pickup: 2 mm × 2.5 mm
Use a nozzle size of less than 1.3 mm in diameter, so that the head does not touch the outer area of the
package.
Use a soft tip pick-and-place head.
Add 0.05 mm to the component thickness so that the device will be released 0.05 mm into the solder paste
without putting pressure or splashing the solder paste.
Slow the pick arm when picking the part from the tape and reel carrier and when depositing the device on the
board.
If the machine releases the component by force, use the minimum force and no more than 3 N.
For PCBs with surface mount components on both sides, it is suggested to put the LMZ20501 on the top
side. In case the application requires bottom side placement, a re-flow fixture can be required to protect the
module during the second reflow.
In addition, please follow the important guidelines found in the AN-1187 Leadless Leadframe Package (LLP)
Application Report. The curves in Figure 10-3 and Figure 10-4 show typical soldering temperature profiles.
Figure 10-3. Typical Re-flow Profile Eutectic (63sn/37pb) Solder Paste
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Figure 10-4. Typical Re-flow Profile Lead-Free (Sca305 Or Sac405) Solder Paste
26
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ20501 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Table 11-1. Resources For Estimating RθJA
TITLE
LINK
AN-2020 Thermal Design By Insight, Not
Hindsight
SNVA419
AN-2026 The Effect of PCB Design
on the Thermal Performance of SIMPLE
SWITCHER Power Modules
SNVA424
AN-1520 A Guide to Board Layout for Best
Thermal Resistance for Exposed Packages
SNVA183
AN-1187 Leadless Lead-frame Package
(LLP)
SNOA401
SPRA953B Semiconductor and IC Package
Thermal Metrics
SPRA953
Table 11-2. PCB Layout Resources
TITLE
LINK
AN-1149 Layout Guidelines for Switching
Power Supplies
SNVA021
AN-1229 SIMPLE SWITCHER PCB Layout
Guidelines
SNVA054
Constructing Your Power Supply- Layout
Considerations
SLUP230
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11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® and WebTherm® are registered trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
28
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LMZ20501SILR
uSiP
SIL
8
3000
330.0
12.4
3.75
3.75
2.2
8.0
12.0
Q2
LMZ20501SILT
uSiP
SIL
8
250
178.0
13.2
3.75
3.75
2.2
8.0
12.0
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
30
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ20501SILR
uSiP
SIL
8
3000
383.0
353.0
58.0
LMZ20501SILT
uSiP
SIL
8
250
223.0
194.0
35.0
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PACKAGE OPTION ADDENDUM
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30-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
LMZ20501SILR
ACTIVE
uSiP
SIL
8
3000
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 125
1501 7543 EB
LMZ20501SILT
ACTIVE
uSiP
SIL
8
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 125
1501 7543 EB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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