LMZ30606EVM-003

LMZ30604EVM-001, LMZ30604EVM-002, and LMZ30606EVM-003 User's Guide Literature Number: SNVU296A July 2013 – Revised March 2014 User's Guide SNVU296A – July 2013 – Revised March 2014 LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module The LMZ30604EVM-001, LMZ30602EVM-002, and LMZ30606 evaluation modules (LMZ3060xEVM-00x) are designed as an easy-to-use platform that facilitates an extensive evaluation of the features and performance of the Simple Switcher power module. The EVM PCB may be configured with one of three devices (see Table 1). 1 Introduction This user's guide provides information on the correct usage of the EVM and an explanation of the numerous test points on the board. Table 1. LMZ3060xEVM-00x Device Configuration 2 DEVICE TITLE LMZ30602 2.95 to 6-V input, 2-A output sync, step-down converter with PWM LMZ30604 2.95 to 6-V input, 4-A output sync, step-down converter with PWM LMZ30604 2.95 to 6-V input, 6-A output sync, step-down converter with PWM Description The EVM features a LMZ3060x synchronous buck power module configured for operation with typical 3.3and 5-V input bus applications. The output voltage can be set to one of five popular values by using a simple configuration jumper. In similar fashion, the switching frequency can be set to one of four values by use of a jumper. The full rated output current can be supplied by the EVM. A minimal amount of input and output capacitance is used on the board. Component pads are provided for additional input and output capacitors if desired. Monitoring test points are provided to allow measurement of efficiency, power dissipation, input ripple, output ripple, line and load regulation, and transient response. Control test points are provided for use of the PWRGD, Inhibit/UVLO, synchronization, and slow-start/tracking features of the device. The EVM uses a recommended PCB layout that maximizes thermal performance and minimizes output ripple and noise. 2 LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module Copyright © 2013–2014, Texas Instruments Incorporated SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback Getting Started www.ti.com 3 Getting Started Figure 1 highlights the user interface items associated with the EVM. The polarized VIN Power terminal block is used for connection to the host input supply and the polarized VOUT Power terminal block is used for connection to the load. The terminal blocks can except up to 16 AWG wire. The VIN monitor and VOUT monitor test points located near the power terminal blocks are intended to be used as voltage monitoring points where voltmeters can be connected to measure VIN and VOUT. The voltmeter references should be connected to any of the four VIN/VOUT monitor grounds test points located between the power terminal blocks. Do not use these VIN and VOUT monitoring test points as the input supply or output load connection points. The PCB traces connecting to these test points are not designed to support high currents. Figure 1. LMZ3060xEVM-00x User Interface The VIN scope and VOUT scope test points can be used to monitor VIN and VOUT waveforms with an oscilloscope. These test points are intended for use with un-hooded scope probes. The scope probe tip should be connected to the socket labeled VIN or VOUT, and the scope ground barrel should lean against to the test point labeled GND. The GND TP may need to be cut or bent slightly to hold the probe barrel. Metal Ground Barrel Probe Tip TP15 TP16 Figure 2. Tip and Barrel Measurement The control test points located directly below the LMZ3060x device are made available to test the features of the device. Any external connections made to these test points should be referenced to either of the two control ground test points located along the bottom of the EVM. Refer to Section 4 of this user guide for more information on the individual control test points. SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module Copyright © 2013–2014, Texas Instruments Incorporated 3 Test Point Descriptions www.ti.com The VOUT-select and FSW-select configuration jumpers are provided for selecting the desired output voltage and appropriate switching frequency. Before applying power to the EVM, ensure that the jumpers are present and properly positioned for the intended output voltage. Refer to Table 2 for the recommended jumper settings. Always remove input power before changing the jumper settings. Once the jumper settings have been confirmed, configure the host input supply to apply the appropriate bus voltage listed in Table 2 and confirm that the selected output voltage is obtained. Table 2. Output Voltage and Switching Frequency Jumper Settings 4 VOUT SELECT LMZ30602, FSW SELECT LMZ30604, FSW SELECT LMZ30606, FSW SELECT VIN BUS VOLTAGE 3.3 V 1.5 MHz 1 MHz 1 MHz 5V 2.5 V 1.5 MHz 1 MHz 1 MHz 5V 1.8 V 1 MHz 1 MHz 1 MHz 5 V or 3.3 V 1.2 V 750 kHz 750 kHz 750 kHz 5 V or 3.3 V 0.8 V 650 kHz 650 kHz 650 kHz 5 V or 3.3 V Test Point Descriptions Fourteen wire-loop test points have been provided as convenient connection points for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. A via labled PH is available near U1 to scope on the switching frequency. A description of each test point is listed in Table 3 Table 3. Test Point Descriptions TEST POINT VIN Input voltage monitor. Connect DVM to this point for measuring efficiency. VOUT Output voltage monitor. Connect DVM to this point for measuring efficiency, line regulation, and load regulation. GND Input and output voltage monitor grounds (located between terminal blocks). Reference the above DVMs to any of these four ground points. VIN (scope) Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple voltage. VOUT (scope) Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output ripple voltage and transient response. PWRGD Monitors the power good signal of the device. This is an open drain signal that requires an external pullup resistor to VIN if monitoring is desired. A 10-kΩ to 100-kΩ pullup resistor is recommended. PWRGD is high if the output voltage is within 92% to 106% of its nominal value. INH/UVLO Connect this point to control ground to inhibit the device. Allow this point to float to enable the device. Do not use a pull-up resistor. An external resistor can be connected from this point to control ground to increase the under-voltage lockout (UVLO) of the device. RT/CLK SS/TR GND 4 DESCRIPTION Connects to the RT/CLK pin of the device. An external clock signal can be applied to this point to synchronize the device to an appropriate frequency. Connects to the internal slow-start capacitor of the device. An external capacitor can be connected from this point to control ground to increase the slow-start time of the device. This point can also be used as an input for tracking applications. Control grounds (located along bottom of EVM). Reference any signals associated with the control test points to either of these two ground points. LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module Copyright © 2013–2014, Texas Instruments Incorporated SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback Operation Notes www.ti.com 5 Operation Notes The UVLO threshold of the factory-stock EVM is approximately 3.05 V with 0.3 V of hysteresis. The input voltage must be above the UVLO threshold in order to startup the device. The UVLO threshold can be increased by adding a resistor to the INH/UVLO test point as described in Table 3. After startup, the minimum input voltage to the device must be at least 2.95 V or (VOUT + 1.1 V), whichever is greater, in order to produce a regulated output. The maximum operating input voltage for the device is 6 V. For further information on the input voltage range and UVLO operation, refer to the device data sheet. After application of the proper input voltage, the output voltage of the device will ramp to its final value in approximately 1 ms. If desired, this soft-start time can be increased by adding a capacitor to the SS/TR test point as described above. Refer to the device datasheet for further information on adjusting the softstart time. Table 1 lists the recommended switching frequencies for each of the VOUT selections. These recommendations cover operation over a wide range of input voltage and output load conditions. Several factors such as duty cycle, minimum on-time, minimum off-time, and current limit influence selection of the appropriate switching frequency. In some applications, other switching frequencies might be used for particular output voltages, depending on the above factors. For further information on switching frequency selection, including synchronization, refer to the device data sheet. SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module Copyright © 2013–2014, Texas Instruments Incorporated 5 LMZ3060xEVM-00x Schematic 6 www.ti.com LMZ3060xEVM-00x Schematic VIN TP1 TP14 2 1 VIN GND + TB1 C7 C5 C3 C1 220 μF 0.1 μF 0.1 μF 47 μF 1 U1 LMZ3060xRKG 1 PH 1 3.0 to 5.5 VIN 2 3 SS/TR 4 TP12 5 6 7 1 1 C9 8 C10 0.01 μF 9 0.01 μF 10 11 12 13 RT/CLK 14 15 TP8 16 17 1 R14 113 kΩ R13 174 kΩ R7 348 kΩ R8 715 kΩ R9 1.2 MΩ 18 R2 100 kΩ 19 J1 2 MHz 1.5 MHz 1 MHz 750 kHz 650 kHz COMPRTN VOUT RC PGND COMP SENSE+ RT/CLK VADJ RTRTN AGND SS/TR AGND STSEL VIN VOUT VIN VOUT VIN VOUT INHRTN VOUT INH/UVLO VOUT PWRGD VOUT BOOT VOUT PH DNC PH DNC PH PH PH PH PH PH PH 39 38 37 36 35 34 33 R3 2.87 kΩ 32 R4 1.15 kΩ R5 681 Ω R6 464 Ω J2 31 1 2 3 4 5 6 7 8 9 10 1 30 R1 100 kΩ 29 TP10 28 1 R12 100 kΩ 27 R11 100 kΩ 1 26 25 24 3.3 2.5 1.8 1.2 0.8 V V V V V Output Select 23 TP11 22 2 21 R10 0Ω 20 PH 1 2 3 4 5 6 7 8 9 10 TP13 TP2 TP7 TB2 C2 47 μF NOTES: TP3 TP4 TP5 TP6 C8 C6 + C4+ 1 VOUT 2 220 μF 0.1 μF 1 1 100uF GND TP9 1 2 Not Populated Connect AGND to PGND directly at U1-37 on Layer 1 0.8 to 3.3 VOUT Figure 3. LMZ3060xEVM-00x Schematic 6 LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated PCB Layouts www.ti.com 7 PCB Layouts Figure 4. Top Layer Figure 5. Internal Layer 1 SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module Copyright © 2013–2014, Texas Instruments Incorporated 7 PCB Layouts www.ti.com Figure 6. Internal Layer 2 Figure 7. Bottom Layer 8 LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module Copyright © 2013–2014, Texas Instruments Incorporated SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback PCB Layouts www.ti.com Figure 8. Top Assembly Figure 9. Bottom Layer SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module Copyright © 2013–2014, Texas Instruments Incorporated 9 Bill of Materials 8 www.ti.com Bill of Materials Table 4. LMZ3060xEVM-00x Bill of Materials -003 -002 -001 REF DES 1 1 1 C1 Capacitor, ceramic, 10 V, x5R, 10%, 47 µF, 1210 GRM32ER61A476K Murata 1 1 1 C2 Capacitor, ceramic, 6.3 V, x5R, 20%, 47 µF, 1210 GRM32ER60J476M Murata 1 1 1 C7 Capacitor, polymer, 10 V, 20%, 220 µF, D3L 10TPE220ML Sanyo 0 0 0 C8 Capacitor, polymer, 10 V, 20%, 220 µF, D3L 10TPE220ML Sanyo 1 1 1 C4 Capacitor, polymer, 6.3 V, 20%, 100 µF, B2 6TPE100MPB Sanyo 0 0 0 C3, C5, C6 Capacitor, ceramic, 0.1 µF, 1210 Std STD 0 0 0 10 Capacitor, ceramic, 0.01 µF, 0402 STD STD Part Number MFR Header, male 2 x 5 pin, 100-mil spacing, 0.100 inch x 5 PEC05DAAN inch x 2 inch Sullins 2 2 2 J1-2 1 1 1 R3 Resistor, chip, 1/16 W, 1%, 2.87 kΩ, 0603 STD STD 1 1 1 R4 Resistor, chip, 1/16 W, 1%, 1.15 kΩ, 0603 STD STD 1 1 1 R5 Resistor, chip, 1/16 W, 1%, 681 Ω, 0603 STD STD 1 1 1 R6 Resistor, chip, 1/16 W, 1%, 464 Ω, 0603 STD STD 1 1 1 R7 Resistor, chip, 1/16 W, 1%, 348 kΩ, 0603 STD STD 1 1 1 R8 Resistor, chip, 1/16 W, 1%, 715 kΩ, 0603 STD STD 1 1 1 R9 Resistor, chip, 1/16 W, 1%, 1.2 MΩ, 0603 STD STD 1 1 1 R10 Resistor, chip, 1/16 W, 5%, 0 Ω, 0603 STD STD 1 1 1 R13 Resistor, chip, 1/16 W, 1%, 174 kΩ, 0603 STD STD 1 1 1 R14 Resistor, chip, 1/16 W, 1%, 113 kΩ, 0603 STD STD 0 0 0 R1, R2, R11, R12 Resistor, chip, 1/16 W, 1%, 100 kΩ, 0402 Std Std ED120/2DS OST 2 2 2 TB1-2 Terminal block, 2 pin, 15 A, 5.1 mm, 0.40 inch x 0.35 inch 8 8 8 TP1, TP2 TP8 TP10- TP14 Test point, white, thru hole, 5012, 0.125 inch x 0.125 inch 5012 Keystone 6 6 6 TP3-7 TP9 Test point, black, thru hole, 5011, 0.125 inch x 0.125 inch 5011 Keystone 0 0 1 U1 6-V input, 4-A Output Sync. Step-Down Converter with PWM, QFN LMZ30604RKG TI 0 1 0 U1 6-V input, 2-A Output Sync. Step-Down Converter with PWM, QFN LMZ30604RKG TI 1 0 0 U1 6-V input, 6-A Output Sync. Step-Down Converter with PWM, QFN LMZ30604RKG TI 1 1 1 PCB, 0.063 inch H x 1.9 inch L x 3.9 inch W PWR059 ANY 2 2 2 Conn jumper shorting gold flash SPC02SYAN Sullins 4 Bumpon hemisphere 0.44 inch x 0.20 inch clear, 0.440 inch Dia x 0.200 inch H SJ-5303 3M 4 10 DESCRIPTION 4 LMZ3060xEVM-00x 2- to 6-A Simple Switcher Power Module Copyright © 2013–2014, Texas Instruments Incorporated SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback Revision History www.ti.com Revision History Changes from Original (July 2013) to A Revision ........................................................................................................... Page • Updated Figure 3 ......................................................................................................................... 6 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SNVU296A – July 2013 – Revised March 2014 Submit Documentation Feedback Revision History Copyright © 2013–2014, Texas Instruments Incorporated 11 ADDITIONAL TERMS AND CONDITIONS, WARNINGS, RESTRICTIONS, AND DISCLAIMERS FOR EVALUATION MODULES Texas Instruments Incorporated (TI) markets, sells, and loans all evaluation boards, kits, and/or modules (EVMs) pursuant to, and user expressly acknowledges, represents, and agrees, and takes sole responsibility and risk with respect to, the following: 1. User agrees and acknowledges that EVMs are intended to be handled and used for feasibility evaluation only in laboratory and/or development environments. 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