LMZ31710X2EVM

www.ti.com Table of Contents User’s Guide LMZ31704 2-Phase Power Module Evaluation Module User's Guide ABSTRACT The LMZ31710 device is a 2.95-V to 17-V input, 10-A output, SIMPLE SWITCHER® power module, which integrates the PWM controller, power MOSFETs, shielded inductor, and passives in a low-profile, QFN package. For applications requiring greater than 10 A, it is possible to parallel up to six LMZ31710 devices. This user's guide provides information on the correct usage of the test board and an explanation of the test points and jumpers on the board. Table of Contents 1 Description.............................................................................................................................................................................. 2 2 Getting Started........................................................................................................................................................................2 3 Test Point Descriptions.......................................................................................................................................................... 4 4 Operation Notes......................................................................................................................................................................5 5 Current Limitations.................................................................................................................................................................6 6 Performance Data................................................................................................................................................................... 7 7 2× Parallel Bill of Material.................................................................................................................................................... 12 8 2× Parallel Schematic........................................................................................................................................................... 13 9 4× Parallel Bill of Material.................................................................................................................................................... 15 10 4× Parallel Schematic......................................................................................................................................................... 16 11 Revision History..................................................................................................................................................................18 SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 LMZ31704 2-Phase Power Module Evaluation Module User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated 1 Description www.ti.com 1 Description This test board features the LMZ31710 device configured for parallel operation. The test board operates over the entire input voltage range of the LMZ31710 device (2.95 to 17 V) with the option to select a split input power rail. The output voltage can be set to one of four popular values by using a configuration jumper (P4). This board can be configured to accept an external clock to set the switching frequency. Using a jumper, each paralleled LMZ31710 device can be configured to operate in phase with the controller or 180° out-of-phase. Input and output capacitors are included on the board to accommodate the entire range of input and output voltages. Current monitoring test points are available to measure the current of each device. Monitoring test points are provided to allow measurement of the following: • • • • • • Efficiency Power dissipation Input ripple Output ripple Line and load regulation Transient response Control test points are provided to use the PWRGD, inhibit/UVLO, synchronization (CLK_IN), and slow-start or tracking features. 2 Getting Started Figure 2-1 and Figure 2-2 highlight the user interface items associated with both the 2× and 4× LMZ31710 parallel test board. The polarized PVIN power terminal blocks are used to connect to the host input supply, and the polarized VOUT power terminal blocks are used to connect to the load. These terminal blocks can accept up to 16 AWG wire. The polarized VBIAS terminal block is used along with the VIN SELECT jumper (P1) when optional split power supply operation is desired. Refer to the LMZ31710 10-A Module, 2.95-V to 17-V Input and Current Sharing in QFN Package data sheet for further information on split power supply operation. Refer to Table 2-1 for terminal block numbering for either the 2× or 4× LMZ31710 parallel test board. PVIN Monitor VIN Selector PVIN Power + - Current Monitors VOUT Power - + VOUT Monitor VOUT Scope C O N T R O LS VIN (VBIAS) Input PVIN Scope Clock Phase Selector VOUT Selector Figure 2-1. 2× LMZ31710 Test Board User Interface 2 LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Getting Started PVIN Monitor PVIN Power + - VOUT - Power + - PVIN Scope VOUT Monitor + VOUT Scope VIN Selector Current Monitors VIN (VBIAS) Input C O N T R O L S Clock Phase Selectors VOUT Selector Figure 2-2. 4× LMZ31710 Test Board User Interface Table 2-1. Terminal Block Numbering Function 2× LMZ31710 4× LMZ31710 PVIN Power TB1 TB1 PGND (Input) TB2 TB2 PGND (Output) TB3 TB3, TB4 VOUT Power TB4 TB5, TB6 VBIAS Input TB5 TB7 The PVIN monitor and VOUT monitor test points located near the power terminal blocks are intended as voltage monitoring points where digital voltmeters can connect to measure PVIN and VOUT. CAUTION Do not use these PVIN and VOUT monitoring test points as the input supply or output load connection points. The PCB traces connecting to these test points are not designed to support high currents. High currents can damage the PCB traces. The PVIN Scope and VOUT Scope test points can be used to monitor PVIN and VOUT waveforms with an oscilloscope. These test points are intended for use with un-hooded scope probes outfitted with a low-inductance ground lead (ground spring) mounted to the scope barrel. The two sockets of each test point are on 0.1-inch centers. The scope probe tip should be connected to the socket labeled PVIN, or VOUT, and the scope ground lead should be connected to the socket labeled PGND. The current monitor test points located above each LMZ31710 device are intended to be used with digital voltmeters to monitor the current across a 1-mΩ sense resistor located on the bottom of the board. The controls test points located on the perimeter of the board are made available to test the features of the device. Any external connections made to these test points should be referenced to an AGND test point. Refer to Section 3 for more information on the individual control test points. SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 LMZ31704 2-Phase Power Module Evaluation Module User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated 3 Test Point Descriptions www.ti.com The VOUT SELECT jumper (P4) is provided for selecting the desired output voltage. Before applying power to the test board, ensure that the jumper is present and properly positioned for the intended output voltage. Always remove input power before changing the jumper settings. 3 Test Point Descriptions Wire-loop test points and scope probe test points have been provided as convenient connection points for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the test board. Table 3-1 provides a description of each test point. Table 3-1. Test Point Descriptions Test Point Description AGND Control and monitor grounds. Reference the DVMs and any signals associated with the control test points to any of the analog ground points. CLK_IN INH/UVLO PVIN PVIN Scope (P2) PWRGD 4 Connects to the RT/CLK pin of the LMZ31710 devices. An external clock signal can be applied to this point to synchronize the devices to an appropriate frequency. Connect this point to control ground to inhibit the LMZ31710 devices. Allow this point to float to enable the device. An external resistor divider (R3 and R4) can be connected between this point, control ground, and PVIN to adjust the undervoltage lockout of the device. Input voltage monitor. Connect the DVM to this point to measure efficiency. Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple voltage. Monitors the power good signal of the LMZ31710. This is an open-drain signal that requires an external pullup resistor if monitoring is desired. TI recommends a 10-kΩ to 100-kΩ pullup resistor. PWRGD PULL_UP Power-good pullup voltage connection point. Connect an external voltage (< 6 V) to this pin to supply a voltage for the PWRGD signal. A 100-kΩ pullup resistor is located on the bottom-side of the board. SS/TR Connects to the slow-start connection of the LMZ31710 devices. An external capacitor can be connected from this point to control ground to increase the slow-start time of the devices. This point can also be used as an input for tracking applications. SYNC_OUT This output provides a clock signal that is 180° out of phase with the PH node of the LMZ31710 device and can be used to synchronize other devices. VOUT Output voltage monitor. Connect DVM to this point for measuring efficiency, line regulation, and load regulation. VOUT Scope (P3) Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output ripple voltage and transient response. LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Operation Notes 4 Operation Notes To operate the test board using a single power supply, the VIN SELECT jumper (P1) must be in the default PVIN-VIN position as shown in Figure 2-1 and Figure 2-2. In this position, the PVIN and VIN pins of the LMZ31710 devices are connected together. When connected together the input voltage range is 4.5 to 17 V. Refer to the LMZ31710 10-A Module, 2.95-V to 17-V Input and Current Sharing in QFN Package data sheet for further information on the input voltage range, UVLO operation, and optional split power supply operation when using an external Vbias supply. After a valid input voltage is present, the output voltage ramps to the selected value in approximately 1.2 ms. The soft-start time can be increased by adding a SS capacitor to the C12 position on the bottom of the test board. Refer to the LMZ31710 10-A Module, 2.95-V to 17-V Input and Current Sharing in QFN Package data sheet for further information on adjusting the soft-start time. All LMZ31710 devices on the test board must be synchronized to the same frequency. This can be accomplished by either applying an external clock signal to the CLK_IN test point and running the clock to each device, or by setting the frequency of the controller device using the RRT resistor (R2) and running the Sync_Out signal to the remaining target devices. The Clock Phase Selector for each device is used to select either the external clock or the Sync_Out clock signal. The Sync_Out signal is a clock signal that is the same as the switching frequency, but is 180° out of phase. The test boards are set-up to operate at a free-running frequency of 300 kHz. To change the free-running switching frequency, the value of R2 can be changed according to the LMZ31710 10-A Module, 2.95-V to 17-V Input and Current Sharing in QFN Package data sheet. Table 4-1 lists the switching frequency ranges for each of the VOUT selections. Several factors such as duty cycle, minimum on-time, minimum off-time, and current limit influence selection of the switching frequency. Table 4-1. Switching Frequency Range Frequency Range VOUT (V) PVIN = 12 V PVIN = 5 V 0.6 200 to 250 kHz 200 to 550 kHz 0.9 200 to 300 kHz 200 to 800 kHz 1.2 200 to 450 kHz 200 to 1000 kHz 1.8 300 to 600 kHz 300 to 1200 kHz SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 LMZ31704 2-Phase Power Module Evaluation Module User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated 5 Current Limitations www.ti.com 5 Current Limitations When operating LMZ31710 devices in parallel, the maximum output current the solution can provide must be calculated using Equation 1. Due to internal variances between devices, the amount of output current must be de-rated to ensure none of the devices operate above the maximum output current of a single device (10 A). See Figure 5-1 for typical current balancing between four LMZ31710 devices. IOUTmax = 0.9 × (n × 10) (A) (1) where • n is the number of LMZ31710 devices being paralleled. 11 Output Current per Device (A) 10 9 8 7 6 5 4 3 Device1 Device2 Device3 Device4 2 1 0 0 4 8 12 16 20 24 28 32 36 40 Output Current Total (A) C001 Figure 5-1. Typical Current Balancing 6 LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Performance Data 6 Performance Data Figure 6-1. UVLO Start-Up Waveform Figure 6-2. UVLO Shutdown Waveform SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 LMZ31704 2-Phase Power Module Evaluation Module User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated 7 Performance Data www.ti.com Figure 6-3. INH Start-Up Waveform Figure 6-4. INH Shutdown Waveform 8 LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Performance Data Figure 6-5. Output Voltage Ripple – In-Phase Figure 6-6. Output Voltage Ripple – 180° Out-of-Phase SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 LMZ31704 2-Phase Power Module Evaluation Module User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated 9 Performance Data www.ti.com Figure 6-7. Input Voltage Ripple – In-Phase Figure 6-8. Input Voltage Ripple – 180° Out-of-Phase 10 LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com Performance Data Figure 6-9. Transient Response – 10-A Load Step (1 A/µs) SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 LMZ31704 2-Phase Power Module Evaluation Module User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated 11 2× Parallel Bill of Material www.ti.com 7 2× Parallel Bill of Material RefDes Part Type Value C1, C2, C16, C17 C1210 22 µF C4, C5, C6, C7, C8, C18, C19, C20, C21, C22 C1210 100 µF C9, C24 C0805 0.1 µF C10, C25 C0805 4.7 µF C11, C12, C26 C0805 DNL C3 CAP_ALUM_FC-A 220 µF C14, C23 CAP_POSCAP_D 220 µF P1, P5 MALE HEADER_1X3 PEC03SAAN P2, P3 FEMALE HEADER_1X2 SOCKET 2 PIN P4 MALE HEADER_2X4 PEC04DAAN R1 R0402 NOT POPULATED R2, R11 R0402 487 k R3 R0402 68.1 k R4 R0402 24.3 k R5 R0805 NOT POPULATED R6 R0603_1% 2.87 k R7 R0603_1% 1.43 k R8 R0603_1% 715 Ω R9, R10 57-WSL3637 R001R 1% R12 R0603 100 k TB1, TB2, TB3, TB4 TBLK_15A_2X5.1MM ED120/2DS TB5 TBLK_6A_2X3.5MM ED555/2DS TB6 CONN_DC_PJ-102AH PJ-102AH TP6, TP7, TP8, TP10, TP11, TP13 TP-5012-WHITE 5012 TP1, TP2, TP15, TP17 TP-5010-RED 5010 TP3, TP4, TP5, TP9, TP16, TP18 TP-5011-BLACK 5011 TP12, TP14 TP-038 STD U1, U2 LMZ31710RVQ LMZ31710RVQ 12 LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com 2× Parallel Schematic 8 2× Parallel Schematic TP2 VOUT SENSE TP1 PVIN MASTER CURRENT DVM_Monitor PVIN TP15 1.6 V to 17 V 3 TB1 4 PVIN PVIN C3 220 µF 25 V + TB2 VOUT TP16 0.6 V to 1.8 V / 18 A 1 R9 TB4 2 VOUT P2 PVIN PGND C2 22 µF 25 V P3 C9 0.1 µF 25 V C1 22 µF 25 V C4 100 µF C5 100 µF 6.3 V 6.3 V PGND C6 100 µF 6.3 V C7 100 µF 6.3 V C8 100 µF 6.3 V VOUT VOUT + PGND R5 C14 220 µF 10 V TB3 1 PGND PGND PGND TP9 AGND VIN SELECT P1 PGND 4.5 V to 17 V TB5 PVIN 1 VIN 2 VBIAS 3 PGND PVIN VIN R3 68.1 kΩ 21 PGND 20 PGND 31 32 PGND PGND 34 33 PGND VOUT 36 35 VOUT VOUT VOUT 38 37 41 VOUT VOUT 11 40 12 PVIN PVIN PVIN 1 PVIN PGND PVIN PGND 39 VBIAS TP10 INH/UVLO R4 INH/UVLO 24.3 kΩ PWRGD TP6 PULL UP 2 3 R12 100 kΩ PWRGD C10 4.7 µF 25 V AGND 4 5 6 PGND 7 TP11 8 PWRGD 9 10 AGND INH/UVLO VIN STSEL OCP_SEL SS/TR U1 DNC SENSE+ ILIM VADJ SYNC_OUT ISHARE PWRGD DNC AGND DNC PH RT/CLK 30 AGND 29 TP13 SS/TR 28 27 26 VADJ 25 SS/TR C12 ISHARE 1 24 TP3 23 C11 22 R1 TP4 1 SYNC_OUT 1 PH PH AGND 487 kΩ 42 19 PH PH PH 17 18 PH 14 15 16 PH 13 PH R2 TP7 SYNC_OUT AGND AGND TP12 1 PHASE CLK_IN MASTER TP8 CLK_IN VOUT SELECT R8 715 Ω P4 1. Not Populated. 2. This is designed to be a platform for quick customer evaluation of the LMZ31710 product. AGND NOTES: AGND R7 1.43 kΩ 1 1.8 V 2 3 1.2 V 4 5 0.9 V 6 7 0.6 V 8 TP5 AGND R6 2.87 kΩ SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback LMZ31704 2-Phase Power Module Evaluation Module User's Guide Copyright © 2022 Texas Instruments Incorporated 13 2× Parallel Schematic www.ti.com SLAVE CURRENT DVM_Monitor TP17 TP18 3 PVIN 4 C16 22 µF 25 V C18 100 µF 6.3 V C24 0.1 µF 25 V C17 22 µF 25 V C19 100 µF 6.3 V C20 100 µF 6.3 V C21 100 µF 6.3 V 1 R10 VOUT 2 C22 100 µF 6.3 V C23 220 µF 10 V + PGND C25 4.7 µF 25 V 4 AGND 5 6 PGND 7 PWRGD 8 9 10 PGND 20 31 32 21 PGND PGND 33 AGND PGND PGND 35 34 VOUT VOUT 37 36 VOUT VOUT 38 41 VOUT VOUT 12 11 PVIN 39 PVIN PVIN 1 3 PVIN PVIN 2 VIN 40 PGND INH/UVLO VIN STSEL OCP_SEL SS/TR U2 DNC SENSE+ ILIM VADJ SYNC_OUT ISHARE PWRGD DNC AGND DNC PH RT/CLK 30 INH/UVLO 29 28 SS/TR 27 26 VADJ 25 ISHARE 24 C26 23 1 22 CLK_IN P5 AGND PH 2 3 42 PH PH PH 18 19 PH 16 17 PH PH 14 15 13 PH 1 R11 487 kΩ TP14 1 PHASE SYNC_OUT AGND SLAVE NOTES: 1. Not Populated. 2. This is designed to be a platform for quick customer evaluation of the LMZ31710 product. 14 LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com 4× Parallel Bill of Material 9 4× Parallel Bill of Material RefDes Part Type Value C1, C2, C13, C15, C16, C17,C36, C37 C1210 22 µF C4, C5, C6, C7, C8, C18, C19, C20, C21, C22, C27, C28, C29, C34,C35, C38, C39, C40, C45, C46 C1210 100 µF C9, C24, C30, C41 C0805 0.1 µF C10, C25, C31, C42 C0805 4.7 µF C11, C12, C26, C33, C44 C0805 DNL C3, C47 CAP_ALUM_FC-A 220 µF C14, C23, C32, C43 CAP_POSCAP_D 220 µF P1, P5, P6, P7 HEADER_1X3 PEC03SAAN P2, P3 HEADER_1X2 NOT POPULATED P4 HEADER_2X4 PEC04DAAN R1 R0402 NOT POPULATED R2, R11, R12, R14 R0402 487 k R3 R0402 68.1 k R4 R0402 24.3 k R5 R0805 NOT POPULATED R6 R0603_1% 2.87 k R7 R0603_1% 1.43 k R8 R0603_1% 715 Ω R9, R10, R13, R15 57-WSL3637 R001R 1% R16 R0603 100k TB1, TB2, TB3, TB4, TB5, TB6 TBLK_15A_2X5.1MM ED120/2DS TB7 TBLK_6A_2X3.5MM ED555/2DS TP1, TP2, TP15, TP17, TP19, TP23 TP-5010-RED 5010 TP3, TP4, TP5, TP9, TP16, TP18, TP20, TP25 TP-5011-BLACK 5011 TP7, TP8, TP10, TP11, TP13 TP-5012-WHITE 5012 TP6, TP12, TP14, TP22 TP-038 STD U1, U2, U3, U4 LMZ31710RVQ LMZ31710RVQ SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 LMZ31704 2-Phase Power Module Evaluation Module User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated 15 4× Parallel Schematic www.ti.com 10 4× Parallel Schematic TP2 VOUT SENSE TP1 PVIN 1.6 V to 17 V TB1 TP15 PVIN P2 + PGND C47 220 µF 25 V + PVIN C3 220 µF PGND 25 V C2 22 µF 25 V C1 22 µF 25 V C4 100 µF 6.3 V C9 0.1 µF 25 V C5 100 µF 6.3 V C6 100 µF 6.3 V C7 100 µF 6.3 V TB6 VOUT VOUT TP16 3 4 PVIN TB2 0.6 V to 1.8 V / 36 A VOUT MASTER CURRENT DVM_Monitor PVIN TB5 1 2 R9 VOUT VOUT P3 VOUT C8 100 µF 6.3 V + PGND C14 220 µF 10 V R5 TB4 1 PGND PGND PGND TP4 TB3 VIN SELECT P1 PGND 21 PGND 20 PGND 32 31 33 PGND PGND VOUT 35 34 36 VOUT VOUT VOUT 41 38 37 11 PVIN VOUT VOUT 40 39 12 3 PVIN VBIAS PGND VIN PVIN 2 1 1 VIN PVIN 4.5 V to 17 V TB7 PVIN PVIN PGND PGND R4 R3 24.3 kΩ 68.1 kΩ VBIAS 2 PGND 3 PGND C10 4.7 µF 25 V PWRGD TP7 PULL UP 4 AGND 5 6 PGND 7 SYNC_OUT 8 9 PWRGD 10 R16 AGND INH/UVLO VIN STSEL OCP_SEL SS/TR U1 DNC SENSE+ ILIM VADJ SYNC_OUT ISHARE PWRGD DNC AGND DNC PH RT/CLK 30 TP10 INH/UVLO AGND INH/UVLO PVIN 29 TP13 SS/TR 28 27 SS/TR 26 VADJ 25 C12 ISHARE 1 24 23 22 100 kΩ C11 R1 1 1 TP3 R2 TP11 AGND PH PH R6 2.87 kΩ 42 19 PH PH PH 17 18 16 PH PH 13 14 15 TP9 PH 487 kΩ PWRGD AGND R7 1.43 kΩ R8 VOUT SELECT 715 Ω CLK_IN TP12 PHASE 1 AGND P4 TP8 1 1.8 V 2 3 1.2 V 4 5 0.9 V 6 7 0.6 V 8 CLK_IN MASTER TP5 AGND AGND SLAVE 1 CURRENT DVM_Monitor TP17 PVIN TP18 3 1 4 2 VOUT R10 C16 22 µF 25 V C18 100 µF 6.3 V C24 0.1 µF 25 V C17 22 µF 25 V C19 100 µF 6.3 V C20 100 µF 6.3 V C21 100 µF 6.3 V + C22 100 µF 6.3 V C23 220 µF 10 V PGND 2 3 VIN C25 4.7 µF 25 V 4 AGND 5 6 PGND 7 8 PWRGD SYNC_OUT2 9 10 PGND 21 PGND 20 PGND 31 32 33 PGND AGND PGND VOUT 34 35 36 VOUT VOUT VOUT 37 41 38 12 11 PVIN VOUT VOUT PVIN PVIN 39 40 PVIN PVIN 1 PGND INH/UVLO VIN STSEL OCP_SEL SS/TR U2 DNC SENSE+ ILIM VADJ SYNC_OUT ISHARE PWRGD DNC AGND DNC PH RT/CLK 30 INH/UVLO 29 28 SS/TR 27 26 VADJ 25 ISHARE 24 C26 23 1 22 CLK_IN P5 AGND PH PH 2 3 42 19 PH PH PH 17 18 16 PH PH 13 14 15 NOTES: 1. Not Populated. PH 1 R11 2. This is designed to be a platform for quick customer evaluation of the LMZ31710 product. TP14 1 PHASE 16 SYNC_OUT 487 kΩ SLAVE 1 AGND LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated www.ti.com 4× Parallel Schematic SLAVE 2 CURRENT DVM_Monitor TP19 PVIN TP20 3 1 4 2 VOUT R13 C13 22 µF 25 V C27 100 µF 6.3 V C30 0.1 µF 25 V C15 22 µF 25 V C28 100 µF 6.3 V C29 100 µF 6.3 V C34 100 µF 6.3 V + C35 100 µF 6.3 V C32 220 µF 10 V PGND 2 3 VIN 4 C31 4.7 µF 25 V 5 AGND 6 PGND 7 8 PWRGD 9 10 PGND 20 21 31 PGND PGND 34 32 33 PGND PGND VOUT 37 35 36 VOUT VOUT VOUT 41 11 38 VOUT PVIN PVIN VOUT 40 12 39 PVIN PVIN PVIN 1 PGND AGND INH/UVLO VIN STSEL OCP_SEL SS/TR U3 DNC SENSE+ ILIM VADJ SYNC_OUT ISHARE PWRGD DNC AGND DNC PH RT/CLK 30 INH/UVLO 29 28 SS/TR 27 26 VADJ 25 ISHARE 24 C33 23 1 22 CLK_IN P6 AGND 1 PH PH 2 3 42 19 PH PH PH 16 17 18 PH 15 PH 13 14 PH SYNC_OUT3 R12 SYNC_OUT2 487 kΩ TP6 1 PHASE AGND SLAVE 2 SLAVE 3 CURRENT DVM_Monitor TP23 TP25 3 PVIN 1 4 VOUT 2 R15 C36 22 µF 25 V C38 100 µF 6.3 V C41 0.1 µF 25 V C37 22 µF 25 V C39 100 µF 6.3 V C40 100 µF 6.3 V C45 100 µF 6.3 V + C46 100 µF 6.3 V C43 220 µF 10 V PGND 2 3 VIN C42 4.7 µF 25 V 4 AGND 5 6 PGND 7 8 PWRGD 9 10 PGND 20 21 31 PGND PGND 34 32 33 PGND AGND PGND VOUT 37 35 36 VOUT VOUT VOUT 41 11 38 VOUT PVIN PVIN VOUT 12 39 PVIN 40 PVIN PVIN 1 PGND INH/UVLO VIN STSEL OCP_SEL SS/TR U4 DNC SENSE+ ILIM VADJ SYNC_OUT ISHARE PWRGD DNC AGND DNC PH RT/CLK 30 INH/UVLO 29 28 SS/TR 27 26 VADJ 25 ISHARE 24 C44 23 1 22 CLK_IN P7 AGND PH PH 2 3 42 19 PH PH PH 16 17 18 PH 15 PH 13 14 NOTES: PH 1 R14 1. Not Populated. 2. This is designed to be a platform for quick customer evaluation of the LMZ31710 product. SYNC_OUT3 487 kΩ TP22 1 PHASE SLAVE 3 AGND SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback LMZ31704 2-Phase Power Module Evaluation Module User's Guide Copyright © 2022 Texas Instruments Incorporated 17 Revision History www.ti.com 11 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (February 2014) to Revision A (January 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document. ................2 • Updated the user's guide title ............................................................................................................................ 2 18 LMZ31704 2-Phase Power Module Evaluation Module User's Guide SLVUA04A – FEBRUARY 2014 – REVISED JANUARY 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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