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LMZ34202
SNVSAJ2C – MARCH 2016 – REVISED JUNE 2018
LMZ34202 4.5-V to 42-V Input, 2-A Power Module
1 Features
2 Applications
•
•
•
•
•
Complete Integrated Power Solution Allows
Small Footprint, Low-Profile Design
10 mm × 10 mm × 4.3 mm Package
Wide-Output Voltage Adjust (2.5 V to 7.5 V)
Adjustable Switching Frequency
(200 kHz to 1 MHz)
Synchronizes to an External Clock
Automatic PFM Mode for Light Load Efficiency
Adjustable Soft-Start Time
Output Voltage Sequencing / Tracking
Power Good Output
Programmable Undervoltage Lockout (UVLO)
Over-Temperature Thermal Shutdown Protection
Over-Current Protection (Hiccup Mode)
Pre-Bias Output Start-Up
Operating Temperature Range: –40°C to 105°C
Enhanced Thermal Performance: 14°C/W
Meets EN55022 Class B Emissions
– Integrated Shielded Inductor
Create a Custom Design using the LMZ34202
with the WEBENCH® Power Designer
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Industrial and Motor Controls
Automated Test Equipment
Medical and Imaging Equipment
High Density Power Systems
3 Description
The LMZ34202 power module is an easy-to-use
integrated power supply that combines a 2-A DC-DC
converter with a shielded inductor and passives into a
low profile, QFN package. This total power solution
allows as few as three external components while
maintaining an ability to adjust key parameters to
meet specific design requirements.
The QFN package is easy to solder to a printed
circuit board, allows reflow profiles up to 245°C, and
has excellent power dissipation capability. The
LMZ34202 offers flexibilty with many features and is
ideal for powering a wide range of devices and
systems.
Device Information(1)
DEVICE NUMBER
LMZ34202
LMZ34202
PVIN
INH/UVLO
CIN
Efficiency vs Output Current
VOUT
100
VOUT
SENSE+
90
COUT
VBSEL
RSET
AGND
80
Efficiency (%)
VADJ
PGND
BODY SIZE
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
VIN
PACKAGE
QFN (43)
70
PVIN = 12 V
60
PVIN = 24 V
50
VOUT = 5 V
40
30
0.0
0.5
1.0
Output Current (A)
1.5
2.0
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ34202
SNVSAJ2C – MARCH 2016 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Switching Characteristics .......................................... 7
Typical Characteristics .............................................. 8
Typical Characteristics (Thermal Derating)............. 11
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 21
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
10.3 EMI........................................................................ 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
12.1 Tape and Reel Information ................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2018) to Revision C
Page
•
Changed allows reflows "up to 260°C" to "up to 245°C" to match Abs Max table ................................................................. 1
•
Added top navigator for TI reference design .......................................................................................................................... 1
Changes from Revision A (June 2017) to Revision B
Page
•
Added WEBENCH® design links for the LMZ34202 ............................................................................................................. 1
•
Increased the peak reflow temperature and maximum number of reflows to JEDEC specifications for improved
manufacturability..................................................................................................................................................................... 5
Changes from Original (March 2016) to Revision A
•
2
Page
Added peak reflow and maximum number of reflows information ........................................................................................ 5
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5 Pin Configuration and Functions
AGND
1
40 39
PGND
PGND
PH
PH
PH
PH
PH
PH
DNC
RVQ Package
43-Pin QFN
(Top View)
38 37 36 35 34 33 32
31
PGND
AGND
2
30 PGND
AGND
3
29 PGND
AGND
4
AGND
5
DNC
6
VBSEL
7
25 SS/TR
CLK
8
24 VADJ
RT
9
23 VERSA-COMP
28 PVIN
42
PVIN 27 PVIN
41 PGND
RTSEL 10
22 SENSE+
43 VOUT
11
21
PWRGD_PU
PWRGD
PGND
VOUT
16 17 18 19 20
VOUT
VOUT
VOUT
VOUT
AGND
12 13 14 15
VOUT
AGND
26 INH/UVLO
Pin Functions
PIN
TYPE
(1)
DESCRIPTION
NAME
NO.
AGND
1, 2, 3, 4,
5, 11, 12
G
Zero volt reference for the analog control circuitry. All of these pins are not connected together
internal to the device and must be connected to one another externally using an analog ground
plane on the PCB. Pins 11 and 12 are internally connected to the PGND of the device at a single
point. The analog ground plane of the PCB should allow only analog ground currents to flow through
these pins.
CLK
8
I
Synchronization input to synchronize the device to an external clock. Connect this pin to AGND if
not used.
DNC
6, 40
-
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage.
These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
26
I
Inhibit and UVLO adjust pin. Use an open drain or open collector device to control the inhibit
function. A resistor divider between this pin, AGND, and PVIN adjusts the UVLO voltage. Connect
this pin to PVIN if not used.
PGND
19, 29, 30,
31, 32, 33,
41
G
This is the return current path for the power stage of the device. Connect these pins to the input
source, the load, and to the bypass capacitors associated with PVIN and VOUT using power ground
planes on the PCB. Pad 41 should be connected to the ground planes using multiple vias for good
thermal performance.
PH
34, 35, 36,
37, 38, 39
O
Phase switch node. Do not place any external components on these pins or tie them to a pin of
another function.
PVIN
27, 28, 42
I
Power input voltage. These pins supply all of the power to the device. Connect these pins to the
input source and connect external bypass capacitors between these pins and PGND close to the
device.
20
O
Power Good flag pin. This open drain output asserts low if the output voltage is more than
approximately ±10% out of regulation. This pin is internally connected to an uncommitted 100k pullup resistor that can be pulled up to a user-defined voltage applied to the PWRGD_PU pin.
INH/UVLO
PWRGD
(1)
G = Ground, I = Input, O = Output
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Pin Functions (continued)
PIN
NAME
NO.
TYPE
(1)
DESCRIPTION
PWRGD_PU
21
I
An internal 100 k pull-up resistor is connected between this pin and the PWRGD pin. If use of this
internal pull-up resistor is desired, connect this pin to an appropriate voltage source that is less than
or equal to 12 V. If unused, leave this pin floating.
RT
9
I
This pin is connected to internal frequency setting circuitry which sets the default switching
frequency to 500 kHz. An external resistor can be connected from this pin to AGND to adjust the
switching frequency. Refer to application section in datasheet.
RTSEL
10
I
This pin can be used to adjust the switching frequency to 1 MHz without the need for an external
resistor. Connect this pin to AGND to adjust the frequency to 1 MHz. Otherwise, leave this pin
floating.
SENSE+
22
I
Remote sense connection. This pin must be connected to VOUT at the load or at the device pins.
Connect the pin to VOUT at the load for improved regulation.
SS/TR
25
I
soft-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage
soft-start ramp above its 4.1 ms default setting. A voltage applied to this pin allows for tracking and
sequencing control.
VADJ
24
I
Connecting a resistor between this pin and AGND adjusts the output voltage.
VBSEL
7
I
Selectable internal bias supply. For output voltages ≥ 4.5 V, connect this pin to VOUT. For output
voltages < 4.5 V, connect this pin to AGND.
VERSACOMP
23
I
Connects to internal compensation network. This pin can be left floating or connected to the VADJ
pin to select the proper compensation depending on the output voltage.
13, 14, 15,
16, 17, 18,
43
O
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external bypass capacitors between these pins and PGND close to the
device.
VOUT
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
PVIN, INH/UVLO
MIN
MAX
UNIT
–0.3
50
V
VOUT, SENSE+, VBSEL
–0.3
VADJ, VERSA-COMP, RT, RTSEL, SS/TR
–0.3
3.6
V
PWRGD, PWRGD_PU
–0.3
15
V
CLK
–0.3
5.5
V
PH
–0.3
50
V
Operating junction temperature (3)
–40
125
°C
Storage temperature, Tstg
–65
150
°C
245 (5)
°C
Input voltage
Output voltage
30
(2)
Peak Reflow Case Temperature (4)
Maximum Number of Reflows Allowed (4)
3 (5)
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20-2000Hz
(1)
(2)
(3)
(4)
(5)
V
1500
G
20
G
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The maximum voltage that can be applied to these pins is 30 V or PVIN, whichever is less.
See temperature derating curves in the Typical Characteristics section for thermal information.
For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note.
Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
4.5
UNIT
PVIN
Input voltage
42
V
VOUT
Output voltage
2.5
7.5
ƒSW
Switching frequency
300
1000
kHz
TA
Operating ambient temperature
–40
105
°C
V
6.4 Thermal Information
LMZ34202
THERMAL METRIC
(1)
RVQ (QFN)
UNIT
43 PINS
RθJA
Junction-to-ambient thermal resistance
14
°C/W
ψJT
Junction-to-top characterization parameter
2.6
°C/W
ψJB
Junction-to-board characterization parameter
9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Over –40°C to +105°C free-air temperature, PVIN = 24 V, VOUT = 5 V, IOUT = IOUT max, ƒsw = 500 kHz,
CIN1 = 1 × 10-µF, 100-V 1210 ceramic, CIN2 = 1 × 100-µF 100-V electrolytic bulk, and COUT = 3 × 47-µF, 16-V 1210 ceramic
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (PVIN)
PVIN
Input voltage range
UVLO
PVIN undervoltage lockout
4.5 (1)
Over IOUT range
PVIN increasing
3.2
PVIN decreasing
2.8
42
V
3.8
V
V
OUTPUT VOLTAGE
VOUT (ADJ)
VOUT
VOUT ripple
Output voltage adjust range
Over IOUT range
Set-point voltage tolerance
TA = 25°C, IOUT = 200 mA
2.5
±0.7
7.5
V
±1.5 (2)
%
Temperature variation
-40°C ≤ TA ≤ 105°C, IOUT = 0 A
±0.9
%
Line regulation
TA = 25°C, Over PVIN range, IOUT = 300 mA
±0.1
%
Load regulation
TA = 25°C, IOUT = 300 mA to IOUT max
±0.3
%
Total output voltage variation
Includes set-point, line, load, and temperature
±2
%
Output voltage ripple
20-MHz Bandwidth
10
mV/pp
OUTPUT CURRENT
IOUT
Output current
TA = 105°C, natural convection
0
1.5
A
IOUT
Output current
TA = 105°C, 200LFM
0
2
A
IOUT
Output current
TA = 95°C, natural convection
0
2
A
ILIM
Overcurrent threshold
2.5
A
VOUT = 7.5 V; ƒSW = 400 kHz
95
%
VOUT = 5 V; ƒSW = 200 kHz
93
%
VOUT = 5 V; ƒSW = 500 kHz
92
%
VOUT = 3.3 V; ƒSW= 200 kHz
90
%
VOUT = 2.5 V; ƒSW = 200 kHz
87
%
VOUT = 7.5 V; ƒSW = 400 kHz
92
%
VOUT = 5 V; ƒSW= 250 kHz
90
%
VOUT = 5 V; ƒSW= 500 kHz
88
%
VOUT = 3.3 V; ƒSW = 250 kHz
86
%
VOUT = 2.5 V; ƒSW = 250 kHz
81
%
100
µs
Transient response
IOUT = 50%
Recovery time
load step
Over/Undershoot
1 A/µs slew rate
2
%
Internal slow start time
SS/TR pin open
4.1
ms
PERFORMANCE
PVIN = 12 V
IOUT = 1 A
Efficiency
η
PVIN = 24 V
IOUT = 1 A
SLOW START
TSS
INHIBIT
VINH (high)
VINH (low)
II (shutdown)
Inhibit control
Input shutdown supply current
Precision inhibit level
Inhibit turn-off hysteresis
INH/UVLO pin conected to AGND
2.00
2.1
2.42
V
6.2 (3)
µA
-0.294
2.4
V
POWER GOOD (PWRGD)
VOUT rising
VPWRGD
PWRGD thresholds
VOUT falling
(1)
(2)
(3)
6
Good
95
%
Fault
110
%
Fault
90
%
Good
105
%
The minimum PVIN is 4.5 V or (VOUT / 0.75), whichever is greater. For VOUT = 3.3 V, the minimum PVIN is 4.75 V when IOUT > 1.5 A.
The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
Guaranteed by design. Not production tested.
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Electrical Characteristics (continued)
Over –40°C to +105°C free-air temperature, PVIN = 24 V, VOUT = 5 V, IOUT = IOUT max, ƒsw = 500 kHz,
CIN1 = 1 × 10-µF, 100-V 1210 ceramic, CIN2 = 1 × 100-µF 100-V electrolytic bulk, and COUT = 3 × 47-µF, 16-V 1210 ceramic
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
TSHUTDOWN
Thermal shutdown
Shutdown Temperature
160
°C
10
°C
Hysteresis
INPUT/OUTPUT CAPACITANCE
CIN
External input capacitance
10 (4)
ceramic
non-ceramic
100
64 (5)
Ceramic
COUT
External output capacitance
µF
Non-ceramic
100
ceramic + non-ceramic
(5)
(6)
µF
See (6)
µF
(6)
µF
20
mΩ
See
Equivalent series resistance (ESR)
(4)
µF
See (6)
The specified minimum ceramic input capacitance represents the standard capacitance value. The actual effective capacitance after
considering the effects of DC bias and temperature variation should be ≥ 4.7 µF.
The amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection). The minimum
required output capacitance must be comprised of ceramic capacitance. The amount of required ceramic capacitance represents the
standard capacitance value. Locate the capacitance close to the device. Adding additional ceramic or non-ceramic capacitance close to
the load improves the response of the regulator to load transients.
The maximum allowable output capacitance varies depending on the output voltage (see Output Capacitor Selection).
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
RT and RTSEL pins open
410
500
590
kHz
ƒCLK
Synchronization frequency
200
1000
kHz
VCLK-H
CLK high level
2
5.5
V
0.4
V
ƒSW
VCLK-L
Switching frequency
CLK Control
DCLK
TEST CONDITIONS
CLK low level
CLK duty cycle
10%
50%
90%
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6.7 Typical Characteristics
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
TA = 25°C, unless otherwise noted.
70
60
70
60
50
50
40
40
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
30
0.0
0.5
1.0
Output Current (A)
1.5
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 200 kHz
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
30
0.0
2.0
0.5
D001
PVIN = 5 V
Figure 1. Efficiency vs Output Current
D004
Figure 2. Efficiency vs Output Current
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 200 kHz
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
1.75
1.50
Power Dissipation (W)
Power Dissipation (W)
2.0
2.00
1.75
1.25
1.00
0.75
0.50
0.25
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0.0
0.5
1.0
Output Current (A)
1.5
0.00
0.0
2.0
0.5
D002
PVIN = 5 V
1.0
Output Current (A)
1.5
2.0
D005
PVIN = 12 V
Figure 3. Power Dissipation vs Output Current
Figure 4. Power Dissipation vs Output Current
30
30
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
25
Output Voltage Ripple (mV)
Output Voltage Ripple (mV)
1.5
PVIN = 12 V
2.00
20
15
10
5
0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 200 kHz
VOUT = 3.3 V, fSW = 200 kHz
VOUT = 2.5 V, fSW = 200 kHz
25
20
15
10
5
0
0.0
0.5
D003
PVIN = 5 V
1.0
Output Current (A)
1.5
2.0
D006
PVIN = 12 V
Figure 5. Voltage Ripple vs Output Current
8
1.0
Output Current (A)
Figure 6. Voltage Ripple vs Output Current
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Typical Characteristics (continued)
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
TA = 25°C, unless otherwise noted.
70
60
70
60
50
50
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
40
30
0.0
0.5
1.0
Output Current (A)
1.5
fSW = 250 kHz
fSW = 500 kHz
fSW = 750 kHz
fSW = 1 MHz
40
30
0.0
2.0
0.5
PVIN = 24 V
PVIN = 24 V
VOUT = 5 V
Figure 7. Efficiency vs Output Current
2.0
D010
over frequency range
2.5
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
fSW = 1 MHz
fSW = 750 kHz
fSW = 500 kHz
fSW = 250 kHz
2.0
Power Dissipation (W)
2.0
Power Dissipation (W)
1.5
Figure 8. Efficiency vs Output Current
2.5
1.5
1.0
1.5
1.0
0.5
0.5
0.0
0.0
0.5
1.0
Output Current (A)
1.5
0.0
0.0
2.0
0.5
D008
PVIN = 24 V
PVIN = 24 V
VOUT = 5 V
Figure 9. Power Dissipation vs Output Current
1.0
Output Current (A)
1.5
2.0
D011
over frequency range
Figure 10. Power Dissipation vs Output Current
40
40
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
30
Output Voltage Ripple (mV)
Output Voltage Ripple (mV)
1.0
Output Current (A)
D007
20
10
0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
fSW = 250 kHz
fSW = 500 kHz
fSW = 750 kHz
fSW = 1 MHz
30
20
10
0
0.0
0.5
D009
PVIN = 24 V
PVIN = 24 V
VOUT = 5 V
Figure 11. Voltage Ripple vs Output Current
1.0
Output Current (A)
1.5
2.0
D012
over frequency range
Figure 12. Voltage Ripple vs Output Current
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Typical Characteristics (continued)
TA = 25°C, unless otherwise noted.
100
3.0
90
Power Dissipation (W)
80
Efficiency (%)
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
2.5
70
60
50
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
40
30
0.0
0.5
1.0
Output Current (A)
1.5
2.0
1.5
1.0
0.5
2.0
0.0
0.0
0.5
1.0
Output Current (A)
D013
PVIN = 36V
1.5
2.0
D014
PVIN = 36 V
Figure 13. Efficiency vs Output Current
Figure 14. Power Dissipation vs Output Current
Output Voltage Ripple (mV)
50
VOUT = 7.5 V, fSW = 400 kHz
VOUT = 5.0 V, fSW = 250 kHz
VOUT = 3.3 V, fSW = 250 kHz
VOUT = 2.5 V, fSW = 250 kHz
40
30
20
10
0
0.0
0.5
1.0
Output Current (A)
1.5
2.0
D015
PVIN = 36 V
Figure 15. Voltage Ripple vs Output Current
10
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6.8 Typical Characteristics (Thermal Derating)
115
115
105
105
105
105
Ambient Temperature (ƒC)
Ambient Temperature (ƒC)
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's
maximum operating temperatures. Derating limits apply to devices soldered directly to a 50 mm × 100 mm, 4-layer PCB with
2 oz. copper.
95
85
75
65
Airflow
55
45
100LFM
35
Nat conv
95
85
75
65
Airflow
55
200LFM
45
100LFM
35
Nat conv
25
25
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Output Current (A)
PVIN = 24 V
2.0
0.0
0.2
0.4
0.6
VOUT = 3.3 V
0.8
1.0
1.2
1.4
1.6
1.8
Output Current (A)
C001
fSW = 250 kHz
PVIN = 24 V
Figure 16. Safe Operating Area
VOUT = 5 V
2.0
C001
fSW = 250 kHz
Figure 17. Safe Operating Area
115
Ambient Temperature (ƒC)
105
105
95
85
75
Airflow
65
400LFM
55
200LFM
45
100LFM
35
Nat conv
25
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Output Current (A)
PVIN = 24 V
VOUT = 7.5 V
1.8
2.0
C001
fSW = 400 kHz
Figure 18. Safe Operating Area
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7 Detailed Description
7.1 Overview
The LMZ34202 is a full featured 42-V input, 2-A, synchronous step down converter with PWM, MOSFETs,
inductor, and control circuitry integrated into a low-profile, overmolded package. This device enables small
designs by integrating all but the input and output capacitors, while still leaving the ability to adjust key
parameters to meet specific design requirements. The LMZ34202 provides a 3× output voltage range of 2.5 V to
7.5 V. A single external resistor is used to adjust the output voltage to the desired output. The switching
frequency is also adjustable by using an external resistor or a synchronization pulse to accommodate various
input and output voltage conditions and to optimize efficiency. The device provides accurate voltage regulation
for a variety of loads by using an internal voltage reference that is 2% accurate over temperature. Input undervoltage lockout is internally set at 3.2 V, but can be adjusted upward using a resistor divider on the INH/UVLO
pin of the device. The INH/UVLO pin can also be pulled low to put the device in standby mode to reduce input
quiescent current. The device provides a power good signal to indicate when the output is within ±5% of its
nominal voltage. Thermal shutdown and current limit features protect the device during an overload condition.
Automatic PFM mode improves light-load efficiency. A 43-pin, QFN, package that includes exposed bottom pads
provides a thermally enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
LMZ34202
PWRGD_PU
100kΩ
OCP
INH/UVLO
Shutdown
Logic
PWRGD
LDO
SENSE+
PWRGD
Logic
VERSA-COMP
Thermal
Shutdown
PVIN
UVLO
VBSEL
PVIN
20kΩ
PH
VADJ
+
+
VREF
SS/TR
Comp
Power
Stage
and
Control
Logic
VOUT
10 µH
CLK
Oscillator
PGND
RT
AGND
RTSEL
38.3kΩ
12
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage
The VADJ pin sets the output voltage of the LMZ34202. The output voltage adjustment range is from 2.5 V to
7.5 V. The switching frequency range for any output voltage must be determined from Table 4 or Table 5. The
adjustment method requires the addition of RSET, which sets the output voltage, and the connection of SENSE+
to VOUT. The RSET resistor must be connected directly between the VADJ (pin 24) and AGND. The SENSE+ pin
(pin 22) must be connected to VOUT either at the load for improved regulation or at VOUT of the device. Table 1
lists the standard external RSET resistor for a number of common bus voltages.
Table 1. Standard RSET Resistor Values for Common Output Voltages
OUTPUT VOLTAGE VOUT (V)
RSET (kΩ)
2.5
3.3
5.0
6.0
7.5
13.7
8.87
5.11
4.02
3.09
For other output voltages, the value of the required resistor can either be calculated using the following formula,
or simply selected from the range of values given in Table 2.
RSET
20
(k:)
ª§ VOUT · º
«¨ 1.011 ¸ 1»
¹ ¼
©
(1)
Table 2. Standard RSET Resistor Values
VOUT (V)
RSET (kΩ)
VOUT (V)
RSET (kΩ)
2.5
13.7
5.1
4.99
2.6
12.7
5.2
4.87
2.7
11.8
5.3
4.75
2.8
11.3
5.4
4.64
2.9
10.7
5.5
4.53
3.0
10.2
5.6
4.42
3.1
9.76
5.7
4.32
3.2
9.31
5.8
4.22
3.3
8.87
5.9
4.12
3.4
8.45
6.0
4.02
3.5
8.06
6.1
3.97
3.6
7.87
6.2
3.92
3.7
7.50
6.3
3.83
3.8
7.32
6.4
3.74
3.9
6.98
6.5
3.65
4.0
6.81
6.6
3.61
4.1
6.49
6.7
3.57
4.2
6.34
6.8
3.48
4.3
6.19
6.9
3.40
4.4
5.90
7.0
3.36
4.5
5.76
7.1
3.32
4.6
5.62
7.2
3.24
4.7
5.49
7.3
3.20
4.8
5.36
7.4
3.16
4.9
5.23
7.5
3.09
5.0
5.11
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7.3.2 Switching Frequency (RT)
The switching frequency range of the LMZ34202 is 200 kHz to 1 MHz. Not all PVIN, VOUT, and IOUT conditions
can be set to all of the frequencies in this range. See Recommended Operating Range for the allowable
operating ranges. The switching frequency can easily be set one of three ways. First, leaving the RT pin (pin 9)
and RTSEL pin (pin 10) floating (OPEN) allows operation at the default switching frequency of 500 kHz. Also,
connecting the RTSEL pin to AGND while floating the RT pin, sets the switching frequency to 1 MHz. The option
is also available to set the switching frequency to any frequency in the range of 200 kHz to 1 MHz, by connecting
a resistor (RRT) between the RT pin and AGND, while floating the RTSEL pin. See Table 3 for standard resistor
values for setting the switching frequency or use Equation 2 to calculate RRT for other switching frequencies.
Table 3. Switching Frequency RRT Values
Switching Frequency
RRT
RRT (kΩ)
250 kHz
158
500 kHz
78.7 or (RT pin OPEN, RTSEL pin OPEN)
750 kHz
53.6
1 MHz
38.3 or (RT pin OPEN, RTSEL pin to AGND)
40200
0.6 (k:)
Fsw(kHz)
(2)
7.3.3 Recommended Operating Range
Table 4 and Table 5 below show the allowable switching frequencies for a given range of output voltages.
Reference Table 4 for applications where the maximum output current is 1.75 A or less. Reference Table 5 for
applications that the output current is greater than 1.75 A. Notice that applications requiring less than 1.75 A can
operate over a much wider range of switching frequencies. For the most efficient solution, always operate at the
lowest allowable frequency.
Table 4. Switching Frequency vs Output Voltage
Output Current ≤ 1.75 A
SWITCHING FREQUENCY RANGE (kHz)
VOUT RANGE (V)
PVIN = 12 V
PVIN = 24 V
PVIN = 36 V
MIN
MAX
MIN
MAX
MIN
MAX
2.5 - 3.5 V
200
1000
200
600
200
400
>3.5 - 4.5 V
200
1000
200
850
200
550
>4.5 - 5.5 V
200
1000
200
1000
200
750
>5.5 - 6.5 V
300
1000
200
1000
200
1000
>6.5 - 7.5 V
300
900
300
1000
300
950
Table 5. Switching Frequency vs Output Voltage
Output Current > 1.75 A
SWITCHING FREQUENCY RANGE (kHz)
VOUT RANGE (V)
14
PVIN = 12 V
PVIN = 24 V
PVIN = 36 V
MIN
MAX
MIN
MAX
MIN
MAX
2.5 - 3.5 V
200
450
200
500
200
400
>3.5 - 4.5 V
200
500
200
600
200
550
>4.5 - 5.5 V
200
500
200
650
200
700
>5.5 - 6.5 V
300
500
250
700
250
800
>6.5 - 7.5 V
300
400
300
750
300
800
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7.3.4 Synchronization (CLK)
The LMZ34202 switching frequency can also be synchronized to an external clock from 200 kHz to 1 MHz. Not
all PVIN, VOUT, and IOUT conditions can be set to all of the frequencies in this range. See Recommended
Operating Range for the allowable operating ranges.
To implement the synchronization feature, connect a clock signal to the CLK pin with a duty cycle between 10%
and 90%. The clock signal amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the
switching cycle is synchronized to the rising edge of CLK pin. Before the external clock is present the device
operates in RT mode and the switching frequency is set by RRT resistor. Select RRT to set the frequency close to
the external synchronization frequency. When the external clock is present, the CLK mode overrides the RT
mode. If the external clock is removed or fails at logic high or low, the LMZ34202 will switch at the frequency
programmed by the RRT resistor after a time-out period. Connect the CLK pin (pin 8) to AGND if not used.
7.3.5 Output Capacitor Selection
The minimum required and maximum output capacitance of the LMZ34202 is a function of the output voltage as
shown in Table 6. Additionally, the output voltage will determine the Versa-Comp configuration (see VERSACOMP Pin Configurations), which is also included in Table 6. The capacitance values listed in Table 6 are the
specified capacitance values. The effects of DC bias and temperature variation must be considered when using
ceramic capacitance. For ceramic capacitors, package size, voltage rating, and dielectric material will contribute
to differences between the specified value and the actual effective value of the capacitance. COUT(min) must be
comprised of ceramic type capacitors. Additional capacitance, not exceeding COUT(max), may be ceramic type or
low-ESR polymer type. See Table 7 for a preferred list of output capacitors by vendor.
Table 6. Required Output Capacitance
(1)
(2)
VOUT (V)
MINIMUM REQUIRED
COUT (µF) (1) (2)
2.5
64
350
Leave OPEN
3.3
64
350
Connect to VADJ
5.0
64
350
Connect to VADJ
6.0
64
200
Connect to VADJ
7.5
100
200
Connect to VADJ
MAXIMUM COUT (µF)
Versa-Comp
Connection
(2)
Minimum required output capacitance must be comprised of ceramic capacitance.
COUT values represent specified capacitance values.
Table 7. Recommended Output Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING
VOLTAGE (V)
CAPACITANCE (2)
(µF)
ESR (3)
(mΩ)
TDK
X5R
C3225X5R1C106K
16
10
2
Murata
X5R
GRM32ER61C106K
16
10
2
TDK
X5R
C3225X5R1C226M
16
22
2
Murata
X5R
GRM32ER61C226K
16
22
2
TDK
X5R
C3225X5R1A476M
10
47
2
Murata
X5R
GRM32ER61C476K
16
47
3
TDK
X5R
C3225X5R0J107M
6.3
100
2
Murata
X5R
GRM32ER60J107M
6.3
100
2
Murata
X5R
GRM32ER61A107M
10
100
2
Kemet
X5R
C1210C107M4PAC7800
16
100
2
18
Panasonic
POSCAP
6TPE100MI
6.3
100
Panasonic
POSCAP
6TPF220M9L
6.3
220
9
Panasonic
POSCAP
6TPE220ML
6.3
220
12
(1)
(2)
(3)
Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Specified capacitance values.
Maximum ESR @ 100kHz, 25°C.
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7.3.6 VERSA-COMP Pin Configurations
The versa-comp feature of the LMZ34202 allows a simple method to adjust the internal compensation network to
provide the optimized phase and gain margin based on the output voltage. This easy-to-use feature requires no
external components and is implemented by the simple configuration of two adjacent pins on the module.
The versa-comp feature must be configured in one of two ways; VERSA-COMP pin left OPEN or VERSA-COMP
pin tied to VADJ. The output voltage determines the appropriate Versa-Comp pin configuration. Table 8 lists the
Versa-Comp configuration. Figure 19 shows the two possible Versa-Comp pin configurations.
Versa-Comp OPEN
Versa-Comp to VADJ
VOUT
VOUT
SENSE+
SENSE+
VERSA-COMP
VERSA-COMP
VADJ
VADJ
AGND
AGND
RSET
RSET
Figure 19. Versa-Comp Configurations
Table 8. VERSA-COMP Pin Configurations
VOUT RANGE (V)
VERSA-COMP PIN
CONFIGURATION
MIN
MAX
2.5
< 3.0
OPEN
3.0
7.5
Connect to VADJ
7.3.7 Input Capacitor Selection
The LMZ34202 requires a ceramic capacitor with a minimum effective input capacitance of 4.7 μF. Use only
high-quality ceramic type X5R or X7R capacitors with sufficient voltage rating. An additional 100 µF of nonceramic capacitance is recommended for applications with transient load requirements. The voltage rating of
input capacitors must be greater than the maximum input voltage. To compensate the derating of ceramic
capactors, a voltage rating of twice the maximum input voltage is recommended. At worst case, when operating
at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must be at least
1.0 Arms. Table 9 includes a preferred list of capacitors by vendor.
Table 9. Recommended Input Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING VOLTAGE (V)
CAPACITANCE
(µF)
(2)
ESR (3)
(mΩ)
TDK
X5R
C3225X5R1H106K
50
10
3
Murata
X7R
GRM32ER71H106K
50
10
2
Murata
X7R
GRM32ER71J106K
63
10
2
Panasonic
ZA
EEHZA1H101P
50
100
28
Panasonic
ZA
EEHZA1J560P
63
56
30
(1)
(2)
(3)
16
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Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Specified capacitance values
Maximum ESR @ 100kHz, 25°C.
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7.3.8 Output On/Off Inhibit (INH/UVLO)
The INH/UVLO pin provides on and off control of the device. The INH input provides a precise 2.1 V rising
threshold to allow direct logic drive or connection to a voltage divider from a higher voltage source such as PVIN.
Once the INH/UVLO pin voltage exceeds the threshold voltage, the device starts operation. The INH input also
incorporates 300 mV (typ) of hysteresis resulting in a falling threshold of 1.8 V. If the INH/UVLO pin voltage is
pulled below the threshold voltage, the regulator stops switching and enters low quiescent current state. The
INH/UVLO pin cannot be open circuit or floating. The simplest way to enable the operation of the LMZ34202 is to
connect the INH/UVLO pin to PVIN pin directly as shown in Figure 20. This connection allows the LMZ34202
device to restart when PVIN is again within the operation range.
If an application requires controlling the INH/UVLO pin, either drive it directly with a logic input or use an open
drain and collector device to interface with the pin and place a 100-kΩ resistor between this pin and PVIN pin as
shown in Figure 21. When turning Q1 on applies a low voltage to the inhibit control (INH/UVLO) pin and disables
the output of the supply, shown in Figure 22. If Q1 is turned off, the supply executes a soft-start power-up
sequence, as shown in Figure 23.
PVIN
PVIN
PVIN
100 kΩ
INH/UVLO
INH/UVLO
Q1
INH
Control
AGND
AGND
Figure 20. Enabling the Device
Figure 21. Typical Inhibit Control
Figure 22. Inhibit Turn-Off
Figure 23. Inhibit Turn-On
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7.3.9 Under Voltage Lockout (UVLO)
The LMZ34202 device has an internal UVLO circuit which prevents the device from operating until the PVIN
voltage exceeds the UVLO threshold, (3.2 V (typ)). The device will begin switching and the output voltage will
begin to rise once PVIN exceeds the threshold, however PVIN must be greater than (VOUT/0.75) in order to for
VOUT to regulate at the set-point voltage.
Applications may require a higher UVLO threshold to prevent early turn-on, for sequencing requirements, or to
prevent input current draw at lower input voltages. An external resistor divider can be added to the INH/UVLO pin
to adjust the UVLO threshold higher. The external resistor divider can be configured as shown in Figure 24.
Table 10 lists standard values for RUVLO1 and RUVLO2 to adjust the UVLO voltage higher.
PVIN
PVIN
RUVLO1
INH/UVLO
RUVLO2
AGND
Figure 24. Adjustable PVIN UVLO
Table 10. Resistor Values for Adjusting PVIN UVLO
PVIN UVLO (V)
4.5
10
15
20
25
30
RUVLO1 (kΩ)
100
100
100
100
100
100
RUVLO2 (kΩ)
86.6
26.1
16.2
11.5
9.09
7.50
7.3.10 Remote Sense
The SENSE+ pin must be connected to VOUT at the load, or at the device pins.
Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by
allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by
the high output current flowing through the small amount of pin and trace resistance. This should be limited to a
maximum of 300 mV.
NOTE
The remote sense feature is not designed to compensate for the forward drop of nonlinear
or frequency dependent components that may be placed in series with the converter
output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When
these components are enclosed by the SENSE+ connection, they are effectively placed
inside the regulation control loop, which can adversely affect the stability of the regulator.
7.3.11 VBSEL
The VBSEL pin allows the user to select the input source of the internal bias circuitry to improve efficiency. For
output voltages ≥ 4.5 V, connect this pin to VOUT. For output voltages < 4.5 V, connect this pin to AGND.
18
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7.3.12 Soft-Start (SS/TR)
Leaving SS/TR pin open enables the internal slow start time interval of approximately 4.1 ms. Adding additional
capacitance between the SS pin and AGND increases the slow start time. Increasing the slow start time will
reduce inrush current seen by the input source and reduce the current seen by the device when charging the
output capacitors. To avoid the activation of current limit and ensure proper start-up, the SS capacitor may need
to be increased when operating near the maximum output capacitance limit.
See Table 11 below for SS capacitor values and timing interval.
Table 11. Soft-Start Capacitor Values and Soft-Start Time
CSS (nF)
open
15
22
33
47
SS Time (ms)
4.1
7
10
15
20
7.3.13 Power Good (PWRGD) and Pull-up (PWRGD_PU)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 95% and 105% of the
set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pullup resistor value is
between 10 kΩ and 100-kΩ to a voltage source that is 12 V or less. The LMZ34202 has an internal 100 kΩ
between the PWRGD pin (pin 20) and the PWRGD_PU pin (pin 21). Connect the PWRGD_PU pin to an external
voltage source to avoid using an external pullup resistor. The PWRGD pin is pulled low when the voltage on
SENSE+ is lower than 90% or greater than 110% of the nominal set voltage.
7.3.14 Overcurrent Protection
For protection against load faults, the LMZ34202 incorporates output overcurrent protection. Applying a load that
exceeds the regulator's overcurrent threshold causes the output to shut down when the output voltage falls below
the PWRGD threshold. Following shutdown, the module periodically attempts to recover by initiating a soft-start
power-up as shown in Figure 25. This is described as a hiccup mode of operation, whereby the module
continues in a cycle of successive shutdown and power up until the load fault is removed. During this period, the
average current flowing into the fault is significantly reduced which reduces power dissipation. Once the fault is
removed, the module automatically recovers and returns to normal operation as shown in Figure 26.
Figure 25. Overcurrent Limiting
Figure 26. Removal of Overcurrent
7.3.15 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C typically. The device reinitiates the power up sequence when the junction temperature drops below 150°C
typically.
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7.4 Device Functional Modes
7.4.1 Active Mode
The LMZ34202 is in Active Mode when PVIN is above the UVLO threshold and the INH/UVLO pin voltage is
above the INH high threshold. The simplest way to enable the LMZ34202 is to connect the INH/UVLO terminal to
PVIN. This allows self start-up of the LMZ34202 when the input voltage is in the operation range: 4.5 V to 42 V.
7.4.2 Light Load Operation
At light load, the LMZ34202 operates in pulse skip mode to improve efficiency and decrease power dissipation by
reducing switching losses and gate drive losses. In light load operation (PFM mode), the output voltage can rise
slightly above the set-point specification. To avoid this behavior, a 300-mA load is required on the output.
7.4.3 Shutdown Mode
The INH/UVLO pin provides electrical ON and OFF control for the LMZ34202. When the INH/UVLO pin voltage is
below the INH threshold, the device is in shutdown mode. In shutdown mode the stand-by current is 2.4 μA
typically with PVIN = 24 V. The LMZ34202 also employs under voltage lock out protection. If PVIN is below the
UVLO level, the output of the regulator turns off.
20
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ34202 is a synchronous step down DC-DC power module. It is used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LMZ34202. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH software utilizes an iterative design procedure and accesses
comprehensive databases of components.
8.2 Typical Application
8.2.1 Minimum External Component Application
The LMZ34202 requires only a few external components to convert from a wide input voltage supply range to a
wide range of output voltages. Figure 27 shows a basic LMZ34202 schematic with only the minimum required
components.
SENSE+
PVIN = 24V
PVIN
VOUT = 5V
VOUT
VBSEL
10 µF
50 V
LMZ34202
100 µF
10 V
INH/UVLO
SS/TR
CLK
RTSEL
RT
PWRGD_PU
PWRGD
VERSA-COMP
VADJ
AGND
PGND
5.11 kΩ
Figure 27. LMZ34202 Minimum External Component Application
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 12 and follow the design procedures below.
Table 12. Design Example Parameters
DESIGN PARAMETER
VALUE
Input Voltage PVIN
24 V typical
Output Voltage VOUT
5.0 V
Output Current Rating
2A
Operating Frequency
500 kHz
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ34202 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Output Voltage Set-Point
The output voltage of the LMZ34202 device is externally adjustable using a single resistor (RSET). Select the
value of RSET from Table 2 or calculate using Equation 3:
20
RSET
(k:)
ª§ VOUT · º
«¨ 1.011 ¸ 1»
¹ ¼
©
(3)
Knowing the desired output voltage is 5 V, the RSET value can then be calculated using Equation 3 or selected
from Table 2. The formula yields a value of 5.07 kΩ. Choose the closest available value of 5.11 kΩ for RSET.
8.2.1.2.3 RT and RTSEL
The default switching frequency of the LMZ34202 is set to 500 kHz by leaving the RT pin open and the RTSEL
pin open. The switching frequency of this application is 500-kHz, therefore no additional resistor is required to set
the switching frequency. If another frequency is desired, use Table 3 to select the required resistor value.
8.2.1.2.4 VERSA-COMP
The Versa-Comp feature of the LMZ34202 configures the internal compensation based on the output voltage.
From Table 8, the required Versa-Comp configuration for a 5-V output is to connect the VERSA-COMP pin to the
VADJ pin.
8.2.1.2.5 VBSEL
The VBSEL pin allows the user to select the input source of the internal bias circuitry to improve efficiency. For
output voltages ≥ 4.5 V, connect this pin to VOUT. For output voltages < 4.5 V, connect this pin to AGND.
8.2.1.2.6 Input Capacitors
For this design, a 10-μF, X7R dielectric ceramic capacitor rated for 50 V is used for the input decoupling
capacitor. The effective capacitance at 24 V is 5.7 μF, the equivalent series resistance (ESR) is approximately 3
mΩ, and the current-rating is 5 A.
8.2.1.2.7 Output Capacitors
The minimum required output capacitance for a 5 V output is 64 μF of ceramic capacitance. For this design, a
100 μF, X5R dielectric ceramic capacitor rated for 10 V is used for the output capacitor.
22
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8.2.1.3 Application Curves
Figure 29. Output Ripple and PH Node Waveforms
Figure 28. Start-up Waveforms
8.2.2 INH Control Application
Figure 30 shows a more typical use schematic which makes use of the INH control, Versa-Comp, SS, PWRGD
and PWRGD_PU features, along with adjusting the switching frequency with an external resistor. Setting these
additional features is descibed below.
SENSE+
PVIN = 24V
VBSEL
100 kΩ
LMZ34202
100 µF 10 µF
50 V 50 V
INH/UVLO
INH
Control
Q1
SS/TR
22 nF
CLK
RTSEL
100 µF 100 µF 100 µF
10 V
10 V
10 V
PWRGD_PU
PWRGD
PWRGD
VERSA-COMP
VADJ
RT
53.6 kΩ
VOUT = 5V
VOUT
PVIN
5.11 kΩ
AGND
PGND
Figure 30. LMZ34202 Typical Schematic
8.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 13 as the input parameters. For the complete design
procedures start with the procedures for the basic application above as well as the procedures listed below.
Table 13. Design Example Parameters
DESIGN PARAMETER
VALUE
Input Voltage PVIN
24 V typical
Output Voltage VOUT
5.0 V
Output Current Rating
2A
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Table 13. Design Example Parameters (continued)
DESIGN PARAMETER
VALUE
Operating Frequency
750 kHz
Inhibit Control
Yes
Power Good Signal
Yes
Slow Start Time
10 ms
Output Capacitance
300 µF
8.2.3 Detailed Design Procedure
8.2.3.1 Switching Frequency
To adjust the switching frequency place a resistor between the RT pin (pin 9) and AGND. Refer to Table 3 to
select the required value for RRT resistor. To set the switching frequency to 750 kHz, the value for RRT is 53.6
kΩ, selected from Table 3.
8.2.3.2 Power Good
The PWRGD pin is an open drain output. The LMZ34202 includes an internal 100 kΩ pullup resistor between the
PWRGD pin and the PWRGD_PU pin. Connecting the PWRGD_PU pin to a pullup voltage allows use of the
PWRGD signal without adding an additional component. In this example, the 5-V output is used as the pullup
voltage.
8.2.3.3 Inhibit Control
To control the turn ON and OFF of the LMZ34202, an open-drain and collector device is recommended. The
open-drain and collector device must be rated for the maximum voltage applied to PVIN. A pull-up resistor is
required between the INH/UVLO pin and PVIN. Place a 100-kΩ resistor between the INH/UVLO pin and the
PVIN pin.
8.2.3.4 VERSA-COMP
The Versa-Comp feature of the LMZ34202 configures the internal compensation based on the output voltage.
From Table 8, the required Versa-Comp configuration for a 5-V output is to connect the VERSA-COMP pin to the
VADJ pin.
8.2.3.5 VBSEL
The VBSEL pin allows the user to select the input source to the internal power circuitry to improve efficiency. For
output voltages ≥ 4.5 V, connect this pin to VOUT. For output voltages < 4.5 V, connect this pin to AGND.
8.2.3.6 Soft-Start Capacitors
When the SS/TRK pin remains floating the LMZ34202 implements a typical soft-start time of 4.1 ms. In order to
increase the slow start time, an external slow start capacitor, CSS must be placed between the SS/TRK pin and
AGND. Select a value for CSS from Table 11.
For the desired soft-start time of 10 ms, a soft-start capacitor value of 22 nF is selected from Table 11.
8.2.3.7 Input Capacitors
For this design, a 10-μF ceramic capacitor plus a 100-µF aluminum electrolytic capacitor, both rated for 50 V are
used for the input decoupling capacitors.
8.2.3.8 Output Capacitors
The maximum allowable output capacitance for a 5-V output is 350 μF of capacitance. At least 64 µF of
capacitance must be ceramic type. For this design, 3× 100-μF, X5R dielectric ceramic capacitors rated for 10 V
are used for the output capacitors.
24
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9 Power Supply Recommendations
The LMZ34202 is designed to operate from an input voltage supply range between 4.5 V and 42 V. This input
supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail should be low enough that an input current transient does not cause a high
enough drop at the LMZ34202 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LMZ34202 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is 47 µF or the
typical amount of electrolytic capacitance is 100 μF.
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10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. The following guidelines will help users design a PCB with the best power conversion performance,
thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 31 thru
Figure 34, shows a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another. The connection is made internal to the device.
• Place RSET, RRT, and CSS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
10.2 Layout Example
26
Figure 31. Typical Top-Layer Layout
Figure 32. Typical Layer-2 Layout
Figure 33. Typical Layer-3 Layout
Figure 34. Typical Bottom-Layer Layout
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10.3 EMI
The LMZ34202 is compliant with EN55022 Class B radiated emissions. Figure 35 Figure 36 show typical
examples of radiated emissions plots for the LMZ34202 operating from 24 V. Both graphs include the plots of the
antenna in the horizontal and vertical positions.
Figure 35. Radiated Emissions (EN55022 Class B)
24-V Input, 5-V Output, 2-A Load, 250 kHz
Figure 36. Radiated Emissions (EN55022 Class B)
24-V Input, 5-V Output, 2-A Load, 500 kHz
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ34202 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.1.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
28
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11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LMZ34202RVQR
B3QFN
RVQ
43
500
330.0
24.4
10.35
10.35
4.6
16.0
24.0
Q2
LMZ34202RVQT
B3QFN
RVQ
43
250
330.0
24.4
10.35
10.35
4.6
16.0
24.0
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
30
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ34202RVQR
B3QFN
RVQ
43
500
383.0
353.0
58.0
LMZ34202RVQT
B3QFN
RVQ
43
250
383.0
353.0
58.0
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMZ34202RVQR
ACTIVE
B3QFN
RVQ
43
500
RoHS Exempt
& Green
NIPDAU
Level-3-245C-168 HR
-40 to 105
LMZ34202
LMZ34202RVQT
ACTIVE
B3QFN
RVQ
43
250
RoHS & Green
NIPDAU
Level-3-245C-168 HR
-40 to 105
LMZ34202
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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