LMZM33602EVM

User's Guide SNVU565 – August 2017 LMZM33603 and LMZM33602 EVM User's Guide The LMZM33603 and LMZM33602 evaluation modules (EVM) are designed as easy-to-use platforms that facilitate an extensive evaluation of the features and performance of the LMZM33603 and LMZM33602 power modules. This guide provides information on the correct usage of the EVMs and an explanation of the numerous test points on the board. 1 Description This EVM features the LMZM33603/LMZM33602 synchronous buck power module configured for operation with typical 4-V to 36-V input bus applications. The output voltage can be set to one of four popular values by using a configuration jumper. Similarly, the switching frequency can be set to one of four values with a jumper. The full output current rating of the device can be supplied by the EVM. Input and output capacitors are included on the board to accommodate the entire range of input and output voltages. Monitoring test points are provided to allow measurement of efficiency, power dissipation, input ripple, output ripple, line and load regulation, and transient response. Control test points and component footprints are provided for use of the EN, UVLO, PGOOD, and SYNC features of the LMZM33603/LMZM33602 device. The EVM uses a recommended PCB layout that maximizes thermal performance and minimizes output ripple and noise. 2 Getting Started Figure 1 highlights the user interface items associated with the EVM. The VIN Power terminal block (J1) is used for connection to the host input supply and the VOUT Power terminal block (J2) is used for connection to the load. These terminal blocks can accept up to 16-AWG wire. Figure 1. LMZM33603/LMZM33602EVM User Interface SNVU565 – August 2017 Submit Documentation Feedback LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated 1 Test Point Descriptions www.ti.com The S+ and S- test points for both VIN and VOUT, located near the power terminal blocks are intended to be used as voltage monitoring points where voltmeters can be connected to measure VIN and VOUT. Do not use these S+ and S- monitoring test points as the input supply or output load connection points. The PCB traces connecting to these test points are not designed to support high currents. The VIN Scope (J3) and VOUT Scope (J4) test points can be used to monitor VIN and VOUT waveforms with an oscilloscope. These test points are intended for use with un-hooded scope probes outfitted with a low-inductance ground lead (ground spring) mounted to the scope probe barrel. The two sockets of each test point are on 0.1 inch centers. The scope probe tip should be connected to the socket labeled VIN or VOUT, and the scope ground lead should be connected to the socket labeled PGND. The control test points located to the right of the device are made available to test the features of the device. Refer to the Test Points Descriptions section of this guide for more information on the individual control test points. The VOUT SELECT jumper (J6) and Fsw SELECT jumper (J5) are provided for selecting the desired output voltage and appropriate switching frequency. Before applying power to the EVM, ensure that the jumpers are present and properly positioned for the intended output voltage. Refer to Table 1 for the recommended jumper settings. Always remove input power before changing the jumper settings. Table 1. Output Voltage and Switching Frequency Jumper Settings 3 VOUT Select Fsw Select 2.5 V 250 kHz 3.3 V 300 kHz 5.0 V 450 kHz 12 V 900 kHz Test Point Descriptions Wire-loop test points and two scope probe test points have been provided as convenient connection points for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. A description of each test point follows: Table 2. Test Point Descriptions (1) VIN S+ Input voltage monitor. Connect the positive lead of a DVM to this point for measuring efficiency. VIN S– Input voltage monitor. Connect the negative lead of a DVM to this point for measuring efficiency. VOUT S+ Output voltage monitor. Connect the positive lead of a DVM to this point for measuring efficiency, line regulation, and load regulation. VOUT S– Output voltage monitor. Connect the negative lead of a DVM to this point for measuring efficiency, line regulation, and load regulation. AGND Analog ground test point. PGND Power ground test point. VIN Scope (J1) Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple voltage. VOUT Scope (J2) Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output ripple voltage and transient response. PGOOD Monitors the power good signal of the device. This is an open drain signal. A pull-up to a 5.1–V zener diode clamp (D1 & R10) is present on this EVM. EN Enable test point. Connect this test point to PGND to disable the device. A 100 kΩ pull-up resistor (R16) to VIN is present on the EVM. Leave this test point open to enable the device. SYNC Synchronization input test point. An AC coupling capacitor (C17) is present on the EVM between this test point and the SYNC pin of the device. A 49.9 Ω termination resistor (R17) is present between this test point and PGND. An external clock signal can be applied to this point to synchronize the device to an appropriate frequency. (1) 2 Refer to the LMZM33603/LMZM33602 datasheet for absolute maximum ratings associated with above features. LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated SNVU565 – August 2017 Submit Documentation Feedback Operation Notes www.ti.com 4 Operation Notes In order to operate the EVM, apply an input voltage in the range of 4.0 V to 36 V. The UVLO threshold of the EVM is typically 3.6 V, with 0.3 V of hysteresis. The input voltage must be above the UVLO threshold in order for the device to startup. The UVLO voltage threshold can be adjusted to a higher voltage by adjusting the UVLO resistors on the EVM, R9 and R16. Refer to the LMZM33603/LMZM33602 datasheet for further information on the input voltage range and UVLO operation. The VOUT SELECT jumper (J6) allows easy evaluation of four common output voltages by simply connecting a jumper. Table 1 lists the VOUT SELECT voltages and the recommended switching frequency selections. The selection of jumper J6 connects the appropriate RFBT resistor and CFF capacitor (if required). If evaluation of another output voltage is desired, jumper J6 should be left open and components R2 and C18 can be populated with the required values. Refer to the LMZM33603 or LMZM33602 datasheet for the RFBT and CFF values. The FSW SELECT jumper (J5) allows the user to easily change the switching frequency for evaluation. Table 1 lists the recommended switching frequencies for each of the VOUT selections. These recommendations cover operation over a wide range of input voltage and output load conditions. Several factors such as duty cycle, minimum on-time, minimum off-time, and current limit influence selection of the appropriate switching frequency. In some applications, other switching frequencies might be used for particular output voltages, depending on the above factors. Refer to the LMZM33603 or LMZM33602 datasheet for further information on switching frequency selection, including synchronization. The EVM includes the required amount of input and output capacitors to accommodate most input and output voltage conditions. The actual capacitance required will depend on the input and output voltage conditions of the particular application, along with the desired transient response. If evaluation of the EVM with additional capacitance is desired, additional capacitor footprints are available on the EVM. Refer to the LMZM33603 or LMZM33602 datasheet for further information on the minimum required input and output capacitance. SNVU565 – August 2017 Submit Documentation Feedback LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated 3 Performance Data 5 www.ti.com Performance Data Figure 2 through Figure 5 demonstrate the LMZM33603EVM performance. For more data regarding the LMZM33603 or LMZM33602 please see the product data sheet. 16.0 95 15.0 90 14.0 Output Ripple Voltage (mV) 100 Efficiency (%) 85 80 75 70 65 VOUT, fSW 12 V, 900 kHz 5.0 V, 450 kHz 3.3 V, 300 kHz 2.5 V, 250 kHz 60 55 50 0.0 4 0.5 1.0 1.5 2.0 Output Current (A) 2.5 13.0 VOUT, fSW 2.5 V, 250 kHz 3.3 V, 300 kHz 12 V, 900 kHz 5.0 V, 450 kHz 12.0 11.0 10.0 9.0 8.0 7.0 3.0 6.0 0.0 0.5 D003 1.0 1.5 2.0 Output Current (A) 2.5 Figure 2. Efficiency (Vin = 24V) Figure 3. Ripple Voltage (Vin = 24V) Figure 4. EN Start-up Waveforms Figure 5. EN Shut-down Waveforms LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated 3.0 D011 SNVU565 – August 2017 Submit Documentation Feedback Bill of Materials (BOM) www.ti.com 6 Bill of Materials (BOM) Table 3 includes the BOM for both the LMZM33602EVM (02) and LMZM33603EVM (03). Table 3. EVM Bill of Materials Designator Quantity Package Reference Value Description Part Number Manufacturer 2 4.7µF CAP, CERM, 4.7 µF, 50 V, +/- 10%, X7R, 1210 1 0.1µF CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R, 0603 1210 GRM32ER71H475KA88L MuRata 0603 GRM188R71H104KA93D MuRata 4 4 22µF CAP, CERM, 22 µF, 25 V, +/- 10%, X7R, 1210 1210 GRM32ER71E226KE15L MuRata C11 1 1 C12 1 1 220pF CAP, CERM, 220 pF, 100 V, +/- 5%, C0G/NP0, 0603 0603 GRM1885C2A221JA01D MuRata 150pF CAP, CERM, 150 pF, 100 V, +/- 5%, C0G/NP0, 0603 0603 GRM1885C2A151JA01D C13 1 1 MuRata 100pF CAP, CERM, 100 pF, 100 V, +/- 5%, C0G/NP0, 0603 0603 GRM1885C2A101JA01D MuRata C16 1 C17 1 1 47µF CAP, AL, 47 µF, 100 V, +/- 20%, 0.14 ohm, TH D8xL15mm EKZN101ELL470MH15D Chemi-Con 1 1000pF 0603 GRM188R71H102KA01D D1 MuRata 1 1 5.1V Diode, Zener, 5.1 V, 500 mW, SOD-123 SOD-123 DDZ9689-7 Diodes Inc. J1, J2 2 2 Socket Strip, 2x1, 100mil, Black, Tin, TH Socket Strip, 100mil, 2pin 310-43-102-41-001000 Mill-Max J3, J4 2 2 Header, 100mil, 4x2, Tin, TH Header, 4x2, 100mil, Tin PEC04DAAN Sullins Connector Solutions R1 1 1 10.0k RES, 10.0 k, 1%, 0.063 W, 0402 0402 CRCW040210K0FKED Vishay-Dale R5 1 1 162k RES, 162 k, 1%, 0.1 W, 0603 0603 CRCW0603162KFKEA Vishay-Dale R6 1 1 133k RES, 133 k, 1%, 0.1 W, 0603 0603 CRCW0603133KFKEA Vishay-Dale R7 1 1 88.7k RES, 88.7 k, 1%, 0.1 W, 0603 0603 CRCW060388K7FKEA Vishay-Dale R8 1 1 44.2k RES, 44.2 k, 1%, 0.1 W, 0603 0603 CRCW060344K2FKEA Vishay-Dale R10 1 1 49.9k RES, 49.9 k, 1%, 0.063 W, 0402 0402 CRCW040249K9FKED Vishay-Dale R11 1 1 15.0k RES, 15.0 k, 1%, 0.1 W, 0603 0603 CRCW060315K0FKEA Vishay-Dale R12 1 1 23.2k RES, 23.2 k, 1%, 0.1 W, 0603 0603 CRCW060323K2FKEA Vishay-Dale R13 1 1 40.2k RES, 40.2 k, 1%, 0.1 W, 0603 0603 CRCW060340K2FKEA Vishay-Dale R14 1 1 110k RES, 110 k, 1%, 0.1 W, 0603 0603 CRCW0603110KFKEA Vishay-Dale R15 1 1 0 RES, 0, 5%, 0.1 W, 0603 0603 CRCW06030000Z0EA Vishay-Dale R16 1 1 100k RES, 100 k, 1%, 0.063 W, 0402 0402 CRCW0402100KFKED Vishay-Dale R17 (or R4) 1 1 49.9 RES, 49.9, 1%, 1 W, 2512 2512 CRCW251249R9FKEG Vishay-Dale TB1, TB2 2 2 Terminal Block, 5.08 mm, 2x1, Brass, TH 2x1 5.08 mm Terminal Block ED120/2DS On-Shore Technology TP1, TP2 2 2 Test Point, Multipurpose, Red, TH Multipurpose Testpoint Red 5010 Keystone 02 03 C1, C2 2 C3 1 C4, C5, C6, C7 CAP, CERM, 1000 pF, 50 V, +/- 10%, X7R, 0603 SNVU565 – August 2017 Submit Documentation Feedback LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated 5 Bill of Materials (BOM) www.ti.com Table 3. EVM Bill of Materials (continued) Part Number Manufacturer Test Point, Multipurpose, Black, TH Multipurpose Testpoint Black 5011 Keystone 3 Test Point, Multipurpose, White, TH Multipurpose Testpoint White 5012 Keystone 1 0 LMZM33602 RLR0018A (B2QFN-18) RLR0018A LMZM33602RLR Texas Instruments 0 1 LMZM33603 RLR0018A (B2QFN-18) RLR0018A LMZM33603RLR Texas Instruments SH-P1, SH-P2 2 2 Shunt, 2mm, Gold plated, Black 2mm Shunt, Closed Top 2SN-BK-G Samtec C8, C9 0 0 CAP, CERM, 1210 C10 0 0 CAP, Tantalum Polymer, 7343-20 SMD C14, C15 0 0 CAP, CERM, 1210 1210 C18 0 0 CAP, CERM, 0402 0402 R2 0 0 RES, 0402 0402 R3 0 0 RES, 0402 0402 R9 0 0 RES, 0402 0402 TP15 0 0 TEST POINT. No entry in BOM. N/A 02 03 TP3, TP4, TP5, TP6 4 4 TP9, TP10, TP11 3 U1 6 Quantity Package Reference Designator Value 1x2 Description 1210 7343-20 LMZM33603 and LMZM33602 EVM User's Guide SNVU565 – August 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Schematic www.ti.com 7 Schematic Figure 6 is the schematic for this EVM. VIN VOUT TP1 TP2 VIN VOUT TB1 J1 VIN PGND VIN PGND C16 47µF TP4 C15 C2 4.7µF C14 TB2 J2 C3 0.1µF 0603 C1 4.7µF C4 22µF C5 22µF C6 22µF C7 22µF C8 VOUT C9 C10 VOUT PGND PGND TP6 PGND PGND NT1 Net-Tie R16 100k TP7 R15 0 C17 TP11 SYNC R17 49.9 2512 TP3 TP8 1000pF 0603 2 4 6 8 SYNC PGND R10 49.9k J4 VOUT SELECT 1 3 5 7 TP9 EN U1 2.5V R9 VIN D1 5.1V 4 PGND 5 VIN VOUT VOUT VOUT 3.3V TP10 PGOOD TP5 R5 162k 0603 R7 88.7k 0603 R6 133k 0603 300kHz R8 44.2k 0603 DNC DNC PGOOD 17 PGOOD EN 2 EN/SYNC 3 RT 1 AGND RT AGND R3 5.0V PGND R2 12 13 PGND 12V 6 VOUT 7 8 SW SW SW FB PGND PGND PGND 9 10 11 SW TP15 C18 R11 15.0k 0603 C11 220pF R12 0603 23.2k C12 150pF R13 0603 40.2k C13 100pF R14 0603 110k 16 FB R1 10.0k 0402 14 15 18 450kHz AGND 900kHz 1 3 5 7 250kHz AGND Fsw J3 AGND PGND 2 4 6 8 SELECT AGND Copyright © 2017, Texas Instruments Incorporated Figure 6. LMZM33603/LMZM33602EVM Schematic SNVU565 – August 2017 Submit Documentation Feedback LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated 7 PCB Layout 8 www.ti.com PCB Layout Figure 7 through Figure 12 show the PCB layers of the LMZM33603/LMZM33602EVM. Figure 7. Topside Component Layout (Top View) Figure 8. Topside Copper (Top View) 8 LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated SNVU565 – August 2017 Submit Documentation Feedback PCB Layout www.ti.com Figure 9. Layer 2 Copper (Top View) Figure 10. Layer 3 Copper (Top View) SNVU565 – August 2017 Submit Documentation Feedback LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated 9 PCB Layout www.ti.com Figure 11. Bottom-Side Copper (Top View) Figure 12. Bottom-Side Component Layout (Bottom View) 10 LMZM33603 and LMZM33602 EVM User's Guide Copyright © 2017, Texas Instruments Incorporated SNVU565 – August 2017 Submit Documentation Feedback IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications (and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice. This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services. These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation modules, and samples (http://www.ti.com/sc/docs/sampterms.htm). Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated