LP2985-30DBVR

参考文献 LP2985, LP2985A ZHCSLK4S – JULY 2004 – REVISED MAY 2025 具有关断功能的 LP2985 150mA 低噪声低压降稳压器 1 特性 3 说明 • VIN 范围（新芯片）：2.5V 至 16V • VOUT 范围（新芯片）： – 1.2V 至 5.0V（固定值，100mV 阶跃） • VOUT 精度： – A 级（旧芯片）为 ±1% – 标准级（旧芯片）为 ±1.5% – ±0.5%（新芯片） • 在整个负载和温度范围内的输出精度为 ±1%（新芯 片） • 输出电流：高达 150mA • 低 IQ（新芯片）：ILOAD = 0mA 时为 71μA • 低 IQ（新芯片）：ILOAD = 150mA 时为 750μA • 关断电流： – 0.01μA（典型值，旧芯片） – 1.12μA（典型值，新芯片） • 低噪声：30μVRMS（具有 10nF 旁路电容器） • 输出电流限制和热保护 • 与 2.2µF 陶瓷电容器搭配使用时可保持稳定（新芯 片） • 高 PSRR：1kHz 时 70dB，1MHz 时 40dB （新芯 片） • 工作结温：-40°C 至 +125°C • 封装：5 引脚 SOT-23 (DBV) LP2985 是一款固定输出、宽输入、低噪声、低压降稳 压器，支持 2.5V 至 16V（对于新芯片）的输入电压范 围和高达 150mA 的负载电流。LP2985 支持 1.2V 至 5.0V 的输出范围（对于新芯片）。 此外，LP2985（新芯片）在整个负载和温度范围内具 有 ±1% 的输出精度，可满足低压微控制器 (MCU) 和 处理器的需求。 30µVRMS 的低输出噪声（带 10nF 旁路电容器）以及 1kHz 时大于 70dB 和 1MHz 时大于 40dB 的宽带宽 PSRR 性能有助于衰减上游直流/直流转换器的开关频 率，并尽可能减少后置稳压器滤波。 在新芯片中，内部软启动机制可减小启动期间的浪涌电 流，从而最大限度降低输入电容。还包括标准保护特 性，例如过流和过热保护。 LP2985 采用 5 引脚、2.9mm × 2.8mm SOT-23 (DBV) 封装。 封装信息 封装(1) 器件型号 LP2985 (1) (2) 封装尺寸(2) DBV（SOT-23，5） 2.9mm × 2.8mm 如需更多信息，请参阅机械、封装和可订购信息。 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。 2 应用 洗衣机和烘干机 陆地移动无线电 有源天线系统 mMIMO 无线电动工具 电机驱动器和控制板 450 Iout 1mA 10mA 400 350 Dropout (mV) • • • • • VIN VOUT IN 50mA 150mA OUT LP2985 300 CIN COUT ON/ OFF 250 200 BYPASS GND GND 10 nF 150 GND GND 100 GND 50 0 -75 典型应用电路 -50 -25 0 25 50 75 Te mperature (°C) 100 125 150 压降电压与温度间的关系（新芯片） 本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认 准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。 English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 Table of Contents 1 特性................................................................................... 1 2 应用................................................................................... 1 3 说明................................................................................... 1 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 ESD Ratings............................................................... 4 5.3 Recommended Operating Conditions.........................4 5.4 Thermal Information....................................................5 5.5 Electrical Characteristics.............................................5 5.6 Typical Characteristics................................................ 8 6 Detailed Description......................................................15 6.1 Overview................................................................... 15 6.2 Functional Block Diagrams....................................... 15 6.3 Feature Description...................................................16 6.4 Device Functional Modes..........................................18 2 7 Application and Implementation.................................. 20 7.1 Application Information............................................. 20 7.2 Typical Application.................................................... 24 7.3 Power Supply Recommendations.............................29 7.4 Layout....................................................................... 29 8 Device and Documentation Support............................30 8.1 Device Support......................................................... 30 8.2 接收文档更新通知..................................................... 30 8.3 支持资源....................................................................30 8.4 Trademarks............................................................... 30 8.5 静电放电警告............................................................ 30 8.6 术语表....................................................................... 30 9 Revision History............................................................ 31 10 Mechanical, Packaging, and Orderable Information.................................................................... 31 Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 4 Pin Configuration and Functions VIN 1 GND 2 ON/OFF 3 5 VOUT 4 BYPASS 图 4-1. DBV Package, 5-Pin SOT-23 (Top View) 表 4-1. Pin Functions PIN NAME NO. TYPE DESCRIPTION BYPASS 4 I/O BYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the Recommended Operating Conditions section for more information. GND 2 — Ground ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the Electrical Characteristics table. Tie this pin to VIN if unused. VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the Input and Output Capacitor Requirements section for more information. VOUT 5 O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground.(1) See the Input and Output Capacitor Requirements section for more information. (1) The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 3 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) VIN VOUT VBYPASS VON/OFF Current MAX –0.3 16 Continuous input voltage range (for new chip) –0.3 18 Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) BYPASS pin voltage range (for new chip) –0.3 3 ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 Maximum output Temperature (1) MIN Continuous input voltage range (for legacy chip) Internally limited UNIT V A Operating junction, TJ –55 150 Storage, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages with respect to GND. (2) 5.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge VALUE (Legacy Chip) VALUE (New Chip) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 ±3000 Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500 ±1000 UNIT V JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. 5.3 Recommended Operating Conditions MIN VIN VOUT VBYPASS VON/OFF IOUT CIN (1) MAX 2.2 16 Supply input voltage (for new chip) 2.5 16 Output voltage (for legacy chip) 1.2 10.0 Output voltage (for new chip) 1.2 5.0 Bypass voltage 1.2 UNIT V V V Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 Output current 0 150 Input capacitor 1 V mA μF Output capacitance (for legacy chip) 2.2 4.7 Output capacitance (for new chip) (1) 1 2.2 COUT ESR(3) Output capacitor ESR (for new chip)(2) 0 1 Ω TJ Operating junction temperature –40 125 °C COUT (1) (2) 4 NOM Supply input voltage (for legacy chip) 200 μF All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 μF minimum for stability. Details related to supported ESR range for the legacy chip are available in Recommended Capacitors for the Legacy Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn (3) ZHCSLK4S – JULY 2004 – REVISED MAY 2025 Maximum supported ESR range for new chip is 1Ω. For output capacitor with higher ESR values, place a low ESR MLCC capacitor with value of 100nF, close to the output pin of the LDO. 5.4 Thermal Information THERMAL METRIC (2) (1) Legacy Chip New Chip DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS UNIT RθJA Junction-to-ambient thermal resistance 205.4 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.8 77.9 °C/W RθJB Junction-to-board thermal resistance 46.7 47.2 °C/W ψJT Junction-to-top characterization parameter 8.3 15.9 °C/W ψJB Junction-to-board characterization parameter 46.3 46.9 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application note. 5.5 Electrical Characteristics specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS IL = 1 mA 1 mA ≤ IL ≤ 50 mA ∆VOUT Output voltage tolerance 1 mA ≤ IL ≤ 150 mA 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C MIN Legacy chip (standard grade) –1.5 1.5 Legacy chip (A grade) –1.0 1.0 New chip –0.5 0.5 Legacy chip (standard grade) –2.5 2.5 Legacy chip (A grade) –1.5 1.5 New chip –0.5 0.5 Legacy chip (standard grade) –3.0 3.0 Legacy chip (A grade) –2.5 2.5 New chip –0.5 0.5 Legacy chip (standard grade) –3.5 3.5 Legacy chip (A grade) –2.5 2.5 –1 1 Legacy chip (standard grade) –4.0 4.0 Legacy chip (A grade) –3.5 3.5 –1 1 New chip 1 mA ≤ IL ≤ 150 mA, –40°C ≤ TJ ≤ 125°C New chip Copyright © 2025 Texas Instruments Incorporated TYP MAX UNIT % 提交文档反馈 5 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.5 Electrical Characteristics （续） specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER ΔVOUT(Δ VIN) TEST CONDITIONS VO(NOM) + 1 V ≤ VIN ≤ 16 V Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C IOUT = 0 mA IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C IOUT = 1 mA IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C IOUT = 10 mA VIN - VOUT Dropout voltage(1) IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C IOUT = 50 mA IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C IOUT = 150 mA IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C IOUT = 0 mA IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C IGND GND pin current IOUT = 1 mA IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C IOUT = 10 mA IGND GND pin current IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C 6 MIN TYP MAX UNIT Legacy chip 0.007 0.014 New chip 0.002 0.014 Legacy chip 0.007 0.032 New chip 0.002 0.032 Legacy chip 1 3 New chip 1 2.75 Legacy chip 5 New chip 3 Legacy chip New chip 7 10 11.5 14 Legacy chip 15 New chip 17 Legacy chip 40 60 New chip 98 115 Legacy chip 90 New chip %/V mV 148 Legacy chip 120 150 New chip 120 145 Legacy chip 225 New chip 184 Legacy chip 280 350 New chip 180 198 Legacy chip 575 New chip 254 Legacy chip 65 95 New chip 69 95 Legacy chip 125 New chip 123 Legacy chip 75 110 New chip 78 110 Legacy chip 170 New chip 140 Legacy chip 120 220 New chip 175 210 Legacy chip 400 New chip 250 Legacy chip 350 600 New chip 380 440 µA µA IGND GND pin current IOUT = 50 mA IGND GND pin current IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 900 µA IGND GND pin current IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C New chip 650 µA IGND GND pin current IOUT = 150 mA Legacy chip 850 1200 µA IGND GND pin current IOUT = 150 mA New chip 765 µA 890 µA Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.5 Electrical Characteristics （续） specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IGND GND pin current IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2000 µA IGND GND pin current IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C New chip IGND GND pin current VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 1060 µA 0.08 µA IGND GND pin current VON/OFF < 0.3 V, VIN = 16 V New chip IGND GND pin current VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 85°C Legacy chip 1.25 1.75 µA 0 1 µA IGND GND pin current VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 85°C New chip 1.12 2.25 µA IGND GND pin current VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.01 2 µA IGND VUVLO+ GND pin current VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C New chip 1.12 2.75 µA Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C Low = Output OFF VON/OFF ON/OFF input voltage New chip 0.130 Legacy chip 0.55 New chip 0.72 VON/OFF = 0 V VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C ION/OFF ON/OFF input current VON/OFF = 5 V VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) IO(SC) Short output current RL = 0 Ω (steady state) ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Vn Tsd+ Tsd(1) Output noise voltage Thermal shutdown threshold 0.15 1.4 New chip 0.85 1.6 Legacy chip 0.01 New chip 0.42 Legacy chip New chip Legacy chip New chip -1 µA -0.9 µA µA 0.011 Legacy chip New chip Legacy chip 300 350 New chip 300 350 Legacy chip 400 New chip 375 Legacy chip 45 New chip 78 Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT New chip = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA 30 New chip µA 5 30 Reset, temperature decreasing V 1.6 Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT Legacy chip = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Shutdown, temperature increasing V 0.15 Legacy chip High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ Legacy chip TJ ≤ 125°C New chip ON/OFF input current V Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ Legacy chip TJ ≤ 125°C New chip High = Output ON ION/OFF 1.9 µA 15 µA 2.20 µA 170 150 mA dB µVRM S °C Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 7 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.6 Typical Characteristics at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 3.345 10.20 VI = 11 V 10.15 VO = 10 V 3.335 CO = 4.7 µF Output Voltage − (V) Output Voltage – V CI = 1 µF 10.10 IO = 1 mA 10.05 10.00 9.95 VI = 4.3 V VO = 3.3 V Ci = 1 mF Co = 4.7 mF IO = 1 mA 3.325 3.315 3.305 9.90 9.85 -50 -25 0 25 50 75 100 125 3.295 −50 150 −25 Temperature – °C 0 25 50 75 100 125 150 Temperature − (°C) 图 5-1. Output Voltage vs Temperature for Legacy Chip 图 5-2. Output Voltage vs Temperature for Legacy Chip 3.315 Output Voltage (V) 3.31 VI = 4.3 V VO = 3.3 V Iout = 1mA CO = 4.7uF 3.305 3.3 3.295 3.29 3.285 3.28 -75 -50 -25 0 25 50 Te mp C 75 100 125 150 VIN = 4.3 V, VOUT = 3.3 V (for new chip) 图 5-3. Output Voltage vs Temperature for New Chip 图 5-4. Dropout Voltage vs Temperature for Legacy Chip 450 400 1mA 10mA 200 175 300 250 200 150 125 100 75 50 50 25 -55 °C -40 °C 0 °C Te mperature 25 °C 85 °C 125 °C 150 °C 0 -50 -25 0 25 50 75 Te mperature (°C) 100 125 150 图 5-5. Dropout Voltage vs Temperature for New Chip 8 150 100 0 -75 VO = 3.3 V CO = 4.7uF 225 50mA 150mA Dropout (mV) Dropout (mV) 350 250 Iout 0 20 40 60 80 100 IOUT (mA) 120 140 160 图 5-6. Dropout Voltage vs Load Current for New Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 1 1.5 0.6 150 °C 0.4 0.2 0 -0.2 Te mperature -55C 85C -40C 125C 0C 150C 25C VO = 3.3 V Iout= 1mA CO = 4.7uF 1 Line Regulation (mV) 0.5 0 -0.5 -1 -0.4 -1.5 -0.6 -2 -0.8 0 20 40 60 80 100 IOUT (mA) 120 140 图 5-7. Output Regulation vs Load Current for New Chip Short-Circuit Current − (A) 0.4 6 8 10 VIN (V) 12 5 VI = 6 V VO = 3.3 V Ci = 1 mF Cbyp = 0.01 mF 3 0.3 0.25 0.2 0.15 16 6000 VO I SC 4 0.35 14 图 5-8. Output Regulation vs Input Voltage for New Chip Output Voltage - (V) 0.5 0.45 4 160 5400 4800 2 4200 1 3600 0 3000 -1 2400 VIN = 6 V Cbyp = 10 nF VO = 3.3 V -2 -3 1800 1200 0.1 -4 600 0.05 -5 0 0 −500 -6 0 500 1000 Time − (ms) 1500 0 2000 200 400 600 200s/div 800 Output Current - (mA) Load Regulation (mV) Te mperature -55 °C 25 °C -40 °C 85 °C 0 °C 125 °C VI = 4.3 V VO = 3.3 V CO = 4.7uF 0.8 -600 1000 VIN = 6 V 0.5 VI = 16 V VO = 3.3 V Ci = 1 mF Cbyp = 0.01 mF 0.45 0.4 0.35 0.3 0.25 0.2 0.15 6000 VO I SC 4 3 Output Voltage - (V) Short-Circuit Current − (A) 图 5-10. Short-Circuit Current vs Time for New Chip 5 5400 4800 2 4200 1 3600 0 3000 -1 2400 VIN = 16 V Cbyp = 10 nF VO = 3.3 V -2 -3 1800 1200 0.1 -4 600 0.05 -5 0 0 −100 -6 100 300 500 Time − (ms) 700 图 5-11. Short-Circuit Current vs Time for Legacy Chip 0 200 400 600 200s/div 800 Output Current - (mA) 图 5-9. Short-Circuit Current vs Time for Legacy Chip -600 1000 图 5-12. Short-Circuit Current vs Time for New Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 9 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 380 320 VO = 3.3 V 360 300 Current Limit (mA) ISC − (mA) 340 280 260 240 320 300 VI = 4.3 V 280 260 240 220 -55 °C -40 °C 0 °C 220 150 °C 200 200 0 0.5 1 1.5 2 2.5 Output Voltage − (V) 3 0 3.5 图 5-13. Short-Circuit Current vs Output Voltage for Legacy Chip 0.5 1 1.5 2 VOUT (V) 2.5 3 3.5 图 5-14. Short-Circuit Current vs Output Voltage for New Chip 352 1200 VO = 3.3 V Cbyp = 10 nF 1100 VI = 4.3 V CO = 4.7uF 1000 Ground Pin Current − mA 351 Current Limit (mA) Te mperature 25 °C 85 °C 125 °C 350 349 900 800 700 600 500 400 300 200 100 348 -55 -25 5 35 65 Te mperature (C) 95 125 0 150 图 5-15. Short-Circuit Current vs Temperature for New Chip 60 80 100 Load Current − mA 120 140 160 100 VI = 4.3 V VO = 3.3 V CO = 4.7uF 1000 900 VI = 5 V VO = 3.3 V Co = 10 mF Cbyp = 0 nF 90 80 800 700 600 500 400 Te mperature -55 °C 85 °C -40 °C 125 °C 0 °C 150 °C 25 °C 300 200 100 0 Ripple Rejection − (dB) 1100 IGND (A) 40 图 5-16. Ground Pin Current vs Load Current for Legacy Chip 1200 70 50 mA 1 mA 60 50 40 150 mA 30 20 10 0 0 20 40 60 80 IOUT 100 120 140 160 10 100 1k 10k 100k 1M Frequency − (Hz) 图 5-17. Ground Pin Current vs Load Current for New Chip 10 20 0 图 5-18. Ripple Rejection vs Frequency for Legacy Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 120 100 1 mA 150 mA 50 mA 110 80 90 Ripple Rejection − (dB) Ripple Rejection - (dB) 100 80 70 60 50 40 30 VIN = 5 V V0 = 3.3 V C0 = 10 uF Cbyp = 0 nF 70 1 mA 60 50 mA 50 40 30 150 mA 20 20 10 10 0 101 VI = 3.7 V VO = 3.3 V Co = 10 mF Cbyp = 0 nF 90 102 103 104 105 Frequency - (Hz) 106 0 107 10 100 1k 10k 100k 1M Frequency − (Hz) VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF 图 5-19. Ripple Rejection vs Frequency for New Chip 图 5-20. Ripple Rejection vs Frequency for Legacy Chip 120 100 1 mA 150 mA 50 mA 110 80 90 80 70 60 50 40 30 70 1 mA 60 50 40 50 mA 30 20 20 150 mA 10 10 0 1x101 VI = 5 V VO = 3.3 V Co = 4.7 mF Cbyp = 10 nF 90 Ripple Rejection − (dB) Riple Rejection - (dB) 100 1x102 1x103 1x104 1x105 Frequency - (Hz) 1x106 0 1x107 10 100 1k 10k 100k 1M Frequency − (Hz) VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF 图 5-21. Ripple Rejection vs Frequency for New Chip 图 5-22. Ripple Rejection vs Frequency for Legacy Chip 120 100 1 mA 150 mA 50 mA 110 90 80 70 60 50 40 30 VIN = 5 V V0 = 3.3 V C0 = 4.7 uF Cbyp = 10 nF 80 70 40 10 1x106 1x107 图 5-23. Ripple Rejection vs Frequency for New Chip 100 mA 30 10 1x103 1x104 1x105 Frequency - (Hz) 10 mA 50 20 1x102 1 mA 60 20 0 1x101 VI = 5 V VO = 3.3 V Co = 4.7 mF Cbyp = 10 nF 90 Ripple Rejection − (dB) Ripple Rejection - (dB) 100 0 10 100 1k 10k Frequency − (Hz) 100k 1M 图 5-24. Ripple Rejection vs Frequency for Legacy Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 11 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 120 10 100 90 Output Impedance − (W) Ripple Rejection - (dB) Ci = 1 mF Co = 10 mF VO = 3.3 V 1 mA 10 mA 100 mA 110 80 70 60 50 VIN = 5 V V0 = 3.3 V C0 = 4.7 uF Cbyp = 10 nF 40 30 20 1 1 mA 10 mA 100 mA 0.1 0.01 10 0 1x101 1x102 1x103 1x104 1x105 Frequency - (Hz) 1x106 Noise Density − (mV/ Hz) Output Impedance − (W) 100 mA 0.1 0.01 1k 10k 100k 1 Cbyp = 1 nF 0.1 Cbyp = 10 nF 0.01 1M 100 1k 100k 图 5-28. Output Noise Density vs Frequency for Legacy Chip 10 CBYP 100 pF 1 nF 10 nF 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 1x102 1x103 1x104 1x105 Frequency - (Hz) 1x106 1x107 图 5-29. Output Noise Density vs Frequency for New Chip ILOAD = 1 mA Noise Density − (mV/ Hz) Noise Density - (V / Hz) 10 5 10k Frequency − (Hz) 图 5-27. Output Impedance vs Frequency for Legacy Chip 12 1M Cbyp = 100 pF Frequency − (Hz) 0.002 0.001 1x101 100k ILOAD = 150 mA 10 mA 100 10k 10 1 mA 0.001 10 1k 图 5-26. Output Impedance vs Frequency for Legacy Chip Ci = 1 mF Co = 4.7 mF VO = 3.3 V 1 100 Frequency − (Hz) 图 5-25. Ripple Rejection vs Frequency for New Chip 10 0.001 10 1x107 1 Cbyp = 100 pF Cbyp = 1 nF 0.1 Cbyp = 10 nF 0.01 100 1k 10k Frequency − (Hz) 100k 图 5-30. Output Noise Density vs Frequency for Legacy Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 1.8 CBYP 100pF 1nF 10nF ILOAD = 1mA 2 1 0.5 RL = 3.3 kW 1.4 0.2 0.1 0.05 0.02 0.01 0.005 1.2 1 0.8 RL = Open 0.6 0.4 0.2 0.002 0.001 1x101 0 1x102 1x103 1x104 1x105 Frequency - (Hz) 1x106 0 1x107 1 2 3 4 5 6 Input Voltage − (V) 图 5-31. Output Noise Density vs Frequency for New Chip 图 5-32. Input Current vs Input Voltage for Legacy Chip 1000 1400 150 °C 1200 Ground Current − (C) Te mperature -55 °C 25 °C -40 °C 85 °C 0 °C 125 °C 800 600 IGND (A) VO = 3.3 V Cbyp = 10 nF 1.6 Input Current − (mA) Noise Density - (V/ Hz) 10 5 VO = 3.3 V CO = 4.7uF 400 200 VO = 3.3 V Cbyp = 10 nF 150 mA 1000 800 600 1 mA 400 50 mA 0 mA 0 200 10 mA 0 -200 0 2 4 6 8 VIN 10 12 14 16 −50 −25 0 25 50 75 100 125 150 Temperature − (°C) 图 5-33. Input Current vs Input Voltage for New Chip 图 5-34. Ground-Pin Current vs Temperature for Legacy Chip 1400 1200 IGND (A) 1000 Load Current 0 50mA 1mA 150mA 10mA VI = 4.3 V VO = 3.3 V 800 600 400 200 0 -75 -50 -25 0 25 50 75 Te mperature C 100 125 150 图 5-35. Ground-Pin Current vs Temperature for New Chip 图 5-36. 2.2-μF Stable ESR Range for Output Voltage ≤ 2.3 V for Legacy Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 13 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 5.6 Typical Characteristics (continued) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 图 5-37. 4.7-μF Stable ESR Range for Output Voltage ≤ 2.3 V for Legacy Chip 14 图 5-38. 2.2-μF, 3.3-μF Stable ESR Range for Output Voltage ≥ 2.5 V for Legacy Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 6 Detailed Description 6.1 Overview The LP2985 is a fixed-output, low-noise, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and nonportable applications. The LP2985 has an output tolerance of ±1% across load, and temperature variation (for the new chip) and is capable of delivering 150mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, and output enable. The new chip version also features internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C. 6.2 Functional Block Diagrams 图 6-1. Functional Block Diagram (Legacy Chip) Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 15 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 VIN VOUT R1 Current Limit R2 + – UVLO BYPASS RF GND ON/OFF Internal Controller Bandgap Reference VREF = 1.2 V Output Pull-down GND GND Thermal Shutdown GND 图 6-2. Functional Block Diagram (New Chip) 6.3 Feature Description 6.3.1 Output Enable The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/ OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled with the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. In the legacy chip, for proper operation of the ON/OFF functionality, apply a signal with a slew rate of ≥40mV/µs. No slew rate consideration is required for the new chip. The new chip has an internal pulldown circuit that activates when the device is disabled. Pull the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the output voltage. 6.3.2 Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. 16 Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. RDS(ON) = VDO IRATED (1) 6.3.3 Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. 图 6-3 shows a diagram of the current limit. VOUT Brickwall VOUT(NOM) IOUT 0V 0 mA IRATED ICL 图 6-3. Current Limit 6.3.4 Undervoltage Lockout (UVLO) The new chip has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table. Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 17 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 6.3.5 Output Pulldown The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: • When the device is disabled (VON/OFF < VON/OFF(LOW)) • If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the Reverse Current section for more details. 6.3.6 Thermal Shutdown The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up completes. For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating Conditions table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. 6.4 Device Functional Modes 6.4.1 Device Functional Mode Comparison 表 6-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table for parameter values. 表 6-1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) VON/OFF < VON/ Not applicable TJ > TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO OFF(LOW) 6.4.2 Normal Operation The device regulates to the nominal output voltage when the following conditions are met: • • • • 18 The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 6.4.3 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. 6.4.4 Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 19 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 7 Application and Implementation 备注 以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定 器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 7.1 Application Information 7.1.1 Recommended Capacitor Types 7.1.1.1 Recommended Capacitors (Legacy Chip) Preferably, use ceramic capacitors on the output of the LP2985 for several reasons. For capacitances ranging from 2.2μF to 4.7μF, ceramic capacitors have the lowest cost and lowest ESR, making these components choice candidates for filtering high-frequency noise. For instance, a typical 2.2μF ceramic capacitor has an ESR ranging from 10mΩ to 20mΩ, which satisfies the minimum ESR requirements of the regulator. Ceramic capacitors have one major disadvantage to be taken into account: a poor temperature coefficient, where the capacitance varies significantly with temperature. For instance, a large-value ceramic capacitor (≥ 2.2μF) potentially loses more than half of the capacitance as the temperature rises from 25°C to 85°C. Thus, a 2.2μF capacitor at 25°C drops well below the minimum COUT required for stability, as ambient temperature rises. For this reason, select an output capacitor that maintains the minimum 2.2μF required for stability over the entire operating temperature range. There are some ceramic capacitors that maintain a ±15% capacitance tolerance over temperature. Tantalum capacitors are able to be used at the output of the LP2985, but there are significant disadvantages prohibiting this usage: • In the 1μF to 4.7μF range, tantalum capacitors are more expensive than ceramics of the equivalent capacitance and voltage ratings. • Tantalum capacitors have higher ESR values than equivalent-sized ceramic counterparts. Thus, to meet the ESR requirements, a higher-capacitance tantalum is required, at the expense of larger size and higher cost. • The ESR of a tantalum capacitor increases as temperature drops, as much as double from +25°C to –40°C. Thus, maintain ESR margins over the temperature range to prevent regulator instability. 7.1.1.2 Recommended Capacitors (New Chip) The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but use good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature. Using Y5V-rated capacitors is discouraged because of large variations in capacitance. Maximum supported ESR range across complete temperature (−40°C to +125°C) and load current range (0mA−150mA) is less than 1Ω. For existing implementations, where different capacitor types with higher ESR values are used, use a low ESR, 100nF MLCC capacitor. Place this capacitor as close as possible to the device output (VOUT) pin. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. 7.1.2 Input and Output Capacitor Requirements 7.1.2.1 Input Capacitor Requirements For the legacy chip, a minimum value of 1μF (over the entire operating temperature range) is required at the input of the LP2985. In addition, place this input capacitor within 1cm of the input pin, connected to a clean 20 Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 analog ground. There are no equivalent series resistance (ESR) requirements for this capacitor; increase capacitance without limit. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5Ω. Use a higher value capacitor if large, fast rise-time load or line transients are anticipated. Use this capacitor if the device is located several inches from the input power source. 7.1.2.2 Output Capacitor Requirements For the legacy chip, the LP2985 permits using low ESR capacitors at the output, including ceramic capacitors that have an ESR as low as 5mΩ. Tantalum and film capacitors are also available if size and cost are not issues. Place the output capacitor within 1cm of the output pin. Make sure this capacitor returns to a clean analog ground. As with other PNP LDOs, stability conditions require the output capacitor to have a minimum capacitance and an ESR that falls within a certain range. • Minimum COUT: 2.2μF (increase this capacitance without limit to improve transient response stability margin) • ESR range: see 图 5-36 through 图 5-38 Both the minimum capacitance and ESR requirement are critical to be met over the entire operating temperature range. Depending on the type of capacitors used, both these parameters potentially vary significantly with temperature (see the Recommended Capacitors (Legacy Chip) section). For the new chip, dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor within the range specified in the Recommended Operating Conditions table for stability. Review the Recommended Capacitors (New Chip) section for further information on supported output capacitors. 7.1.3 Noise Bypass Capacitor (CBYPASS) The LP2985 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is biased in the microampere range and, thus, cannot be loaded significantly, otherwise, the output (and, correspondingly, the output of the regulator) changes. Thus, for best output accuracy, dc leakage current through CBYPASS must be minimized as much as possible and must never exceed 100 nA. The CBYPASS capacitor also impacts the start-up behavior of the regulator. Inrush current and start-up time increase with larger bypass capacitor values. Use a 10-nF capacitor for CBYPASS. Ceramic and film capacitors are good choices for this purpose. 7.1.4 Reverse Current Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. • If the device has a large COUT and the input supply collapses with little or no load current • The output is biased when the input supply is not established • The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. 图 7-1 shows one approach for protecting the device. Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 21 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 Schottky Diode Internal Body Diode IN OUT CIN COUT GND GND GND GND 图 7-1. Example Circuit for Reverse Current Protection Using a Schottky Diode 7.1.5 Power Dissipation (PD) Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). (2) PD = (VIN – VOUT) × IOUT 备注 Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). (3) TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. 7.1.6 Estimating Junction Temperature The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junctionto-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to 22 Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. (4) TJ = TT + ψJT × PD where: • PD is the dissipated power • TT is the temperature at the center-top of the device package (5) TJ = TB + ψJB × PD where: • TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 23 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 7.2 Typical Application 图 7-2 shows the standard usage of the LP2985 as a low-dropout regulator. LP2985 VIN 1 VOUT 5 2.2 µF 1 µF GND ON/OFF 2 3 4 BYPASS 10 nF 图 7-2. LP2985 Typical Application 7.2.1 Design Requirements Minimum COUT value for stability (can be increased without limit for improved stability and transient response) ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used. Optional BYPASS capacitor for low-noise operation. 7.2.2 Detailed Design Procedure 7.2.2.1 ON/OFF Operation The LP2985 allows for a shutdown mode via the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to the input to ensure that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected. 24 Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 7.2.3 Application Curves 3.38 150 3.36 100 3.34 3.32 3.3 3.82 50 IL VO = 3.3 V Cbyp = 10 nF DIL = 100 mA 0 −50 VO −100 3.28 3.7 300 VO 250 IL 200 3.64 150 3.76 3.58 100 V0 = 3.3V Cbyp = 10nF IL=100mA 3.52 3.46 50 0 3.4 -50 3.34 -100 3.28 -150 3.26 −150 3.22 -200 3.24 −200 3.16 -250 3.1 −250 3.22 0 20 40 60 20 ms/div→ 80 20s/div 100 120 Load Current - (mA) 200 Output Voltage -(V) 3.4 Load Current − (mA) Output Voltage − (V) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) -300 140 150 dI/dt = 1 A/μ 图 7-3. Load Transient Response for Legacy Chip 200 150 3.36 100 3.82 300 VO 250 IL 200 3.76 3.32 3.3 VO = 3.3 V Cbyp = 10 nF DIL = 150 mA 50 0 −50 VO −100 3.28 Output Voltage - (V) IL 3.34 Load Current − (mA) Output Voltage − (V) 3.7 3.64 150 3.58 100 VO = 3.3V Cbyp =10 nF IL=150mA 3.52 3.46 50 0 3.4 -50 3.34 -100 3.28 -150 3.26 −150 3.22 -200 3.24 −200 3.16 -250 3.22 −250 3.1 0 20 40 60 20 ms/div→ 80 20s/div 100 120 Load Current - (mA) 3.4 3.38 图 7-4. Load Transient Response for New Chip -300 140 150 dI/dt = 1 A/μ 图 7-5. Load Transient Response for Legacy Chip 图 7-6. Load Transient for New Chip 200 3.82 3.38 150 3.76 3.36 100 300 VO 250 IL 200 3.32 3.3 VO = 3.3 V Cbyp = 0 nF DIL = 150 mA 0 −50 VO 3.28 50 −100 3.26 −150 3.24 −200 −250 3.22 Output Voltage - (V) IL 3.34 Load Current − (mA) Output Voltage − (V) 3.7 3.64 150 3.58 100 V0 = 3.3V Cbyp = 0 nF IL = 150 mA 3.52 3.46 50 0 3.4 -50 3.34 -100 3.28 -150 3.22 -200 3.16 -250 3.1 0 20 20 ms/div→ 40 60 80 20s/div 100 120 Load Current - (mA) 3.4 -300 140 150 dI/dt = 1 A/μ 图 7-7. Load Transient Response for Legacy Chip 图 7-8. Load Transient Response for New Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 25 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 7.2.3 Application Curves (continued) VI Output Voltage − (V) 3.37 3.35 VO = 3.3 V Cbyp = 0 nF IO = 150 mA 3.41 5 3.39 6.5 VO VIN 6 4.5 3.37 5.5 3.35 5 3.33 4.5 3.31 4 3.29 3.5 4 3.5 3.33 3.31 VO 3 3.29 2.5 3.27 2 Output Voltage - (V) 3.39 5.5 Input Voltage − (V) 3.41 3.27 0 40 80 20 ms/div→ 120 160 20 s/div 200 Input Voltage - (V) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 3 280 240 VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ 图 7-9. Line Transient Response for Legacy Chip 3.39 5 3.35 VO = 3.3 V Cbyp = 10 nF IO = 150 mA 4.5 4 3.33 3.5 3.31 3 3.29 VO 7 VO VIN 6.5 3.31 Output Voltage - (V) VI 3.37 3.312 3.308 6 3.306 5.5 3.304 5 3.302 4.5 3.3 4 3.298 2.5 3.5 3.296 3.27 2 Input Voltage - (V) 5.5 Input Voltage − (V) Output Voltage − (V) 图 7-10. Line Transient Response for New Chip 3.41 0 20 40 60 20 ms/div→ 80 100 120 20 s/div 140 160 180 3 200 VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ 图 7-11. Line Transient Response for Legacy Chip 3.41 3.39 5 3.39 6.5 VO VIN 6 4.5 3.37 5.5 3.35 5 3.33 4.5 3.31 4 3.29 3.5 VI 3.37 3.35 VO = 3.3 V Cbyp = 0 nF IO = 1 mA 4 3.33 3.5 3.31 3 2.5 3.29 VO 3.27 3.27 2 0 40 20 ms/div→ 80 120 160 20 s/div 200 240 Input Voltage - (V) 5.5 Output Voltage - (V) 3.41 Input Voltage − (V) Output Voltage − (V) 图 7-12. Line Transient Response for New Chip 3 280 VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ 图 7-13. Line Transient Response for Legacy Chip 图 7-14. Line Transient Response for New Chip 26 Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 7.2.3 Application Curves (continued) 5.5 3.39 5 VIN 4.5 4 3.35 3.33 Input Voltage − (V) Output Voltage − (V) 3.37 VO = 3.3 V Cbyp = 10 nF IO = 1 mA 3.5 3.31 VO 3 2.5 3.29 3.27 3.312 3.311 3.31 3.309 3.308 3.307 3.306 3.305 3.304 3.303 3.302 3.301 3.3 3.299 3.298 3.297 3.296 0 2 20 40 60 100 ms/div→ 80 100 20 s/div 120 140 7 VO 6.75 VIN 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 3.75 3.5 3.25 3 160170 Input Voltage - (V) 3.41 Output Voltage - (V) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ 图 7-15. Line Transient Response for Legacy Chip 图 7-16. Line Transient Response for New Chip 4 16 VO VON 14 VO 3 3 1 6 0 −1 VO = 3.3 V Cbyp = 0 IO = 150 mA 4 VON/OFF − (V) Output Voltage − (V) 2 Output Voltage - (V) 8 −2 VON/OFF 2 −3 V0 = 3.3 V Cbyp =0 ILOAD = 150 mA 2 12 1 10 0 8 -1 6 -2 4 -3 2 -4 −4 0 0 100 200 100 ms/div→ 图 7-17. Turn-On Time for Legacy Chip 3 0 −1 VO = 3.3 V Cbyp = 100 pF ILOAD = 150 mA 4 −2 VON/OFF VON/OFF − (V) Output Voltage − (V) 6 2 −3 0 −4 Output Voltage - (V) 8 2 3 16 VO V0N 14 2 12 1 10 0 8 V0 = 3.3 V Cbyp = 100 pF ILOAD = 150 mA -1 -2 -3 6 4 2 -4 0 200 200 ms/div→ 图 7-19. Turn-On Time for Legacy Chip 0 700 600 图 7-18. Turn-On Time for New Chip VO 1 500 4 10 4 300 400 100s/div VON - (V) 10 Von - (V) 4 400 600 200s/div 800 1000 0 1200 图 7-20. Turn-On Time for New Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 27 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 7.2.3 Application Curves (continued) 4 10 4 3 16 Vo VON 14 2 12 1 10 VO 3 6 0 4 VON/OFF −2 2 −3 8 V0= 3.3 V Cbyp = 1nF ILOAD = 150mA -1 6 -2 4 -3 2 -4 0 −4 0 0 2 4 6 2 ms/div 2 ms/div→ COUT = 4.7 μF 4 4 10 Input 16 3 1 6 0 4 Output −2 VON/OFF − (V) 2 Output Voltage - (V) 8 VO = 3.3 V Cbyp = 10 nF ILOAD = 150 mA 0 12 图 7-22. Turn-On Time for New Chip 3 Output Voltage − (V) 10 COUT = 4.7 μF 图 7-21. Turn-On Time for Legacy Chip −1 8 VOUT VON 2 1 14 12 10 0 8 V0 = 3.3 V Cbyp = 10 nF ILOAD = 150 mA -1 6 -2 4 -3 2 VON - (V) −1 VO = 3.3 V Cbyp = 1 nF ILOAD = 150 mA VON/OFF − (V) Output Voltage − (V) 1 Output Voltage - (V) 8 2 VON - (V) at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted) 2 −3 0 −4 -4 0 20 20 ms/div→ COUT = 4.7 μF 图 7-23. Turn-On Time 28 40 60 20ms/div 80 100 0 120 COUT = 4.7 μF 图 7-24. Turn-On Time for New Chip Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 7.3 Power Supply Recommendations A power supply can be used at the input voltage within the ranges given in the Recommended Operating Conditions table. Use bypass capacitors as described in the Layout Guidelines section. 7.4 Layout 7.4.1 Layout Guidelines • Bypass the input pin to ground with a bypass capacitor. • The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system. Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the system. • For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation. 7.4.2 Layout Example VIN VOUT COUT CIN GND PLANE CBYPASS ON/OFF BYPASS 图 7-25. Layout Diagram Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 29 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 8 Device and Documentation Support 8.1 Device Support 8.1.1 Device Nomenclature 表 8-1. Available Options (1) PRODUCT(1) DESCRIPTION LP2985c-xxyyyzM3 c is the accuracy specification for the legacy chip (A or blank). See the Electrical Characteristics table for more information. This character is insignificant for the new chip. xx is the nominal output voltage (for example, 33 = 3.3V; 50 = 5.0V). yyy is the package designator (DBV = SOT-23). z is the reel designator size. See the Package Addendum for more information on package quantity. This device ships with the legacy chip (CSO: DLN or GF8) or the new chip (CSO: RFB), which uses the latest manufacturing flow. The reel packaging label provides CSO information to distinguish which chip is used. Device performance for new and legacy chips is denoted throughout the document. M3 is a suffix designator only significant for the new chip with CSO:RFB, which uses the latest manufacturing flow. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. 8.2 接收文档更新通知 要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击通知 进行注册，即可每周接收产品信息更改摘 要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。 8.3 支持资源 TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索 现有解答或提出自己的问题，获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的使用条款。 8.4 Trademarks TI E2E™ is a trademark of Texas Instruments. 所有商标均为其各自所有者的财产。 8.5 静电放电警告 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理 和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参 数更改都可能会导致器件与其发布的规格不相符。 8.6 术语表 TI 术语表 30 本术语表列出并解释了术语、首字母缩略词和定义。 Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 LP2985, LP2985A www.ti.com.cn ZHCSLK4S – JULY 2004 – REVISED MAY 2025 9 Revision History 注：以前版本的页码可能与当前版本的页码不同 Changes from Revision R (July 2023) to Revision S (May 2025) • • • • • • • Page 通篇添加了区分新芯片和旧芯片信息的命名规则................................................................................................1 Changed Overview section: changed 1% to ±1%, deleted line variation, and clarified new chip features.......15 Added Functional Block Diagram (Legacy Chip) figure....................................................................................15 Changed Output Enable section to identify differences between new and legacy chip functionality............... 16 Changed Recommended Capacitor Types section and added subsections.................................................... 20 Changed Input and Output Capacitor Requirements section........................................................................... 20 Changed Device Nomenclature section........................................................................................................... 30 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2025 Texas Instruments Incorporated 提交文档反馈 31 Product Folder Links: LP2985 LP2985A English Data Sheet: SLVS522 PACKAGE OPTION ADDENDUM www.ti.com 24-Jul-2025 PACKAGING INFORMATION Orderable part number Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Op temp (°C) Part marking (6) LP2985-10DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LRCG LP2985-10DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LRCG LP2985-10DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LRCG LP2985-10DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LRCG LP2985-18DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPHG, LPHL) LP2985-18DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPHG, LPHL) LP2985-18DBVRE4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPHG LP2985-18DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPHG LP2985-18DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPHG LP2985-18DBVRM3 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LPHG LP2985-18DBVRM3.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LPHG LP2985-18DBVT Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI -40 to 125 (LPHG, LPHL) LP2985-18DBVTG4 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPHG LP2985-18DBVTG4.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPHG LP2985-25DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (LPLG, LPLL) LP2985-25DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPLG, LPLL) (LPLG, LPLL) LP2985-25DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LP2985-25DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPLG, LPLL) LP2985-28DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPGG, LPGL) LP2985-28DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPGG, LPGL) LP2985-28DBVTG4 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPGG LP2985-28DBVTG4.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPGG LP2985-29DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPMG LP2985-29DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPMG NIPDAU | SN | NIPDAU Level-1-260C-UNLIM LP2985-30DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes -40 to 125 (LPNG, LPNL) LP2985-30DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPNG, LPNL) LP2985-30DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 125 (LPNG, LPNL) LP2985-30DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPNG, LPNL) LP2985-30DBVT Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI -40 to 125 (LPNG, LPNL) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable part number 24-Jul-2025 Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) LP2985-33DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes Lead finish/ Ball material MSL rating/ Peak reflow Op temp (°C) Part marking (4) (5) SN Level-1-260C-UNLIM -40 to 125 (LPFG, LPFL) (6) LP2985-33DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPFG, LPFL) LP2985-33DBVRE4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPFG LP2985-33DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPFG LP2985-33DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPFG LP2985-33DBVRM3 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LPFG LP2985-33DBVRM3.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LPFG LP2985-33DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPFG, LPFL) LP2985-33DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPFG, LPFL) LP2985-33DBVTG4 Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI -40 to 125 LPFG LP2985-33DBVTM3 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LPFG LP2985-33DBVTM3.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LPFG NIPDAU | SN | NIPDAU Level-1-260C-UNLIM LP2985-50DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes LP2985-50DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes -40 to 125 (LPSG, LPSL) Level-1-260C-UNLIM -40 to 125 LP2985-50DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes (LPSG, LPSL) NIPDAU | SN | NIPDAU Level-1-260C-UNLIM -40 to 125 (LPSG, LPSL) LP2985-50DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU LP2985-50DBVT.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R - NIPDAU Level-1-260C-UNLIM -40 to 125 (LPSG, LPSL) Level-1-260C-UNLIM -40 to 125 (LPSG, LPSL) NIPDAU LP2985-50DBVTG4 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 125 (LPSG, LPSL) LP2985-50DBVTG4.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPSG, LPSL) LP2985-50DBVTM3 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LPSG LP2985-50DBVTM3.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 LPSG LP2985A-10DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LRDG LP2985A-10DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LRDG LP2985A-10DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LRDG LP2985A-10DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LRDG LP2985A-18DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPTG, LPTL) LP2985A-18DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPTG, LPTL) LP2985A-18DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPTG LP2985A-18DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPTG LP2985A-18DBVT Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI -40 to 125 (LPTG, LPTL) LP2985A-25DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes -40 to 125 (LPUG, LPUL) Addendum-Page 2 NIPDAU | SN | NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com Orderable part number 24-Jul-2025 Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) LP2985A-25DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes Lead finish/ Ball material MSL rating/ Peak reflow Op temp (°C) Part marking (4) (5) NIPDAU Level-1-260C-UNLIM -40 to 125 (LPUG, LPUL) (6) LP2985A-25DBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R - NIPDAU Level-1-260C-UNLIM -45 to 125 (LPUG, LPUL) LP2985A-25DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 125 (LPUG, LPUL) LP2985A-25DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPUG, LPUL) LP2985A-25DBVRM3 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -45 to 125 LPUG LP2985A-25DBVRM3.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -45 to 125 LPUG LP2985A-25DBVRM3.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R - NIPDAU Level-1-260C-UNLIM -45 to 125 LPUG LP2985A-25DBVT Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI -40 to 125 (LPUG, LPUL) LP2985A-28DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (LPJG, LPJL) LP2985A-28DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPJG, LPJL) LP2985A-29DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPZG, LPZL) LP2985A-29DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPZG, LPZL) LP2985A-30DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (LRAG, LRAL) LP2985A-30DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LRAG, LRAL) LP2985A-30DBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R - SN Level-1-260C-UNLIM -45 to 125 (LRAG, LRAL) LP2985A-30DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LRAG, LRAL) LP2985A-30DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LRAG, LRAL) LP2985A-33DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (LPKG, LPKL) LP2985A-33DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LPKG, LPKL) LP2985A-33DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPKG LP2985A-33DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPKG LP2985A-33DBVRM3 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LPKG LP2985A-33DBVRM3.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPKG LP2985A-33DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPFG, LPKG, LPKL) LP2985A-33DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPFG, LPKG, LPKL) LP2985A-33DBVTE4 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPKG LP2985A-33DBVTG4 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPKG LP2985A-33DBVTG4.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LPKG LP2985A-50DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (LR1G, LR1L) Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com Orderable part number (1) 24-Jul-2025 Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LR1G, LR1L) (3) LP2985A-50DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Op temp (°C) Part marking (6) LP2985A-50DBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R - NIPDAU Level-1-260C-UNLIM -45 to 125 (LR1G, LR1L) LP2985A-50DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LR1G, LR1L) LP2985A-50DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (LR1G, LR1L) LR1G LP2985A-50DBVRM3 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LP2985A-50DBVRM3.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 LR1G LP2985A-50DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (LPSG, LR1G, LR1L) LP2985A-50DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 (LPSG, LR1G, LR1L) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 4 PACKAGE OPTION ADDENDUM www.ti.com 24-Jul-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 5 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2025 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LP2985-10DBVR SOT-23 DBV 5 3000 178.0 9.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 LP2985-10DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 LP2985-18DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-18DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 LP2985-18DBVRM3 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-18DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 LP2985-25DBVR SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-28DBVR SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-28DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 LP2985-29DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 LP2985-30DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-30DBVRG4 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-33DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-33DBVRG4 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-33DBVRM3 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-33DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2025 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2985-33DBVTM3 SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-50DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-50DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-50DBVTG4 SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985-50DBVTM3 SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-10DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 LP2985A-10DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 LP2985A-18DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-18DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 LP2985A-25DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-25DBVRG4 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-25DBVRM3 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-28DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 LP2985A-28DBVR SOT-23 DBV 5 3000 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3 LP2985A-29DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 LP2985A-30DBVR SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-33DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-33DBVRG4 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-33DBVRM3 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-33DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-33DBVTG4 SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-50DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-50DBVRG4 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-50DBVRM3 SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP2985A-50DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2985-10DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 LP2985-10DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 LP2985-18DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985-18DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0 LP2985-18DBVRM3 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985-18DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0 LP2985-25DBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 LP2985-28DBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 LP2985-28DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0 LP2985-29DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 LP2985-30DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985-30DBVRG4 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985-33DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985-33DBVRG4 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985-33DBVRM3 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985-33DBVT SOT-23 DBV 5 250 210.0 185.0 35.0 LP2985-33DBVTM3 SOT-23 DBV 5 250 210.0 185.0 35.0 LP2985-50DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2025 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2985-50DBVT SOT-23 DBV 5 250 210.0 185.0 35.0 LP2985-50DBVTG4 SOT-23 DBV 5 250 210.0 185.0 35.0 LP2985-50DBVTM3 SOT-23 DBV 5 250 210.0 185.0 35.0 LP2985A-10DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 LP2985A-10DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 LP2985A-18DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-18DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0 LP2985A-25DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-25DBVRG4 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-25DBVRM3 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-28DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 LP2985A-28DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0 LP2985A-29DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 LP2985A-30DBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 LP2985A-33DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-33DBVRG4 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-33DBVRM3 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-33DBVT SOT-23 DBV 5 250 210.0 185.0 35.0 LP2985A-33DBVTG4 SOT-23 DBV 5 250 210.0 185.0 35.0 LP2985A-50DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-50DBVRG4 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-50DBVRM3 SOT-23 DBV 5 3000 210.0 185.0 35.0 LP2985A-50DBVT SOT-23 DBV 5 250 210.0 185.0 35.0 Pack Materials-Page 4 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 A 5 (0.1) 2X 0.95 1.9 0.1 C B 3.05 2.75 1.9 2 (0.15) 4 0.5 5X 0.3 0.2 3 C A B NOTE 5 4X 0 -15 (1.1) 0.15 TYP 0.00 1.45 0.90 4X 4 -15 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/K 08/2024 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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