LP2985
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
LP2985 150-mA, Low-Noise, Low-Dropout Regulator With Shutdown
1 Features
3 Description
•
•
The LP2985 is a fixed-output, wide-input, low-noise,
low-dropout voltage regulator supporting an input
voltage range from 2.5 V to 16 V and up to 150 mA of
load current. The LP2985 supports an output range of
1.2 V to 5.0 V (for new chip).
•
•
•
•
•
•
•
•
•
•
•
•
VIN range (new chip): 2.5 V to 16 V
VOUT range (new chip): 1.2 V to 5.0 V (fixed, 100mV steps)
VOUT accuracy:
– ±1% for A-grade legacy chip
– ±1.5% for standard-grade legacy chip
– ±0.5% for new chip only
±1% output accuracy over load, and temperature
for new chip
Output current: Up to 150 mA
Low IQ (new chip): 71 μA at ILOAD = 0 mA
Low IQ (new chip): 750 μA at ILOAD = 150 mA
Shutdown current:
– 0.01 μA (typ) for legacy chip
– 1.12 μA (typ) for new chip
Low noise: 30 μVRMS with 10-nF bypass capacitor
Output current limiting and thermal protection
Stable with 2.2-µF ceramic capacitors
High PSRR: 70 dB at 1 kHz, 40 dB at 1 MHz
Operating junction temperature: –40°C to +125°C
Package: 5-pin SOT-23 (DBV)
2 Applications
Washer and dryer
Land mobile radio
Active antenna system mMIMO
Cordless power tool
Motor drives and control boards
Low output noise of 30 µVRMS (with 10-nF bypass
capacitors) and wide bandwidth PSRR performance
of greater than 70 dB at 1 kHz and 40 dB at 1 MHz
help attenuate the switching frequency of an upstream
DC/DC converter and minimize post regulator filtering.
The internal soft-start time and current limit protection
reduce inrush current during start up, thus minimizing
input capacitance. Standard protection features, such
as overcurrent and overtemperature protection, are
included.
The LP2985 is available in a 5-pin 2.9-mm × 1.6-mm
SOT-23 (DBV) package.
Package Information(1)
PART
NUMBER
450
400
350
Iout
1mA
10mA
PACKAGE
LP2985
(1)
Dropout (mV)
•
•
•
•
•
Additionally, the LP2985 (new chip) has a 1% output
accuracy across load, and temperature that can meet
the needs of low-voltage microcontrollers (MCUs) and
processors.
DBV (SOT-23, 5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VIN
VOUT
IN
50mA
150mA
OUT
LP2985
300
CIN
COUT
ON/
OFF
250
200
BYPASS
GND
GND
10 nF
150
GND
GND
100
GND
50
0
-75
Typical Application Circuit
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
Dropout Voltage vs Temperature for New Chip
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 9
7 Detailed Description......................................................16
7.1 Overview................................................................... 16
7.2 Functional Block Diagram......................................... 16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................18
8 Application and Implementation.................................. 20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 23
8.3 Power Supply Recommendations.............................28
8.4 Layout....................................................................... 28
9 Device and Documentation Support............................29
9.1 Device Nomenclature................................................29
9.2 Receiving Notification of Documentation Updates....29
9.3 Support Resources................................................... 29
9.4 Trademarks............................................................... 29
9.5 Electrostatic Discharge Caution................................29
9.6 Glossary....................................................................29
10 Mechanical, Packaging, and Orderable
Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (February 2022) to Revision Q (December 2022)
Page
• Changed Features section..................................................................................................................................1
• Added last bullet to Applications section............................................................................................................ 1
• Changed Description section..............................................................................................................................1
• Changed Description column and added footnote to Pin Functions table ......................................................... 3
• Changed condition statement and curve titles and added curves for new chip in Typical Characteristics
section................................................................................................................................................................ 9
• Changed Overview section...............................................................................................................................16
• Changed Functional Block Diagram figure....................................................................................................... 16
• Changed Feature Description section and added subsections........................................................................ 16
• Added Output Pulldown section........................................................................................................................18
• Changed Device Functional Modes section: changed Normal Operation section, added Device Functional
Mode Comparison, Dropout Operation, and Disabled sections, and deleted Shutdown Mode section........... 18
• Changed Application Information section: deleted previous information and added new subsections............ 20
• Changed LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation section....23
• Changed Application Curves section................................................................................................................24
• Changed Layout Diagram figure.......................................................................................................................28
• Added Device Nomenclature section................................................................................................................29
Changes from Revision O (January 2015) to Revision P (February 2022)
Page
• Changed Applications section............................................................................................................................ 1
• Changed Application Information section......................................................................................................... 20
• Changed Typical Application section to follow current standards.....................................................................23
2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
5 Pin Configuration and Functions
VIN
1
GND
2
ON/OFF
3
5
VOUT
4
BYPASS
Figure 5-1. DBV Package, 5-Pin SOT-23 (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
BYPASS
4
I/O
BYPASS pin to achieve low noise performance. Connecting an external capacitor between
BYPASS pin and ground reduces reference voltage noise. See the Recommended
Operating Conditions section for more information.
GND
2
—
Ground
ON/OFF
3
I
Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low
disables the device. High and low thresholds are listed in the Electrical Characteristics table.
Tie this pin to VIN if unused.
VIN
1
I
Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See
the Input and Output Capacitor Requirements section for more information.
VOUT
5
O
Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to
ground.(1) See the Input and Output Capacitor Requirements section for more information.
(1)
The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is
50%. Make sure that the effective capacitance at the pin is greater than 1 μF.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
3
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
VIN
VOUT
VBYPASS
VON/OFF
16
Continuous input voltage range (for new chip)
–0.3
18
Output voltage range (for legacy chip)
–0.3
9
Output voltage range (for new chip)
V + 0.3 or 9V (whichever
–0.3 IN
is smaller)
BYPASS pin voltage range (for new chip)
–0.3
3
ON/OFF pin voltage range (for legacy chip)
–0.3
16
–0.3
18
Maximum output
Temperature
(2)
MAX
–0.3
ON/OFF pin voltage range (for new chip)
Current
(1)
MIN
Continuous input voltage range (for legacy chip)
UNIT
V
Internally limited
A
Operating junction, TJ
–55
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages with respect to GND.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
(Legacy
chip)
VALUE
(New
chip)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
±500
±1000
UNIT
V
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VIN
VOUT
VBYPASS
MAX
2.2
16
Supply input voltage (for new chip)
2.5
16
Output voltage (for legacy chip)
1.2
10.0
Output voltage (for new chip)
1.2
Bypass voltage
5.0
0
VIN
Enable voltage (for new chip)
0
16
IOUT
Output current
0
CIN (1)
Input capacitor
COUT
TJ
(1)
UNIT
V
1.2
Enable voltage (for legacy chip)
VON/OFF
4
NOM
Supply input voltage (for legacy chip)
150
1
Output capacitor (for legacy chip)
Output capacitance (for new chip) (1)
Operating junction temperature
2.2
4.7
1
2.2
–40
mA
μF
200
125
μF
°C
All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 μF
minimum for stability.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.4 Thermal Information
THERMAL METRIC (1)
Legacy chip
New chip
DBV (SOT23-5)
DBV (SOT23-5)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
205.4
178.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
78.8
77.9
°C/W
RθJB
Junction-to-board thermal resistance
46.7
47.2
°C/W
ψJT
Junction-to-top characterization parameter
8.3
15.9
°C/W
ψJB
Junction-to-board characterization parameter
46.3
46.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IL = 1 mA
1 mA ≤ IL ≤ 50 mA
∆VOUT
Output voltage tolerance
1 mA ≤ IL ≤ 150 mA
1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C
MIN
Legacy chip
(standard
grade)
-1.5
1.5
%
Legacy chip
(A grade)
-1.0
1.0
%
New chip
-0.5
0.5
%
Legacy chip
(standard
grade)
-2.5
2.5
%
Legacy chip
(A grade)
-1.5
1.5
%
New chip
-0.5
0.5
%
Legacy chip
(standard
grade)
-3.0
3.0
%
Legacy chip
(A grade)
-2.5
2.5
%
New chip
-0.5
0.5
%
Legacy chip
(standard
grade)
-3.5
3.5
%
Legacy chip
(A grade)
-2.5
2.5
%
-1
1
%
Legacy chip
(standard
grade)
-4.0
4.0
%
Legacy chip
(A grade)
-3.5
3.5
%
1
%
New chip
1 mA ≤ IL ≤ 150 mA, –40°C ≤ TJ ≤ 125°C
New chip
VO(NOM) + 1 V ≤ VIN ≤ 16 V
ΔVOUT(ΔVIN)
Line Regulation
VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C
TYP MAX UNIT
-1
Legacy chip
0.007 0.014
New chip
0.002 0.014
Legacy chip
0.007 0.032
New chip
0.002 0.032
%/V
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
5
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.5 Electrical Characteristics (continued)
specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOUT = 0 mA
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
IOUT = 10 mA
Dropout voltage(1)
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
IOUT = 50 mA
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
IOUT = 150 mA
IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C
6
3
New chip
1
2.75
Legacy chip
Submit Document Feedback
5
New chip
New chip
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
TYP MAX UNIT
1
Legacy chip
IOUT = 1 mA
VIN - VOUT
MIN
Legacy chip
3
7
10
11.5
14
Legacy chip
15
New chip
17
Legacy chip
40
60
New chip
98
115
Legacy chip
90
New chip
mV
148
Legacy chip
120
150
New chip
120
145
Legacy chip
225
New chip
184
Legacy chip
280
350
New chip
180
198
Legacy chip
575
New chip
254
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.5 Electrical Characteristics (continued)
specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOUT = 0 mA
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
IOUT = 1 mA
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
IOUT = 10 mA
IOUT = 1 0mA, –40°C ≤ TJ ≤ 125°C
IGND
GND pin current
IOUT = 50 mA
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
IOUT = 150 mA
IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C
VON/OFF < 0.3 V, VIN = 16 V
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 85°C
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C
VUVLO+
Rising bias supply UVLO
VIN rising, –40°C ≤ TJ ≤ 125°C
VUVLO-
Falling bias supply UVLO
VIN falling, –40°C ≤ TJ ≤ 125°C
VUVLO(HYST)
UVLO hysteresis
–40°C ≤ TJ ≤ 125°C
Low = O/P OFF
Low = O/P OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤
125°C
VON/OFF
ON/OFF input voltage
High = O/P ON
High = O/P ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤
125°C
MIN
TYP MAX UNIT
Legacy chip
65
New chip
69
Legacy chip
95
95
125
New chip
120
Legacy chip
75
110
New chip
78
105
Legacy chip
170
New chip
130
Legacy chip
120
220
New chip
175
200
Legacy chip
400
New chip
240
Legacy chip
350
600
New chip
380
410
Legacy chip
900
New chip
590
Legacy chip
850 1200
New chip
765
890
Legacy chip
2000
New chip
1060
Legacy chip
0.01
0.08
New chip
1.25
1.75
Legacy chip
0
1
New chip
1.12
2.25
Legacy chip
0.01
2
New chip
1.12
2.75
2.2
2.4
New chip
uA
1.9
V
0.130
V
Legacy chip
0.55
V
New chip
0.72
Legacy chip
New chip
Legacy chip
New chip
V
0.15
V
0.15
V
1.4
V
0.85
V
Legacy chip
1.6
V
New chip
1.6
V
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
V
7
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.5 Electrical Characteristics (continued)
specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VON/OFF = 0 V
VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V,–40°C ≤ TJ ≤
125°C
ION/OFF
ON/OFF input current
VON/OFF = 5 V
VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤
125°C
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) –5% (steady state)
IO(SC)
Short Output Current
RL = 0 Ω (steady state)
ΔVO/ΔVIN
Ripple Rejection
f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF
Vn
Tsd+
Tsd(1)
8
Output noise voltage
Thermal shutdown
threshold
MIN
0.01
New chip
0.42
Legacy chip
New chip
Legacy chip
New chip
uA
-1
uA
-0.9
uA
uA
0.011
uA
New chip
15
uA
2.20
uA
Legacy chip
300
350
mA
New chip
300
350
mA
Legacy chip
400
mA
New chip
375
mA
Legacy chip
45
dB
New chip
78
dB
30
µVRM
30
µVRM
Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT
New chip
= 2.2 µF, VOUT = 3.3V, ILOAD = 150 mA
Reset, temperature decreasing
uA
5
Legacy chip
Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT
Legacy chip
= 2.2 µF, VOUT = 3.3V, ILOAD = 150 mA
Shutdown, temperature increasing
TYP MAX UNIT
Legacy chip
New chip
170
150
S
S
°C
Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured
with a 1-V differential. VDO is measured with VIN = VOUT(nom) - 100mV for fixed output devices.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
3.345
10.20
VI = 4.3 V
VO = 3.3 V
Ci = 1 mF
Co = 4.7 mF
IO = 1 mA
VI = 11 V
10.15
VO = 10 V
10.10
3.335
CO = 4.7 µF
Output Voltage − (V)
Output Voltage – V
CI = 1 µF
IO = 1 mA
10.05
10.00
9.95
3.325
3.315
3.305
9.90
9.85
-50
-25
0
25
50
75
100
125
3.295
−50
150
−25
0
Temperature – °C
25
50
75
100
125
150
Temperature − (°C)
Figure 6-1. Output Voltage vs Temperature for Legacy Chip
Figure 6-2. Output Voltage vs Temperature for Legacy Chip
3.315
Output Voltage (V)
3.31
VI = 4.3 V
VO = 3.3 V
Iout = 1mA
CO = 4.7uF
3.305
3.3
3.295
3.29
3.285
3.28
-75
-50
-25
0
25
50
Temp C
75
100
125
150
VIN = 4.3 V, VOUT = 3.3 V (for new chip)
Figure 6-3. Output Voltage vs Temperature for New Chip
Figure 6-4. Dropout Voltage vs Temperature for Legacy Chip
450
400
1mA
10mA
200
175
300
250
200
150
150
125
100
75
100
50
50
25
0
-75
VO = 3.3 V
CO = 4.7uF
225
50mA
150mA
Dropout (mV)
Dropout (mV)
350
250
Iout
-55 °C
-40 °C
0 °C
Temperature
25 °C
85 °C
125 °C
150 °C
0
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
Figure 6-5. Dropout Voltage vs Temperature for New Chip
0
20
40
60
80
100
IOUT (mA)
120
140
160
Figure 6-6. Dropout Voltage vs Load Current for New Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
9
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
1.5
1
Temperature
25 °C
85 °C
125 °C
150 °C
0.4
0.2
0
-0.2
VO = 3.3 V
Iout= 1mA
CO = 4.7uF
1
0.5
Temperature
-55C
85C
-40C
125C
0C
150C
25C
0
-0.5
-1
-0.4
-1.5
-0.6
-0.8
20
40
60
80
100
IOUT (mA)
120
140
Figure 6-7. Output Regulation vs Load Current for New Chip
Short-Circuit Current − (A)
0.4
4
8
10
VIN (V)
12
5
VI = 6 V
VO = 3.3 V
Ci = 1 mF
Cbyp = 0.01 mF
3
0.3
0.25
0.2
14
16
6000
VO
I SC
4
0.35
0.15
5400
4800
2
4200
1
3600
0
3000
-1
2400
VIN = 6 V
Cbyp = 10 nF
VO = 3.3 V
-2
-3
1800
1200
-4
600
0.1
-5
0
0.05
-6
0
−500
0
0
500
1000
Time − (ms)
1500
0.5
0.35
0.3
0.25
0.2
0.15
800
-600
1000
Figure 6-10. Short-Circuit Current vs Time for New Chip
5
6000
VO
I SC
4
3
Output Voltage - (V)
0.4
400
600
200s/div
VIN = 6 V
VI = 16 V
VO = 3.3 V
Ci = 1 mF
Cbyp = 0.01 mF
0.45
200
2000
Figure 6-9. Short-Circuit Current vs Time for Legacy Chip
Short-Circuit Current − (A)
6
Figure 6-8. Output Regulation vs Input Voltage for New Chip
Output Voltage - (V)
0.5
0.45
-2
160
5400
4800
2
4200
1
3600
0
3000
-1
2400
VIN = 16 V
Cbyp = 10 nF
VO = 3.3 V
-2
-3
1800
1200
-4
600
0.1
-5
0
0.05
-6
0
−100
0
100
300
500
Time − (ms)
Output Current - (mA)
0
700
200
400
600
200s/div
800
Output Current - (mA)
Load Regulation (mV)
0.6
-55 °C
-40 °C
0 °C
Line Regulation (mV)
VI = 4.3 V
VO = 3.3 V
CO = 4.7uF
0.8
-600
1000
Figure 6-11. Short-Circuit Current vs Time for Legacy Chip
Figure 6-12. Short-Circuit Current vs Time for new Chip
10
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
380
320
VO = 3.3 V
360
340
Current Limit (mA)
ISC − (mA)
300
280
260
240
320
300
VI = 4.3 V
280
260
240
-55 °C
-40 °C
0 °C
220
220
Temperature
25 °C
85 °C
125 °C
150 °C
200
0
200
0
0.5
1
1.5
2
2.5
Output Voltage − (V)
3
Figure 6-13. Short-Circuit Current vs Output Voltage for Legacy
Chip
1
1.5
2
VOUT (V)
2.5
3
3.5
Figure 6-14. Short-Circuit Current vs Output Voltage for New
Chip
352
1200
VI = 4.3 V
CO = 4.7uF
VO = 3.3 V
Cbyp = 10 nF
1100
1000
Ground Pin Current − mA
351
Current Limit (mA)
0.5
3.5
350
349
900
800
700
600
500
400
300
200
348
-55
-25
5
35
65
Temperature (C)
95
125
100
150
0
20
0
40
60
80
100
Load Current − mA
120
140
160
Figure 6-15. Short-Circuit Current vs Temperature for New Chip
Figure 6-16. Ground Pin Current vs Load Current for Legacy
Chip
1200
100
1100
VI = 4.3 V
VO = 3.3 V
CO = 4.7uF
900
80
IGND (A)
800
700
600
500
400
Temperature
-55 °C
85 °C
-40 °C
125 °C
0 °C
150 °C
25 °C
300
200
100
0
0
20
VI = 5 V
VO = 3.3 V
Co = 10 mF
Cbyp = 0 nF
90
40
60
80
IOUT
100
120
140
160
Ripple Rejection − (dB)
1000
70
50 mA
1 mA
60
50
40
150 mA
30
20
10
0
10
100
1k
10k
100k
1M
Frequency − (Hz)
Figure 6-17. Ground Pin Current vs Load Current for New Chip
Figure 6-18. Ripple Rejection vs Frequency for Legacy Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
11
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
120
100
1 mA
150 mA
50 mA
110
80
90
Ripple Rejection − (dB)
Ripple Rejection - (dB)
100
80
70
60
VIN = 5 V
V0 = 3.3 V
C0 = 10 uF
Cbyp = 0 nF
50
40
30
70
1 mA
60
40
30
20
10
10
102
103
104
105
Frequency - (Hz)
106
50 mA
50
20
0
101
VI = 3.7 V
VO = 3.3 V
Co = 10 mF
Cbyp = 0 nF
90
150 mA
0
107
10
100
1k
10k
100k
1M
Frequency − (Hz)
VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF
Figure 6-19. Ripple Rejection vs Frequency for New Chip
Figure 6-20. Ripple Rejection vs Frequency for Legacy Chip
120
100
1 mA
150 mA
50 mA
110
80
90
Ripple Rejection − (dB)
Riple Rejection - (dB)
100
80
70
60
50
40
30
70
50
40
20
10
1x103
1x104
1x105
Frequency - (Hz)
1x106
1x107
50 mA
30
10
1x102
1 mA
60
20
0
1x101
VI = 5 V
VO = 3.3 V
Co = 4.7 mF
Cbyp = 10 nF
90
150 mA
0
10
100
VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF
Figure 6-21. Ripple Rejection vs Frequency for New Chip
90
80
70
30
VIN = 5 V
V0 = 3.3 V
C0 = 4.7 uF
Cbyp = 10 nF
70
40
1x106
1x107
100 mA
30
10
1x103
1x104
1x105
Frequency - (Hz)
10 mA
50
20
1x102
1 mA
60
10
Figure 6-23. Ripple Rejection vs Frequency for New Chip
12
80
20
0
1x101
1M
VI = 5 V
VO = 3.3 V
Co = 4.7 mF
Cbyp = 10 nF
90
Ripple Rejection − (dB)
Ripple Rejection - (dB)
100
40
100k
100
1 mA
150 mA
50 mA
110
50
10k
Figure 6-22. Ripple Rejection vs Frequency for Legacy Chip
120
60
1k
Frequency − (Hz)
0
10
100
1k
10k
Frequency − (Hz)
100k
1M
Figure 6-24. Ripple Rejection vs Frequency for Legacy Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
120
10
100
90
Output Impedance − (W)
Ripple Rejection - (dB)
Ci = 1 mF
Co = 10 mF
VO = 3.3 V
1 mA
10 mA
100 mA
110
80
70
60
50
VIN = 5 V
V0 = 3.3 V
C0 = 4.7 uF
Cbyp = 10 nF
40
30
20
1
1 mA
10 mA
100 mA
0.1
0.01
10
0
1x101
1x102
1x103
1x104
1x105
Frequency - (Hz)
1x106
1x107
Noise Density − (mV/ Hz)
Output Impedance − (W)
100 mA
0.1
0.01
1
1M
Cbyp = 100 pF
Cbyp = 1 nF
0.1
Cbyp = 10 nF
0.01
100
1k
10k
100k
100
1M
Figure 6-27. Output Impedance vs Frequency for Legacy Chip
10
5
1k
10k
100k
Frequency − (Hz)
Frequency − (Hz)
Figure 6-28. Output Noise Density vs Frequency for Legacy
Chip
10
CBYP
100 pF
1 nF
10 nF
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
1x102
1x103
1x104
1x105
Frequency - (Hz)
1x106
1x107
ILOAD = 1 mA
Noise Density − (mV/ Hz)
Noise Density - (V / Hz)
100k
ILOAD = 150 mA
10 mA
0.002
0.001
1x101
10k
10
1 mA
0.001
10
1k
Figure 6-26. Output Impedance vs Frequency for Legacy Chip
Ci = 1 mF
Co = 4.7 mF
VO = 3.3 V
1
100
Frequency − (Hz)
Figure 6-25. Ripple Rejection vs Frequency for New Chip
10
0.001
10
1
Cbyp = 100 pF
Cbyp = 1 nF
0.1
Cbyp = 10 nF
0.01
100
Figure 6-29. Output Noise Density vs Frequency for New Chip
1k
10k
Frequency − (Hz)
100k
Figure 6-30. Output Noise Density vs Frequency for Legacy
Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
13
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
1.8
CBYP
100pF
1nF
10nF
ILOAD = 1mA
2
1
0.5
RL = 3.3 kW
1.4
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
1x101
VO = 3.3 V
Cbyp = 10 nF
1.6
Input Current − (mA)
Noise Density - (V/ Hz)
10
5
1.2
1
0.8
RL = Open
0.6
0.4
0.2
2
3
1x10
4
5
6
1x10
1x10
1x10
Frequency - (Hz)
7
1x10
1x10
0
0
1
2
3
4
5
6
Input Voltage − (V)
Figure 6-31. Output Noise Density vs Frequency for New Chip
Figure 6-32. Input Current vs Input Voltage for Legacy Chip
1000
1400
Temperature
-55 °C
25 °C
-40 °C
85 °C
0 °C
125 °C
800
150 °C
1200
Ground Current − (C)
IGND (A)
600
VO = 3.3 V
CO = 4.7uF
400
200
0
VO = 3.3 V
Cbyp = 10 nF
150 mA
1000
800
600
1 mA
400
50 mA
0 mA
200
-200
0
2
4
6
8
VIN
10
12
14
10 mA
16
0
−50
−25
0
25
50
75
100
125
150
Temperature − (°C)
Figure 6-33. Input Current vs Input Voltage for New Chip
Figure 6-34. Ground-Pin Current vs Temperature for Legacy
Chip
1400
1200
IGND (A)
1000
Load Current
0
50mA
1mA
150mA
10mA
VI = 4.3 V
VO = 3.3 V
800
600
400
200
0
-75
-50
-25
0
25
50
75
Temperature C
100
125
150
Figure 6-35. Ground-Pin Current vs Temperature for New Chip
14
Figure 6-36. 2.2-μF Stable ESR Range for Output Voltage ≤ 2.3 V
for Legacy Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, ON/OFF pin tied to
VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
Figure 6-37. 4.7-μF Stable ESR Range for Output Voltage ≤ 2.3 V Figure 6-38. 2.2-μF, 3.3-μF Stable ESR Range for Output Voltage
for Legacy Chip
≥ 2.5 V for Legacy Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
15
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
7 Detailed Description
7.1 Overview
The LP2985 is a fixed-output, low-noise, high PSRR, low-dropout regulator that offers exceptional, cost-effective
performance for both portable and nonportable applications. The LP2985 has an output tolerance of 1% across
line, load, and temperature variation (for the new chip) and is capable of delivering 150 mA of continuous load
current.
This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output
pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line
and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C.
7.2 Functional Block Diagram
VIN
VOUT
R1
Current
Limit
R2
+
–
UVLO
BYPASS
RF
GND
ON/OFF
Internal
Controller
Bandgap
Reference
VREF = 1.2 V
Output
Pull-down
GND
GND
Thermal
Shutdown
GND
7.3 Feature Description
7.3.1 Output Enable
The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the
ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled with the ON/OFF pin
voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is
not needed, connect the ON/OFF pin to the input of the device.
The device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin
voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the output voltage.
7.3.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
16
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
RDS(ON) =
VDO
IRATED
(1)
7.3.3 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the
output current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application note.
Figure 7-1 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
IOUT
0V
0 mA
IRATED
ICL
Figure 7-1. Current Limit
7.3.4 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
17
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
7.3.5 Output Pulldown
The new chip has an output pulldown circuit. The output pulldown activates in the following conditions:
•
•
When the device is disabled (VON/OFF < VON/OFF(LOW))
If 1.0 V < VIN < VUVLO
Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. See the Reverse Current section for more details.
7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VON/OFF
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VON/OFF > VON/OFF(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VON/OFF > VON/OFF(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VON/OFF < VON/
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
OFF(LOW)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
•
18
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet
decreased to less than the enable falling threshold
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum
ON/OFF pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor
is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
19
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage
and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and
output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of
approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be
necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches
from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.3 Noise Bypass Capacitor (CBYPASS)
The LP2985 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal
band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is biased in the microampere
range and, thus, cannot be loaded significantly, otherwise, the output (and, correspondingly, the output of the
regulator) changes. Thus, for best output accuracy, dc leakage current through CBYPASS must be minimized as
much as possible and must never exceed 100 nA. The CBYPASS capacitor also impacts the start-up behavior of
the regulator. Inrush current and start-up time increase with larger bypass capacitor values.
Use a 10-nF capacitor for CBYPASS. Ceramic and film capacitors are good choices for this purpose.
8.1.4 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, use external protection to protect the device. Reverse
current is not limited in the device, so external limiting is required if extended reverse voltage operation is
anticipated.
20
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
Figure 8-1 shows one approach for protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
CIN
COUT
GND
GND
GND
GND
Figure 8-1. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.5 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(2)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(3)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.6 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
21
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(4)
where:
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(5)
where:
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.
22
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
8.2 Typical Application
Figure 8-2 shows the standard usage of the LP2985 as a low-dropout regulator.
LP2985
VIN
1
VOUT
5
2.2 µF
1 µF
GND
ON/OFF
2
3
4
BYPASS
10 nF
Figure 8-2. LP2985 Typical Application
8.2.1 Design Requirements
Minimum COUT value for stability (can be increased without limit for improved stability and transient response)
ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used.
Optional BYPASS capacitor for low-noise operation.
8.2.2 Detailed Design Procedure
8.2.2.1 ON/OFF Operation
The LP2985 allows for a shutdown mode via the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device
OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to
the input to ensure that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
23
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
8.2.3 Application Curves
3.36
100
VO = 3.3 V
Cbyp = 10 nF
DIL = 100 mA
150
0
−50
VO
3.28
−100
3.26
−150
3.24
−200
3.22
−250
3.58
3.46
-50
3.34
-100
3.28
-150
3.22
-200
3.16
-250
0
20
40
60
150
3.36
100
IL
VO = 3.3 V
Cbyp = 10 nF
DIL = 150 mA
0
−50
−100
−150
3.26
3.24
−200
3.22
−250
3.7
3.64
150
3.58
3.46
-50
3.34
-100
3.28
-150
3.22
-200
3.16
-250
0
20
40
60
80
20s/div
100
120
-300
140 150
dI/dt = 1 A/μ
Figure 8-6. Load Transient for New Chip
200
3.82
150
3.76
3.36
100
IL
VO = 3.3 V
Cbyp = 0 nF
DIL = 150 mA
50
0
−50
VO
−100
−150
3.24
−200
3.22
−250
Output Voltage - (V)
3.4
3.38
Load Current − (mA)
Output Voltage − (V)
0
3.4
3.7
300
VO 250
IL
200
3.64
150
3.58
100
V0 = 3.3V
Cbyp = 0 nF
IL = 150 mA
3.52
3.46
50
0
3.4
-50
3.34
-100
3.28
-150
3.22
-200
3.16
-250
3.1
0
20 ms/div→
20
40
60
80
20s/div
100
120
-300
140 150
dI/dt = 1 A/μ
Figure 8-7. Load Transient Response for Legacy
Chip
24
50
3.1
Figure 8-5. Load Transient Response for Legacy
Chip
3.26
100
VO = 3.3V
Cbyp =10 nF
IL=150mA
3.52
20 ms/div→
3.28
-300
140 150
300
VO 250
IL
200
3.76
50
3.28
3.3
120
3.82
VO
3.32
100
Figure 8-4. Load Transient Response for New Chip
Output Voltage - (V)
200
Load Current − (mA)
Output Voltage − (V)
3.4
3.34
80
20s/div
dI/dt = 1 A/μ
3.38
3.3
0
3.1
Figure 8-3. Load Transient Response for Legacy
Chip
3.32
50
3.4
20 ms/div→
3.34
100
V0 = 3.3V
Cbyp = 10nF
IL=100mA
3.52
Load Current - (mA)
3.3
50
IL
3.7
3.64
Load Current - (mA)
3.34
Output Voltage -(V)
150
300
VO 250
IL
200
3.76
Load Current − (mA)
Output Voltage − (V)
3.38
3.32
3.82
200
3.4
Load Current - (mA)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA,
ON/OFF pin tied to VIN, CIN = 1.0 µF, and COUT = 4.7 µF (unless otherwise noted)
Figure 8-8. Load Transient Response for New Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
3.39
5
VO = 3.3 V
Cbyp = 0 nF
IO = 150 mA
4
3.5
3.33
3.31
VO
Input Voltage − (V)
Output Voltage − (V)
3.35
4.5
3
3.27
5.5
3.35
5
3.33
4.5
3.31
4
3.29
3.5
0
40
80
120
160
20 s/div
200
3
280
240
VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt =
1 V/μ
2
20 ms/div→
Figure 8-9. Line Transient Response for Legacy
Chip
3.41
3.37
3.27
2.5
3.29
3.39
6.5
VO
VIN 6
Figure 8-10. Line Transient Response for New Chip
3.312
5.5
7
VO
VIN 6.5
3.31
3.35
VO = 3.3 V
Cbyp = 10 nF
IO = 150 mA
4.5
4
3.33
3.5
3.31
3
Output Voltage - (V)
Output Voltage − (V)
VI
3.37
Input Voltage − (V)
5
3.39
3.308
6
3.306
5.5
3.304
5
3.302
4.5
3.3
4
3.298
3.5
3.296
3.29
VO
3.27
0
2.5
20 ms/div→
5.5
3.39
5
3.35
VO = 3.3 V
Cbyp = 0 nF
IO = 1 mA
60
80
100 120
20 s/div
140
160
180
3.41
4.5
4
3.33
3.5
3.31
3
3.39
6.5
VO
VIN 6
3.37
5.5
3.35
5
3.33
4.5
3.31
4
3.29
3.5
3.27
2.5
3.29
0
VO
3.27
3
200
Figure 8-12. Line Transient Response for New Chip
Output Voltage - (V)
3.41
Input Voltage − (V)
Output Voltage − (V)
Figure 8-11. Line Transient Response for Legacy
Chip
VI
40
VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt
= 1 V/μ
2
3.37
20
2
20 ms/div→
Figure 8-13. Line Transient Response for Legacy
Chip
40
80
120
160
20 s/div
200
240
Input Voltage - (V)
VI
3.37
3.41
Input Voltage - (V)
5.5
Output Voltage - (V)
3.41
Input Voltage - (V)
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
3
280
VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1
V/μ
Figure 8-14. Line Transient Response for New Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
25
LP2985
3.39
5
Output Voltage − (V)
4.5
4
3.35
3.33
VO = 3.3 V
Cbyp = 10 nF
IO = 1 mA
3.5
3.31
VO
3
3.29
2.5
3.27
2
0
Figure 8-15. Line Transient Response for Legacy
Chip
3
6
0
4
VON/OFF − (V)
Output Voltage − (V)
2
Output Voltage - (V)
8
VO = 3.3 V
Cbyp = 0
IO = 150 mA
−2
VON/OFF
2
80
100
20 s/div
120
140
16
VO
VON 14
V0 = 3.3 V
Cbyp =0
ILOAD = 150 mA
2
12
1
10
0
8
-1
6
-2
4
-3
2
-4
−3
0
−4
60
4
10
3
−1
40
Figure 8-16. Line Transient Response for New Chip
VO
1
20
7
VO 6.75
VIN 6.5
6.25
6
5.75
5.5
5.25
5
4.75
4.5
4.25
4
3.75
3.5
3.25
3
160170
VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt =
1 V/μ
100 ms/div→
4
3.312
3.311
3.31
3.309
3.308
3.307
3.306
3.305
3.304
3.303
3.302
3.301
3.3
3.299
3.298
3.297
3.296
100
200
300
400
100s/div
500
VON - (V)
VIN
3.37
Output Voltage - (V)
5.5
Input Voltage − (V)
3.41
Input Voltage - (V)
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
0
700
600
0
100 ms/div→
4
10
4
VO
8
1
6
0
−1
VO = 3.3 V
Cbyp = 100 pF
ILOAD = 150 mA
4
−2
VON/OFF
VON/OFF − (V)
Output Voltage − (V)
2
Output Voltage - (V)
3
3
16
VO
V0N 14
2
12
1
10
0
8
V0 = 3.3 V
Cbyp = 100 pF
ILOAD = 150 mA
-1
-2
-3
2
4
2
-4
0
−3
6
Von - (V)
Figure 8-18. Turn-On Time for New Chip
Figure 8-17. Turn-On Time for Legacy Chip
200
400
600
200s/div
800
1000
0
1200
0
−4
200 ms/div→
Figure 8-20. Turn-On Time for New Chip
Figure 8-19. Turn-On Time for Legacy Chip
26
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
4
10
4
3
16
Vo
VON 14
2
12
1
10
VO
3
1
6
0
−1
VO = 3.3 V
Cbyp = 1 nF
ILOAD = 150 mA
4
VON/OFF − (V)
Output Voltage − (V)
2
Output Voltage - (V)
8
VON/OFF
−2
0
8
V0= 3.3 V
Cbyp = 1nF
ILOAD = 150mA
-1
6
-2
4
-3
2
VON - (V)
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
2
-4
−3
0
2
4
0
−4
6
2 ms/div
8
10
0
12
COUT = 4.7 μF
2 ms/div→
COUT = 4.7 μF
Figure 8-22. Turn-On Time for New Chip
4
Input
4
10
3
3
6
0
4
VO = 3.3 V
Cbyp = 10 nF
ILOAD = 150 mA
Output
−2
2
VON/OFF − (V)
Output Voltage − (V)
1
Output Voltage - (V)
8
2
−1
16
VOUT
VON
2
1
0
8
V0 = 3.3 V
Cbyp = 10 nF
ILOAD = 150 mA
-1
6
-2
4
-3
2
0
0
−4
Figure 8-23. Turn-On Time
20
40
60
20ms/div
80
100
0
120
COUT = 4.7 μF
20 ms/div→
COUT = 4.7 μF
12
10
-4
−3
14
VON - (V)
Figure 8-21. Turn-On Time for Legacy Chip
Figure 8-24. Turn-On Time for New Chip
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
27
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
8.3 Power Supply Recommendations
A power supply can be used at the input voltage within the ranges given in the Recommended Operating
Conditions table. Use bypass capacitors as described in the Layout Guidelines section.
8.4 Layout
8.4.1 Layout Guidelines
•
•
•
Bypass the input pin to ground with a bypass capacitor.
The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system.
Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and
the GND pin of the system.
For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation.
8.4.2 Layout Example
VIN
VOUT
COUT
CIN
GND
PLANE
CBYPASS
ON/OFF
BYPASS
Figure 8-25. Layout Diagram
28
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
LP2985
www.ti.com
SLVS522Q – JULY 2004 – REVISED DECEMBER 2022
9 Device and Documentation Support
9.1 Device Nomenclature
Table 9-1. Available Options(1)
PRODUCT
LP2985-xxyyyz
Legacy chip
LP2985-xxyyyzM3
New chip
(1)
VOUT
xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V).
yyy is the package designator.
z is the package quantity. R is for large quantity reel, T is for small quantity reel.
xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V).
yyy is the package designator.
z is the package quantity. R is for large quantity reel, T is for small quantity reel.
M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process
technology.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LP2985
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LP2985-10DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LRCG
Samples
LP2985-10DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LRCG
Samples
LP2985-18DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPHG, LPHL)
Samples
LP2985-18DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPHG
Samples
LP2985-18DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPHG
Samples
LP2985-18DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPHG, LPHL)
Samples
LP2985-18DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPHG
Samples
LP2985-25DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPLG, LPLL)
Samples
LP2985-25DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPLG, LPLL)
Samples
LP2985-28DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPGG, LPGL)
Samples
LP2985-28DBVT
LIFEBUY
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPGG, LPGL)
LP2985-28DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPGG
LP2985-29DBVR
LIFEBUY
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPMG, LPML)
LP2985-30DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPNG, LPNL)
Samples
LP2985-30DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPNG, LPNL)
Samples
LP2985-30DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPNG, LPNL)
Samples
LP2985-30DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPNG, LPNL)
Samples
LP2985-33DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPFG, LPFL)
Samples
LP2985-33DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPFG
Samples
LP2985-33DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPFG
Samples
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LP2985-33DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPFG, LPFL)
Samples
LP2985-33DBVTE4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPFG
Samples
LP2985-33DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPFG
Samples
LP2985-50DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPSG, LPSL)
Samples
LP2985-50DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPSG, LPSL)
Samples
LP2985-50DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPSG, LPSL)
Samples
LP2985-50DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPSG, LPSL)
Samples
LP2985A-10DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LRDG
Samples
LP2985A-10DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LRDG
Samples
LP2985A-18DBVJ
ACTIVE
SOT-23
DBV
5
10000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPTL
Samples
LP2985A-18DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPTG, LPTL)
Samples
LP2985A-18DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPTG
Samples
LP2985A-18DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPTG, LPTL)
Samples
LP2985A-25DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPUG, LPUL)
Samples
LP2985A-25DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPUG, LPUL)
Samples
LP2985A-25DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPUG, LPUL)
Samples
LP2985A-28DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPJG, LPJL)
Samples
LP2985A-28DBVT
LIFEBUY
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPJG, LPJL)
LP2985A-29DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LPZG, LPZL)
Samples
LP2985A-30DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LRAG, LRAL)
Samples
LP2985A-30DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LRAG, LRAL)
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LP2985A-33DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPKG, LPKL)
Samples
LP2985A-33DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPKG
Samples
LP2985A-33DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(LPKG, LPKL)
Samples
LP2985A-33DBVTE4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPKG
Samples
LP2985A-33DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LPKG
Samples
LP2985A-50DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LR1G, LR1L)
Samples
LP2985A-50DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LR1G, LR1L)
Samples
LP2985A-50DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(LR1G, LR1L)
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
