LP2985IM5-2.0/NOPB

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 LP2985LV-N Micropower 150-mA, Low-Noise, Low-Dropout Regulator in SOT-23 and DSBGA Packages 1 Features 3 Description • • • • • • • • • • • The LP2985LV-N is a 150-mA, fixed-output voltage regulator designed to provide high performance and low noise in applications requiring output voltages ≤ 2 V. 1 Wide Supply Voltage Range: 2.2 V to 16 V Ensured 150-mA Output Current Requires Minimum External Components Stable With Low-ESR Output Capacitor < 1-µA Quiescent Current When Shut Down Low Ground Pin Current at all Loads Output Voltage Accuracy 1% (A Grade) High Peak Current Capability Low ZOUT: 0.3-Ω Typical (10 Hz to 1 MHz) Overtemperature/Overcurrent Protection −40°C to +125°C Junction Temperature Range Using an optimized vertically integrated PNP (VIP) process, the LP2985LV-N delivers unequaled performance in all specifications critical to batterypowered designs: • Ground Pin Current: Typically 825 µA at 150-mA load, and 75 µA at 1-mA load. • Enhanced Stability: The LP2985LV-N is stable with output capacitor equivalent series resistance (ESR) as low as 5 mΩ, which allows the use of ceramic capacitors on the output. • Sleep Mode: Less than 1-µA quiescent current when ON/OFF pin is pulled low. • Precision Output: 1% tolerance output voltages available (A grade). • Low Noise: By adding a 10-nF bypass capacitor, output noise can be reduced to 30 µV (typical). 2 Applications • • • • Cellular Phone Palmtop/Laptop Computer Personal Digital Assistant (PDA) Camcorder, Personal Stereo, Camera Device Information(1) PART NUMBER LP2985LV-N PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm DSBGA (5) 1.164 mm × 0.987 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Space Typical Application VIN IN CIN 1 µF VOUT OUT LP2985LV COUT 2.2 µF GND ON/OFF ON/OFF BYPASS CBYPASS 0.01 µF Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 11 11 12 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application .................................................. 14 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 22 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Example .................................................... DSBGA Mounting.................................................. DSBGA Light Sensitivity ....................................... 22 22 23 23 11 Device and Documentation Support ................. 24 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision P (April 2013) to Revision Q Page • Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; change pin names in text and app circuit drawing "VOUT" and "VIN" to "OUT" and "IN" .................. 1 • Deleted lead temperature spec per new TI documentation guidelines ................................................................................. 4 • Changed value of RθJA for the SOT-23 package is 220°C/W ..." to "...value of RθJA for the SOT-23 package is 175.7°C/W..." in footnote 3 to Abs Max table - see update thermal info for SOT-23 in Thermal Information; add RθJA values to footnote 3 to Abs Max ............................................................................................................................................. 4 • Added Power Dissipation and Estimating Junction Temperature subsections ................................................................... 19 Changes from Revision O (April 2013) to Revision P • 2 Page Changed layout of National Semiconductor data sheet to TI format .................................................................................... 1 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 5 Pin Configuration and Functions DBV Package 5 Pin SOT-23 Top View YPB Package 5-Pin DSBGA Top View (1) The actual physical placement of the package marking varies from part to part. Package marking contains date code and lot traceability information and will vary considerably. Package marking does not correlate to device type. Pin Functions PIN NAME TYPE DESCRIPTION SOT-23 DSBGA BYPASS 4 B2 I/O Bypass capacitor for low noise operation GND 2 A1 — Common ground (device substrate) IN 1 C3 I Input voltage ON/OFF 3 A3 I Logic high enable input OUT 5 C1 O Regulated output voltage Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 3 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Input supply voltage –0.3 16 V Shutdown input voltage –0.3 16 V Power dissipation (3) Internally Limited Output voltage (4) –0.3 IOUT 9 V Short-circuit protected Input-output voltage (5) –0.3 16 V Storage temperature, Tstg –65 150 °C (1) (2) (3) (4) (5) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: TJ _ MAX TA PMAX RT JA Where the value of RθJA for the SOT-23 package is 175.7°C/W in a typical PC board mounting or 178.8°C/W for YPB-type DSBGA package. Exceeding the maximum allowable dissipation causes excessive die temperature, and the regulator goes into thermal shutdown. If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2985LV-N output must be diodeclamped to GND. The output PNP structure contains a diode between the IN to OUT pins that is normally reverse-biased. Reversing the polarity from IN to OUT turns on this diode. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Pins 3 and 4 (SOT-23) Pins A3 and B2 (DSBGA) ±1000 Pins 1, 2, and 5 (SOT-23) Pins A1, C1, and C3 (DSBGA) ±2000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN Supply input voltage VON/OFF ON/OFF input voltage IOUT Output current TJ Operating junction temperature (1) 4 MIN MAX 2.2 (1) 16 V 0 VIN V 150 mA 125 °C –40 UNIT Recommended minimum VIN is the greater of 2.2 V or VOUT(MAX) + rated dropout voltage (maximum) for operating load current. Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 6.4 Thermal Information LP2985LV-N THERMAL METRIC (1) SOT-23 (DBV) DSBGA (YPB) UNIT 5 PINS RθJA (2) Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (1) (2) 175.7 178.8 °C/W 78 2.1 °C/W 30.8 146.3 °C/W 2.8 1.9 °C/W 30.3 146.3 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. 6.5 Electrical Characteristics Unless otherwise specified: VIN = VO(NOM) + 1 V, IL = 1 mA, CIN = 1 µF, COUT = 4.7 µF, VON/OFF = 2 V, TJ = 25°C. (1) PARAMETER TEST CONDITIONS Output voltage tolerance ΔVO/ΔVIN Output voltage line regulation VIN(MIN) Minimum input voltage required to maintain output regulation (3) Dropout voltage (3) TYP −1.5 1.5 −2.5 2.5 1 mA < IL < 50 mA –40°C ≤ TJ ≤ 125°C −2.5 2.5 −3.5 3.5 1 mA < IL < 150 mA −2.5 2.5 −3 3 1 mA < IL < 150 mA –40°C ≤ TJ ≤ 125°C −3.5 3.5 −4 4 VO(NOM) + 1 V ≤ VIN ≤ 16 V 0.007 VO(NOM) + 1 V ≤ VIN ≤ 16 V –40°C ≤ TJ ≤ 125°C 2.05 –40°C ≤ TJ ≤ 125°C IL = 50 mA, –40°C ≤ TJ ≤ 125°C IL = 1 mA, –40°C ≤ TJ ≤ 125°C IL = 10 mA, –40°C ≤ TJ ≤ 125°C IL = 150 mA 280 95 110 220 300 500 825 1200 65 350 mV 95 125 75 110 170 120 220 400 300 500 825 1200 900 IL = 150 mA, –40°C ≤ TJ ≤ 125°C V 600 400 IL = 50 mA, –40°C ≤ TJ ≤ 125°C %/V 150 250 350 170 120 IL = 50 mA 120 125 75 IL = 10 mA 150 2.2 600 65 0.014 2.05 250 280 %VNOM 0.032 2.2 120 IL = 150 mA 0.007 0.032 IL = 1 mA (3) 0.014 UNIT MAX 1 IL = 0 mA, –40°C ≤ TJ ≤ 125°C (1) (2) TYP 1.5 IL = 0 mA Ground pin current MIN −1 IL = 150 mA, –40°C ≤ TJ ≤ 125°C IGND MAX −1.5 IL = 50 mA VIN – VOUT MIN LP2985I-XX (2) 1 mA < IL < 50 mA IL = 1 mA ΔVO LP2985AI-XX (2) μA 900 2000 2000 VON/OFF < 0.3 V 0.01 0.8 0.01 0.8 VON/OFF < 0.15 V –40°C ≤ TJ ≤ 125°C 0.05 2 0.05 2 Exposing the DSBGA device to direct sunlight causes misoperation. See Layout for additional information. Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using statistical quality control (SQC) methods. The limits are used to calculate average outgoing quality level (AOQL). VIN must be the greater of 2.2 V or VOUT(NOM) + dropout voltage to maintain output regulation. Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the value measured with a 1-V differential. Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 5 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: VIN = VO(NOM) + 1 V, IL = 1 mA, CIN = 1 µF, COUT = 4.7 µF, VON/OFF = 2 V, TJ = 25°C.(1) PARAMETER TEST CONDITIONS LP2985AI-XX (2) MIN High = O/P ON VON/OFF ON/OFF input voltage (4) TYP Low = O/P OFF 0.55 0.01 en Output noise voltage IO(SC) (4) (5) 6 Short-circuit current V 0.01 5 VOUT ≥ VO(NOM) − 5% UNIT 0.15 –2 VON/OFF = 5 V Peak output current MAX 0.55 0.15 VON/OFF = 0 V –40°C ≤ TJ ≤ 125°C IO(PK) TYP 1.6 VON/OFF = 5 V –40°C ≤ TJ ≤ 125°C ΔVO/ΔVIN Ripple rejection MIN 1.4 1.6 VON/OFF = 0 V ON/OFF input current MAX 1.4 High = O/P ON –40°C ≤ TJ ≤ 125°C Low = O/P OFF –40°C ≤ TJ ≤ 125°C ION/OFF LP2985I-XX (2) –2 μA 5 15 15 350 350 mA BW = 300 Hz to 50 kHz COUT = 10 μF CBYPASS = 10 nF, VOUT = 1.8 V 30 30 μV(RMS) ƒ = 1 kHz, COUT = 10 μF CBYPASS = 10 nF 45 45 dB 400 400 mA RL = 0 Ω (steady state) (5) The ON/OFF inputs must be properly driven to prevent misoperation. For details, see Operation With ON/OFF Control. The LP2985LV-N has foldback current limiting, which allows a high peak current when VOUT > 0.5 V and then reduces the maximum output current as VOUT is forced to ground (see related curve(s) in Typical Characteristics). Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 6.6 Typical Characteristics Unless otherwise specified: CIN = 1 µF, COUT = 4. 7µF, VIN = VOUT(NOM) + 1, VOUT = 1.8 V, TA = 25°C, ON/OFF pin is tied to VIN. Figure 1. VOUT vs Temperature Figure 2. Short-Circuit Current Figure 3. Short-Circuit Current Figure 4. Short-Circuit Current vs Output Voltage COUT = 4.7 µF Bypass = 10 nF COUT = 4.7 µF Figure 5. Ripple Rejection No Bypass Figure 6. Ripple Rejection Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 7 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com Typical Characteristics (continued) Unless otherwise specified: CIN = 1 µF, COUT = 4. 7µF, VIN = VOUT(NOM) + 1, VOUT = 1.8 V, TA = 25°C, ON/OFF pin is tied to VIN. Figure 7. Output Impedance vs Frequency Figure 8. Output Impedance vs Frequency Figure 9. Noise Density Figure 10. Noise Density Figure 11. Ground Pin vs Load Current 8 Figure 12. Minimum Input Voltage vs Temperature Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 Typical Characteristics (continued) Unless otherwise specified: CIN = 1 µF, COUT = 4. 7µF, VIN = VOUT(NOM) + 1, VOUT = 1.8 V, TA = 25°C, ON/OFF pin is tied to VIN. Figure 13. Minimum Input Voltage vs Temperature Figure 14. Input Current vs VIN Figure 15. Input Current vs VIN Figure 16. Input Current vs VIN Figure 17. Ground Pin Current vs Temperature Figure 18. Instantaneous Short Circuit Current Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 9 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com Typical Characteristics (continued) Unless otherwise specified: CIN = 1 µF, COUT = 4. 7µF, VIN = VOUT(NOM) + 1, VOUT = 1.8 V, TA = 25°C, ON/OFF pin is tied to VIN. Figure 19. Output Characteristics 10 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 7 Detailed Description 7.1 Overview The LP2985LV-N family of fixed-output, ultra-low-dropout and low-noise regulators offers exceptional, costeffective performance for battery-powered applications. Available in output voltages from 1.5 V to 2 V, the family has an output voltage tolerance of 1% for the A version (1.5% for the non-A version) and is capable of delivering 150-mA continuous load current. Standard regulator features, such as overcurrent and overtemperature protection, are also included. Using an optimized vertically integrated PNP (VIP) process, the LP2985LV-N contains several features to facilitate battery-powered designs: • Multiple voltage options • Low dropout voltage, typical dropout of 280 mV at 150-mA load current and 120 mV at 50-mA load current. • Low quiescent current and low ground current, typically 825-μA at 150-mA load, and 75 μA at 1-mA load. • A shutdown feature is available, allowing the regulator to consume only 0.01 µA typically when the ON/OFF pin is pulled low. • Overtemperature protection and overcurrent protection circuitry is designed to safeguard the device during unexpected conditions • Enhanced stability: The LP2985LV-N is stable with output capacitor ESR as low as 5 mΩ, which allows the use of ceramic capacitors on the output. • Low noise: A BYPASS pin allows for low-noise operation, with a typical output noise of 30 µVRMS, with the use of a 10-nF bypass capacitor. 7.2 Functional Block Diagram Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 11 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com 7.3 Feature Description 7.3.1 Multiple Voltage Options In order to meet different application requirement, the LP2985LV-N family provide multiple fixed output options from 1.5 V to 2 V. Contact your regional TI sales team for custom voltage options. 7.3.2 Output Voltage Accuracy Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent. This accuracy error includes the errors introduced by the internal reference and the load and line regulation across the full range of rated load and line operating conditions over temperature, unless otherwise specified by the Electrical Characteristics. Output voltage accuracy also accounts for all variations between manufacturing lots. 7.3.3 Ultra-Low-Dropout Voltage Generally speaking, the dropout voltage often refers to the voltage difference between the input and output voltage (VDO = VIN – VOUT), where the current pass transistor loses its voltage-controlled current capability and the collector (VOUT) to emitter (VIN) voltage becomes constant for a given current and is characterized by the classic VCE(SAT) of the PNP transistor. VDO indirectly specifies a minimum input voltage above the nominal programmed output voltage at which the output voltage is expected to remain within its accuracy boundary. If the input falls below this VDO limit (VIN < VOUT + VDO), then active regulation of the output voltage is no longer possible, and the output voltage decreases as the input voltage falls. 7.3.4 Low Ground Current The LP2985LV-N device uses a vertical PNP process which allows for quiescent currents that are considerably lower than those associated with traditional lateral PNP regulators, typically 825 μA at 150-mA load. 7.3.5 Sleep Mode When the ON/OFF pin is pulled to a low level the LP2985LV-N enters sleep mode, and less than 2-μA quiescent current is consumed. This function is designed for the application which needs a sleep mode to effectively enhance battery life cycle. 7.3.6 Internal Protection Circuitry 7.3.6.1 Short Circuit Protection (Current Limit) The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output. A foldback feature limits the short-circuit current to protect the regulator from damage under all load conditions. If VOUT is forced below 0 V before EN goes high and the load current required exceeds the foldback current limit, the device may not start up correctly. 7.3.6.2 Thermal Protection The LP2985LV-N contains a thermal shutdown protection circuit to turn off the output current when excessive heat is dissipated in the LDO. The thermal time-constant of the semiconductor die is fairly short, and thus the output cycles on and off at a high rate when thermal shutdown is reached until the power dissipation is reduced. The internal protection circuitry of the LP2985LV-N is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown degrades its reliability. 12 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 Feature Description (continued) 7.3.7 Enhanced Stability The LP2985LV-N is designed specifically to work with ceramic output capacitors, utilizing circuitry which allows the regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as 5 mΩ. For output capacitor requirement, refer to Output Capacitor. 7.3.8 Low Noise The LP2985LV-N includes a low-noise reference ensuring minimal noise during operation because the internal reference is normally the dominant term in noise analysis. Further noise reduction can be achieved by adding an external bypass bapacitor between the BYPASS pin and the GND pin. 7.4 Device Functional Modes 7.4.1 Operation with VOUT(TARGET) + 0.6 V ≥ VIN > 16 V The device operate if the input voltage is equal to, or exceeds VOUT(TARGET) + 0.6 V. At input voltages below the minimum VIN requirement, the devices do not operate correctly and output voltage may not reach target value. 7.4.2 Operation With ON/OFF Control If the voltage on the ON/OFF pin is less than 0.15 V, the device is disabled, and in this state shutdown current does not exceed 2 μA. Raising ON/OFF above 1.6 V initiates the start-up sequence of the device. Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 13 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP2985LV-N is a linear voltage regulator operating from 2.2 V to 16 V on the input and regulating voltages from 1.5 V to 2 V with 1% accuracy (A-grade) and 150-mA maximum output current. Efficiency is defined by the ratio of output voltage to input voltage because the LP2985LV-N is a linear voltage regulator. To achieve high efficiency, the dropout voltage (VIN – VOUT) must be as small as possible, thus requiring a very-low-dropout LDO. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to ensure a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. 8.2 Typical Application *ON/OFF input must be actively terminated. Tie to VIN if this function is not to be used. **Minimum capacitance is shown to ensure stability (may be increased without limit). Ceramic capacitor required for output (see Output Capacitor). ***Reduces output noise (may be omitted if application is not noise critical). Use ceramic or film type with very low leakage current (see Noise Bypass Capacitor). Figure 20. Typical Application Schematic 8.2.1 Design Requirements For typical design parameters, see Table 1. Table 1. Design Parameters 14 DESIGN PARAMETERS VALUE Input voltage 2.8 V ±10% Output voltage 1.8 V ±4% Output current 150 mA (maximum) PSRR at 1 kHz > 50 dB Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 8.2.2 Detailed Design Procedure At 150-mA loading, the dropout of the LP2985LV-N has 600-mV maximum dropout over temperature, thus an 1000-mV headroom is sufficient for operation over both input and output voltage accuracy. The efficiency of the LP2985LV-N in this configuration is VOUT / VIN = 64%. To achieve the smallest form factor, the DSBGA package is selected. Input and output capacitors are selected in accordance with the Capacitor Characteristics section. Ceramic capacitances of 1 μF for the input and one 2.2-μF capacitor for the output are selected. With a VIN of 2.8 V, a VOUT of 1.8 V, and an output current of 150 mA Equation 1 shows the power dissipation to be 150 mW. With an RθJA rating of 178.8°C/W for the DSBGA YPB package, and a maximum operating ambient temperature of 85°C, Equation 2 shows the maximum junction temperature to be approximately 111.8°C. 8.2.2.1 External Capacitors Like any low-dropout regulator, the LP2985LV-N requires external capacitors for regulator stability. These capacitors must be correctly selected for good performance. 8.2.2.1.1 Input Capacitor An input capacitor whose capacitance is ≥ 1 µF is required between the LP2985LV-N input and ground (the amount of capacitance may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. NOTE Tantalum capacitors can suffer catastrophic failure due to surge current when connected to a low-impedance source of power (like a battery or very large capacitor). If a Tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance is ≥ 1 µF over the entire operating temperature range. 8.2.2.1.2 Output Capacitor The LP2985LV-N is designed specifically to work with ceramic output capacitors, utilizing circuitry which allows the regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as 5 mΩ. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR value which is within the stable range. Curves are provided showing the stable ESR range as a function of load current (see Figure 21 and Figure 22). Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 15 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com Figure 21. LP2985LV-N 2.2-µF Stable ESR Range Figure 22. LP2985LV-N 4.7-µF Stable ESR Range NOTE The output capacitor must maintain its ESR within the stable region over the full operating temperature range of the application to assure stability. The LP2985LV-N requires a minimum of 2.2 µF on the output (output capacitor size can be increased without limit). It is important to remember that capacitor tolerance and variation with temperature must be taken into consideration when selecting an output capacitor so that the minimum required amount of output capacitance is provided over the full operating temperature range. Ceramic capacitors can exhibit large changes in capacitance with temperature (see Capacitor Characteristics). The output capacitor must be located not more than 1 cm from the output pin and returned to a clean analog ground. 8.2.2.1.3 Noise Bypass Capacitor Connecting a 10-nF capacitor to the BYPASS pin significantly reduces noise on the regulator output. The capacitor is connected directly to a high-impedance circuit in the bandgap reference. Because this circuit has only a few microamperes flowing in it, any significant loading on this node causes a change in the regulated output voltage. For this reason, DC leakage current through the noise bypass capacitor must never exceed 100 nA and must be kept as low as possible for best output voltage accuracy. 16 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic capacitors with either NPO or COG dielectric typically have very low leakage. 10-nF polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. 8.2.2.2 Capacitor Characteristics The LP2985LV-N is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the 2.2-µF to 4.7-µF range, ceramics are the least expensive and also have the lowest ESR values (making them best for eliminating high-frequency noise). The ESR of a typical 2.2-µF ceramic capacitor is in the range of 10 mΩ to 20 mΩ, which easily meets the ESR limits required for stability by the device. One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Most large value ceramic capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C. Problems may ensue if a 2.2-µF capacitor is used on the output because it drops down to approximately 1 µF at high ambient temperatures (which could cause the LM2985 to oscillate). If Z5U or Y5V capacitors are used on the output, a minimum capacitance value of 4.7 µF must be observed. A better choice for temperature coefficient in ceramic capacitors is X7R, which holds the capacitance within ±15%. Unfortunately, the larger values of capacitance are not offered by all manufacturers in the X7R dielectric. 8.2.2.2.1 Tantalum Tantalum capacitors are less desirable than ceramics for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1 µF to 4.7 µF range. An additional important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. Note that the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. 8.2.2.3 On/OFF Input Operation The LP2985LV-N is shut off by driving the ON/OFF input low, and turned on by pulling it high. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator output on at all times. To assure proper operation, the signal source used to drive the ON/OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds listed inElectrical Characteristics under VON/OFF. To prevent mis-operation, the turnon (and turnoff) voltage signals applied to the ON/OFF input must have a slew rate which is ≥ 40 mV/µs. CAUTION The regulator output voltage cannot be ensured if a slow-moving AC (or DC) signal is applied that is in the range between the specified turnon and turnoff voltages listed under the electrical specification VON/OFF (see Electrical Characteristics). 8.2.2.4 Reverse Input-Output Voltage The PNP power transistor used as the pass element in the LP2985LV-N has an inherent diode connected between the regulator output and input. During normal operation (where the input voltage is higher than the output) this diode is reverse-biased. Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 17 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com VIN VOUT PNP GND Figure 23. Normal Operation However, if the output is pulled above the input, this diode turns ON, and current flows into the regulator output. In such cases, a parasitic SCR can latch, allowing a high current to flow into VIN (and out the ground pin), which can damage the part. In any application where the output may be pulled above the input, an external Schottky diode must be connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP2985LV-N to 0.3V (see Absolute Maximum Ratings). SCHOTTKY DIODE VIN VOUT PNP GND Figure 24. Operation With Schottky Diode 8.2.2.5 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 1. PD(MAX) = (VIN(MAX) – VOUT) × IOUT(MAX) (1) Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance. On the DSBGA (YPB) package, the primary conduction path for heat is through the four bumps to the PCB. On the SOT-23 (DBV) package, the primary conduction path for heat is through the device leads to the PCB, predominately device lead 2 (GND). It is recommended that the trace from lead 2 be extended under the package body and connected to an internal ground plane with thermal vias. The maximum allowable junction temperature (TJ(MAX)) determines maximum power dissipation allowed (PD(MAX)) for the device package. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 2 or Equation 3: TJ(MAX) = TA(MAX) + (RθJA × PD(MAX)) PD(MAX) = (TJ(MAX) – TA(MAX)) / RθJA 18 (2) (3) Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copperspreading area, and is to be used only as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink. 8.2.2.6 Estimating Junction Temperature The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are used in accordance with Equation 4 or Equation 5. TJ(MAX) = TTOP + (ΨJT × PD(MAX)) where • • PD(MAX) is explained in Equation 1. TTOP is the temperature measured at the center-top of the device package. (4) TJ(MAX) = TBOARD + (ΨJB × PD(MAX)) where • • PD(MAX) is explained in Equation 1. TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the package edge. (5) For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal Metrics, available for download at www.ti.com. For more information about measuring TTOP and TBOARD, see Using New Thermal Metrics, available for download at www.ti.com. For more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs, available for download at www.ti.com. Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 19 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com 8.2.3 Application Curves 20 Figure 25. Load Transient Figure 26. Load Transient Figure 27. Load Transient Figure 28. Line Transient Figure 29. Line Transient Figure 30. Line Transient Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 Figure 31. Line Transient Figure 32. Turnon Time Figure 33. Turnon Time Figure 34. Turnon Time Figure 35. Turnon Time Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 21 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com 9 Power Supply Recommendations The LP2985LV-N is designed to operate from a minimum input supply voltage of either 2.2 V, or VOUT + VDO, whichever is higher, up to a maximum input supply voltage of 16 V. However, to ensure that the LP2985LV-N output voltage is well regulated, in specification, and that the dynamic performance is optimum, TI recommends a minimum a minimum input supply voltage of at least VOUT + 1 V. The input supply voltage must be well regulated and free of spurious noise. A minimum capacitor value of 1 µF to be placed within 1 cm of the IN pin. Any good-quality ceramic, tantalum, or film capacitor may be used at the input. 10 Layout 10.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. 10.2 Layout Example VIN Input Capacitor VOUT IN OUT Output Capacitor GND Ground Bypass Capacitor BYPASS ON/OFF Figure 36. LP2985 SOT-23 Package Typical Layout VIN Input Capacitor ON/OFF connect to input control through inner layer or bottom layer C1 C3 VOUT BYPASS Output Capacitor B2 Via A3 A1 Bypass Capacitor Ground Figure 37. LP2985 DSBGA Package Typical Layout 22 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N LP2985LV-N www.ti.com SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 10.3 DSBGA Mounting The DSBGA package requires specific mounting techniques which are detailed in AN-1112 DSBGA Wafer Level Chip Scale Package. Referring to the section Surface Mount Technology (SMT) Assembly Considerations, note that the pad style which must be used with the 5-pin package is the NSMD (non-solder mask defined) type. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device. 10.4 DSBGA Light Sensitivity Exposing the DSBGA device to direct sunlight cause misoperation of the device. Light sources such as Halogen lamps can also affect electrical performance if brought near to the device. The wavelengths which have the most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. A DSBGA test board was brought to within 1 cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a deviation of less than 0.1% from nominal. Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N 23 LP2985LV-N SNOS510Q – NOVEMBER 1999 – REVISED OCTOBER 2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For additional information, see the following: • AN-1112 DSBGA Wafer Level Chip Scale Package • Semiconductor and IC Package Thermal Metrics (SPRA953) • Using New Thermal Metrics • Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs 11.1.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated Product Folder Links: LP2985LV-N PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LP2985AIM5-1.5/NOPB LIFEBUY SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCHA LP2985AIM5-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LAYA Samples LP2985AIM5-2.0/NOPB LIFEBUY SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCDA LP2985AIM5X-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LAYA Samples LP2985AIM5X-2.0/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCDA Samples LP2985IM5-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LAYB Samples LP2985IM5-2.0/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCDB Samples LP2985IM5X-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LAYB Samples LP2985IM5X-2.0/NOPB LIFEBUY SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LCDB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of