User's Guide
SNVA056B – August 2002 – Revised May 2013
AN-1241 LP2995 Evaluation Board
1
Introduction
The LP2995 evaluation board is designed to provide the design engineer with a fully functional prototype
system in which to evaluate the LP2995 in both a static environment and with a complete memory system.
There are two versions of the board, while identical in functionality they differ in the package implemented,
either an SO-8 or LLP-16 LP2995 is used. This document contains information regarding the evaluation
board. For more information regarding the LP2995, see the device-specific data sheet.
2
Schematic
The following schematic was used to create the layout.
Figure 1. Schematic
Table 1. Bill Of Materials (BOM)
Name
Value
U1
Description
Manufacturer
Model Number
LP2995 DDR Linear Regulator
Texas Instruments
LP2995M or LP2995LQ
C1
0.1 µF
1206 Ceramic Capacitor X7R 25V
Vishay Vitrammon
VJ1206Y104KXXAT
C2
330 µF
6.3 V Electrolytic Radial FC Series
Panasonic
EEU-FC0J331S
C3
330 µF
6.3 V Electrolytic Radial FC Series
Panasonic
EEU-FC0J331S
Panasonic
EEU-FC0J680
C4
C5
Not Connected
68 µF
6.3 V Electrolytic Radial FC series
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1
Application
3
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Application
The LP2995 evaluation board can be used immediately in either a static test environment to check
functionality or in a memory termination scheme on a motherboard. In either implementation the following
steps should be taken to ensure correct operation:
1. Connect leads from the evaluation board. The board layout has been designed to allow banana jack
sockets to be directly soldered.
2. VIN should be connected to a 2.5 V power supply. This pad connects both the AVIN and PVIN pins of the
LP2995.
3. Two GND pads have been provided for ease of use. Either is sufficient for grounding of the board.
4. The VDDQ input provides the internal divide by two reference voltage. Both VREF and VTT will track this
internal voltage, nominally a 2.5V will be applied.
5. The VREFOUT pad is the output for the VREF from the LP2995 after being bypassed by a ceramic
capacitor. This can be connected either to a multimeter for confirmation or directly to the memory
controller and DIMMS.
6. The remaining two pads are for the force and sense leads of the VTT output. These should be
connected directly to the termination plane or a multimeter if interested in verification. The output will
be regulated where the VSENSE leads connect to the VTT leads permitting the connection to a
motherboard without suffering from large resistance drops.
2
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Performance
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4
Performance
The following series of scope plots shows the performance of the LP2995 evaluation board when it is
subjected to various load tests. On each of the six scope plots there are two traces. The upper trace is the
VTT output voltage that has been AC coupled with a scale of 20 mV per division. The lower trace is the
output current with a scale of 500 mA per division. All the load transients begin from an initial condition of
zero current and show magnitude. Please refer to the title to determine whether the current flow is into
(sinking) or out of (sourcing) the VTT pin. The time scale for all the plots is 2mS per division.
0.5A Load Transient (Sourcing)
1A Load Transient (Sourcing)
1.5A Load Transient (Sourcing)
0.5A Load Transient (Sinking)
1A Load Transient (Sinking)
1.5A Load Transient (Sinking)
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AN-1241 LP2995 Evaluation Board
3
Board Layout
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The LP2995 has been designed to accommodate several different capacitor options to allow the designer
to optimize the solution for the specific application. For most desktop systems large aluminum electrolytic
capacitors will be used for their low cost. However, in height limited situations such as laptops fewer high
performance capacitors might be implemented such as specialty polymers. The table below lists some of
the capacitors that can be used and a vendor that offers that product line.
Capacitor Series
5
Vendor
Vendor Phone Number
Oscon
Vishay
(207) 324-4140
SP
Panasonic
(714) 373-7857
MLCC
Taiyo Yuden
(800)-348-2496
Aluminum
Panasonic
(714) 373-7857
Board Layout
Figure 2. LLP Top Side
4
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Board Layout
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Figure 3. LLP Bottom Side
Figure 4. SO-8 Top Side
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AN-1241 LP2995 Evaluation Board
5
Board Layout
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Figure 5. SO-8 Bottom Side
6
AN-1241 LP2995 Evaluation Board
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Board Layout
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Information
SO-8 Board
Board Material
Size
Board Thickness
Layers
Copper Thickness
Plating
Thermal Vias
Thermal Vias Size
Board Thickness
LLP-16 Board
FR4
FR4
0.9 x 1.1 inches
0.9 x 1.1 inches
0.062 inch
0.062 inch
2
2
1 oz
1 oz
HASL
HASL
3
6
25 mil
10 mil
0.062 inch
0.062 inch
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AN-1241 LP2995 Evaluation Board
7
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