LP2997MRX

LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 LP2997 DDR-II Termination Regulator Check for Samples: LP2997 FEATURES DESCRIPTION • • • • • • • • The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. 1 2 Source and Sink Current Low Output Voltage Offset No External Resistors Required Linear Topology Suspend to Ram (STR) Functionality Low External Component Count Thermal Shutdown Available in SOIC-8, SO PowerPAD-8 Packages APPLICATIONS • • An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. DDR-II Termination Voltage SSTL-18 Termination Typical Application Circuit LP2997 VREF SD SD VREF = 0.9V + AVIN AV IN = 2.5V V SENSE V DDQ VTT PVIN VDDQ = 1.8V CIN + C REF GND V TT= 0.9V + C OUT Figure 1. Typical Application Circuit 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com Connection Diagram GND 1 8 VTT SD VSENSE 2 7 PVIN 3 6 VREF 4 5 AVIN VDDQ GND Figure 2. SO PowerPAD-8 Layout See Package Number DDA (R-PDSO-G8) GND 1 8 VTT SD VSENSE 2 7 PVIN 3 6 VREF 4 5 AVIN VDDQ Figure 3. SOIC-8 Layout See Package Number D0008A PIN DESCRIPTIONS SOIC-8 Pin or SO PowerPAD-8 Pin Name 1 GND 2 SD 3 VSENSE Function Ground Shutdown Feedback pin for regulating VTT. 4 VREF Buffered internal reference voltage of VDDQ/2 5 VDDQ Input for internal reference equal to VDDQ/2 6 AVIN Analog input pin 7 PVIN Power input pin 8 VTT Output voltage for connection to termination resistors EP Exposed pad thermal connection Connect to Ground These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) AVIN to GND −0.3V to +6V PVIN to GND -0.3V to AVIN VDDQ (3) −0.3V to +6V Storage Temp. Range −65°C to +150°C Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 260°C SOIC-8 Thermal Resistance (θJA) 151°C/W SO PowerPAD-8 Thermal Resistance (θJA) 43°C/W Minimum ESD Rating (4) (1) (2) (3) (4) 1kV Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is intended to be functional, but does not ensure specific performance limits. For specific specifications and test conditions see Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Operating Range Junction Temp. Range (1) 0°C to +125°C AVIN to GND (1) 2 2.2V to 5.5V At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at θJA = 151.2° C/W junction to ambient with no heat sink. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 Electrical Characteristics Specifications with standard typeface are for TJ = 25°C and limits in boldface type apply over the full Operating Temperature Range (TJ = 0°C to +125°C) (1). Unless otherwise specified, AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V. Symbol VREF Parameter VREF Voltage Conditions PVIN = VDDQ = 1.7V PVIN = VDDQ = 1.8V PVIN = VDDQ = 1.9V Min Typ Max Units 0.837 0.887 0.936 0.860 0.910 0.959 0.887 0.937 0.986 V ZVREF VREF Output Impedance IREF = -30 to +30 μA VTT VTT Output Voltage IOUT = 0A PVIN = VDDQ = 1.7V PVIN = VDDQ = 1.8V PVIN = VDDQ = 1.9V 0.822 0.874 0.923 0.856 0.908 0.957 0.887 0.939 0.988 IOUT = ±0.5A (2) PVIN = VDDQ = 1.7V PVIN = VDDQ = 1.8V PVIN = VDDQ = 1.9V 0.828 0.878 0.928 0.856 0.908 0.957 0.890 0.940 0.990 -25 -25 -25 0 0 0 25 25 25 mV 320 500 µA VosTT/VTT VTT Output Voltage Offset (VREF-VTT) IOUT = 0A IOUT = -0.5A IOUT = +0.5A IQ Quiescent Current (3) IOUT = 0A (3) ZVDDQ VDDQ Input Impedance ISD Quiescent Current in Shutdown (3) IQ_SD Shutdown Leakage Current SD = 0V VIH Minimum Shutdown High Level VIL Maximum Shutdown Low Level ISENSE VSENSE Input Current TSD Thermal Shutdown TSD_HYS Thermal Shutdown Hysteresis (1) (2) (3) (4) 2.5 kΩ 100 SD = 0V V kΩ 115 150 µA 2 5 µA 1.9 V 0.8 See (4) V 13 nA 165 Celsius 10 Celsius Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate Average Outgoing Quality Level (AOQL). VTT load regulation is tested by using a 10 ms current pulse and measuring VTT. Quiescent current defined as the current flow into AVIN. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 3 LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Iq vs AVIN 1050 350 900 300 750 250 600 IQ (uA) IQ (uA) Iq vs AVIN in SD 400 200 450 150 300 100 150 50 0 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 AVIN (V) AVIN (V) Figure 4. Figure 5. VIH and VIL 4.5 5 5.5 VREF vs VDDQ 4 3 3.5 2.5 3 VREF (V) VSD (V) 2 2.5 2 1.5 1 1.5 0.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 0 1 2 3 4 AVIN (V) VDDQ (V) Figure 6. Figure 7. VTT vs VDDQ 5 6 Iq vs AVIN in SD Temperature 400 3 350 2.5 0oC 300 IQ (uA) VTT (V) 2 1.5 125oC 250 200 1 150 0.5 100 0 50 0 4 1 2 3 4 5 6 2 2.5 3 3.5 4 VDDQ (V) AVIN (V) Figure 8. Figure 9. Submit Documentation Feedback 4.5 5 5.5 Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 1.8V) Iq vs AVIN Temperature 1.4 1050 85oC 1.2 IQ (uA) 750 OUTPUT CURRENT (A) 900 25oC 600 0oC 450 300 1 0.8 0.6 0.4 0.2 150 0 0 2 2.5 3 3.5 4 4.5 5 2 5.5 2.5 AVIN (V) 3 3.5 4 4.5 5 5.5 AVIN (V) Figure 10. Figure 11. Maximum Sinking Current vs AVIN (VDDQ = 1.8V) 2.4 OUTPUT CURRENT (A) 2.2 2 1.8 1.6 1.4 1.2 1 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) Figure 12. Block Diagram VDDQ SD AVIN PVIN 50k VREF + - 50k + VTT VSENSE GND Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 5 LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com DESCRIPTION The LP2997 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-18. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The LP2997 also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2997 to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII). Pin Descriptions AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2997. AVIN is used to supply all the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off separate supplies, under the condition that AVIN is always greater than or equal to PVIN. For SSTL-18 applications, it is recommended to connect PVIN to the 1.8V rail used for the memory core and AVIN to a rail within its operating range of 2.2V to 5.5V (typically a 2.5V supply). PVIN should always be used with either a 1.8V or 2.5V rail. This prevents the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active. A lower rail such as 1.5V can be used but it will reduce the maximum output current, therefore it is not recommended for most termination schemes. VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50kΩ resistors. This ensures that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 1.8V rail at the DIMM instead of PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-18 applications VDDQ will be a 1.8V signal, which will create a 0.9V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over temperature). VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2997 then the long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1uF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors. SHUTDOWN The LP2997 contains an active low shutdown pin that can be used for suspend to RAM functionality. In this condition the VTT output will tri-state while the VREF output remains active providing a constant reference signal for the memory and chipset. During shutdown VTT should not be exposed to voltages that exceed PVIN. With the shutdown pin asserted low the quiescent current of the LP2997 will drop, however, VDDQ will always maintain its constant impedance of 100kΩ for generating the internal reference. Therefore, to calculate the total power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. The shutdown pin also has an internal pull-up current; therefore, to turn the part on the shutdown pin can either be connected to AVIN or left open VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality. VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The LP2997 is designed to handle continuous currents of up to +/- 0.5A with excellent load regulation. If a transient is expected to last above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor should be sized large enough to prevent an excessive voltage drop. If the LP2997 is to operate in elevated temperatures for long durations care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal de-rating should always be used. (Please refer to the Thermal Dissipation section) If the junction temperature exceeds the thermal shutdown point than VTT will tri-state until the part returns below the temperature hysteresis trip-point COMPONENT SELECTIONS INPUT CAPACITOR The LP2997 does not require a capacitor for input stability, but it is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 22 µF. Ceramic capacitors can also be used. A value in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the LP2997 is placed close to the bulk capacitance from the output of the 1.8V DC-DC converter. For the AVIN pin, a small 0.1uF ceramic capacitor is sufficient to prevent excessive noise from coupling into the device. 6 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 OUTPUT CAPACITOR The LP2997 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of VTT. As a general recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these are highlighted below: AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (100 kHz) should be used for the LP2997. To improve the ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESR rapidly increase at cold temperatures. Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic capacitors. Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance are critical, although their cost is typically higher than any other capacitors. Thermal Dissipation Since the LP2997 is a linear regulator any current flow from VTT will result in internal power dissipation generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax). TRmax = TJmax − TAmax (1) From this equation, the maximum power dissipation (PDmax) of the part can be calculated: PDmax = TRmax / θJA (2) The θJA of the LP2997 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. For instance, the θJA of the SOIC-8 is 163°C/W with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value can be reduced to 151.2°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard. Figure 13 shows how the θJA varies with airflow for the two boards mentioned. 180 170 160 150 SOP Board TJA 140 130 120 110 JEDEC Board 100 90 80 0 200 400 600 800 1000 AIRFLOW (Linear Feet per Minute) Figure 13. θJA vs Airflow (SOIC-8) Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 7 LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help. With careful layout it is possible to reduce the θJA further than the nominal values shown in Figure 13. Optimizing the θJA and placing the LP2997 in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current at AVIN and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation can be calculated from the following equations: PD = PAVIN + PVDDQ + PVTT (3) Where, PAVIN = IAVIN * VAVIN PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ (4) (5) To calculate the maximum power dissipation at VTT both conditions at VTT need to be examined, sinking and sourcing current. Although only one equation will add into the total, VTT cannot source and sink current simultaneously. PVTT = VVTT x ILOAD (Sinking) or PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing) (6) (7) The power dissipation of the LP2997 can also be calculated during the shutdown state. During this condition the output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN and the constant impedance that is seen at the VDDQ pin. PD = PAVIN + PVDDQ PAVIN = IAVIN x VAVIN PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ (8) (9) (10) Typical Application Circuits Several different application circuits have been shown to illustrate some of the options that are possible in configuring the LP2997. Graphs of the individual circuit performance can be found in the Typical Performance Characteristics section in the beginning of the datasheet. These curves illustrate how the maximum output current is affected by changes in AVIN and PVIN. Figure 14 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 2.5V, 3.3V or 5V rail. This circuit permits termination in a minimum amount of board space and component count. Capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. However, with motherboards and other applications where VTT is distributed across a long plane it is advisable to use multiple bulk capacitors and addition to high frequency decoupling. The bulk output capacitors should be situated at both ends of the VTT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR and low cost. LP2997 VREF SD SD VREF = 0.9V + 0.01 PF AVIN AVIN = 2.5V VSENSE V DD Q VTT PVIN V DD = 1.8V Q + 7 PF GND VTT = 0.9V + 22 PF 0 Figure 14. Recommended DDR-II Termination 8 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 LP2997 www.ti.com SNVS295F – MAY 2004 – REVISED APRIL 2013 PCB Layout Considerations 1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin. 2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus. 3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. 4. For improved thermal performance excessive top side copper should be used to dissipate heat from the package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these can be located underneath the package if manufacturing standards permit. 5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A 0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency signal. This can be an issue especially if long SENSE traces are used. 6. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the VREF pin. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 9 LP2997 SNVS295F – MAY 2004 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision E (April 2013) to Revision F • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP2997 PACKAGE OPTION ADDENDUM www.ti.com 2-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LP2997M NRND SOIC D 8 95 Non-RoHS & Green Call TI Level-1-235C-UNLIM 0 to 125 L2997 M LP2997M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM 0 to 125 L2997 M LP2997MR NRND SO PowerPAD DDA 8 95 Non-RoHS & Green Call TI Level-3-260C-168 HR 0 to 125 L2997 MR LP2997MR/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green NIPDAU | SN Level-3-260C-168 HR 0 to 125 (L2997, LP2997) MR Samples LP2997MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | SN Level-3-260C-168 HR 0 to 125 (L2997, LP2997) MR Samples D 8 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 125 L2997 M Samples LP2997MX/NOPB ACTIVE SOIC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of