LP2998EVAL

User's Guide SNVA332A – March 2008 – Revised May 2013 AN-1813 LP2998 Evaluation Board The LP2998 evaluation board is designed to provide the design engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system. This application note contains information regarding the board, for more information please refer to the LP2998 DDR-I and DDR-II Termination Regulator (SNVS521) data sheet. 1 Schematic The following schematic was used to create the layout. LP2998 U1 SD VREF SD VDDQ VDDQ AVIN AVIN VSENSE PVIN VTT C6 0.1PF VREF C1 0.01PF GND VS + C4 330 PF + C3 Open VTT + C2 Open PVIN C5 22PF Figure 1. Schematic Used to Create Layout PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. SNVA332A – March 2008 – Revised May 2013 Submit Documentation Feedback AN-1813 LP2998 Evaluation Board Copyright © 2008–2013, Texas Instruments Incorporated 1 Application www.ti.com Table 1. Bill of Materials Name Value LP2998 DDR Linear Regulator U1 C6 2 Description Manufacturer Model Number National Semiconductor LP2998 or LP2998 MuRata GRM219R71C104KA01 0.1µF 0805 Ceramic Capacitor X7R 16V C4 330µF 6.3V ,D3L. POSCAP Sanyo 6TPE330MIL C1 0.01µF 0805 Ceramic Capacitor X7R 25V MuRata GRM216R71E103KA01 C5 22µF 0805 Ceramic Capacitor X5R 6.3V MuRata GRM21BR60J226ME39 C2, C3 Open Application The LP2998 evaluation board can be used immediately in either a static test environment to check functionality or in a memory termination scheme on a motherboard. In either implementation the following steps should be taken to ensure correct operation. 1. Connect AVIN and PVIN to a 2.5V power supply. The voltage on AVIN and PVIN can be separated provided the voltage on ether does not exceed 5.5V and is greater than the minimum operating voltage specificed in the datasheet. 2. The VDDQ input provides the internal divide by two reference voltage. Both VREF and VTT will track this internal voltage, nominally a 2.5V will be applied for DDR I and a 1.8V supply for DDR II applicaitons. 3. The VREF pin is the output for the VREF from the LP2998 after being bypassed by a ceramic capacitor. This can be connected either to a multimeter for confirmation or directly to the memory controller and DIMMS. 4. The SD pin can be initially left floating as it has an internal pull-up 5. The remaining two pins are for the force and sense leads of the VTT output. These should be connected directly to the termination plane or a multimeter if interested in verification. The output will be regulated where the VS lead connects to VTT. Remote sensing with VS permits a connection to a motherboard without suffering from large resistance drops. 3 Performance The LP2998 has been designed to accommodate several different capacitor options to allow the designer to optimize the solution for the specific application. For most desktop systems large aluminum electrolytic capacitors will be used for their low cost. However, in height limited situations such as laptops fewer high performance capacitors might be implemented such as specialty polymers. The table below lists some of the capacitors that can be used and a vendor that offers that product line. Capacitor Series Oscon SP MLCC 2 Vendor Vendor Phone Number Vishay (207)-324-4140 Panasonic (714)-373-7857 Taiyo Yuden (800)-348-2496 Aluminum Panasonic (714)-373-7857 POSCAP Sanyo (619)-661-6835 AN-1813 LP2998 Evaluation Board SNVA332A – March 2008 – Revised May 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Performance www.ti.com Figure 2. SO PowerPAD™ Top Layer Figure 3. SO PowerPAD Bottom Layer Information Board Material FR4 Size 1.0 x 1.5 inches Board Thickness 0.062 inch Layers 2 Copper Thickness 1oz. Plating Immersion Gold Thermal Vias 4 Thermal Vias Size 12 mil Board Thickness 0.062 inch SNVA332A – March 2008 – Revised May 2013 Submit Documentation Feedback AN-1813 LP2998 Evaluation Board Copyright © 2008–2013, Texas Instruments Incorporated 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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