LP38511TS-1.8/NOPB

LP38511 www.ti.com SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 LP38511-1.8 800 mA Fast-Transient Response Low-Dropout Linear Voltage Regulator with Error Flag Check for Samples: LP38511 FEATURES DESCRIPTION • • • • The LP38511-1.8 Fast-Transient Response LowDropout Voltage Regulator offers the highestperformance in meeting AC and DC accuracy requirements for powering Digital Cores. The LP38511-1.8 uses a proprietary control loop that enables extremely fast response to change in line conditions and load demands. Output Voltage DC accuracy is specified at ±2.5% over line, load and full temperature range from -40°C to +125°C. The LP38511-1.8 is designed for inputs from the 2.5V, 3.3V, and 5.0V rail, is stable with 10uF ceramic capacitors, and has a fixed 1.8V output. An Error Flag feature monitors the output voltage and notifies the system processor when the output voltage falls more than 15% below the nominal value. The LP38511-1.8 provides excellent transient performance to meet the demand of high performance digital core ASICs, DSPs, and FPGAs found in highly-intensive applications such as servers, routers/switches, and base stations. 1 2 • • • • • • • • 2.25V to 5.5V Input Voltage Range 1.8V Fixed Output Voltage 800 mA Output Load Current +/- 2.5% VOUT Accuracy over Line, Load, and Full-Temperature Range from -40°C to +125°C Stable with tiny 10 µF Ceramic Capacitors 0.20% Output Voltage Load Regulation from 10 mA to 800 mA Enable pin Error Flag Indicates Status of Output Voltage 1 µA of Quiescent Current in Shutdown 40dB of PSRR at 100 kHz Over-Temperature and Over-Current Protection DDPAK/TO-263 and PFM Surface Mount Packages APPLICATIONS • • • • • • Digital Core ASICs, FPGAs, and DSPs Servers Routers and Switches Base Stations Storage Area Networks DDR2 Memory Typical Application Circuit IN VIN ON OFF VEN CIN 10 PF Ceramic OUT LP38511 EN ERROR COUT 10 PF Ceramic VOUT 10 k: GND GND GND VERROR 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LP38511 SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com Connection Diagrams IN 2 GND 3 OUT 4 ERROR 5 TAB IS GND EN 1 IN 2 GND 3 OUT 4 ERROR 5 Figure 1. Top View DDPAK/TO-263 5 Pin Package LP38511TJ-1.8 LP38511TS-1.8 EN 1 Exposed DAP Figure 2. Top View PFM 5 Pin Package PIN DESCRIPTIONS FOR DDPAK/TO-263 AND PFM PACKAGES Pin # Pin Name Function 1 EN Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and must be tied to the input voltage, or actively driven. 2 IN Input Supply Pin 3 GND Ground 4 OUT Regulated Output Voltage Pin 5 ERROR TAB/DAP TAB/DAP ERROR Flag. A high level indicates that VOUT is within 15% (VOUT falling) of the nominal regulated voltage. The DDPAK/TO-263 TAB, and the PFM DAP, is used as a thermal connection to remove heat from the device to an external heatsink. The TAB/DAP is internally connected to device pin 3, and is electrical ground connection. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) −65°C to +150°C Storage Temperature Range Peak Reflow Temperature (3) DDPAK/TO-263 ESD Rating (4) 260°C, 30s ±2 kV Power Dissipation (5) Internally Limited Input Pin Voltage (Survival) −0.3V to +6.0V Enable Pin Voltage (Survival) −0.3V to +6.0V Output Pin Voltage (Survival) −0.3V to +6.0V ERROR Pin Voltage (Survival) 0.3V to +6.0V IOUT(Survival) (1) (2) (3) (4) (5) Internally Limited Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Refer to JEDEC J-STD-020C for surface mount device (SMD) package reflow profiles and conditions. Unless otherwise stated, the temperatures and times are for Sn-Pb (STD) only. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method is per JESD22-A114. Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). OPERATING RATINGS (1) Input Supply Voltage, VIN 2.25V to 5.5V Enable Input Voltage, VEN 0.0V to 5.5V ERROR Pin Voltage 0.0V to VIN Output Current (DC) 0 mA to 800 mA (1) 2 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions, see the Electrical Characteristics. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 LP38511 www.ti.com SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 OPERATING RATINGS(1) (continued) Junction Temperature (2) (2) −40°C to +125°C Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). ELECTRICAL CHARACTERISTICS Unless otherwise specified: VIN = 2.5V, IOUT = 10 mA, CIN = 10 µF, COUT = 10 µF, VEN = VIN. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions Min Typ Max Units -1.0 −2.5 0 +1.0 +2.5 % Output Voltage Tolerance (1) 2.25V ≤ VIN ≤ 5.5V 10 mA ≤ IOUT ≤ 800 mA ΔVOUT/ΔVIN Output Voltage Line Regulation (1) (2) 2.25V ≤ VIN ≤ 5.5V - 0.02 0.06 - %/V ΔVOUT/ΔIOUT Output Voltage Load Regulation (1) (3) 10 mA ≤ IOUT ≤ 800 mA - 0.25 0.40 - %/A Dropout Voltage (4) IOUT = 800 mA - 135 225 260 mV - 7.5 11 12 - 9.5 13 14 - 0.1 3.5 12 µA - 1.5 - A VOUT VDO IOUT = 10 mA Ground Pin Current, Output Enabled IGND ERROR pin = GND IOUT = 800 mA ERROR pin = GND mA Ground Pin Current, Output Disabled VEN = 0.50V Short Circuit Current VOUT = 0V VEN(ON) Enable ON Threshold VEN rising from 0.50V until VOUT = ON 0.90 0.80 1.20 1.50 1.60 V VEN(OFF) Enable OFF Threshold VEN falling from 1.60V until VOUT = OFF 0.60 0.50 1.00 1.40 1.50 V VEN(HYS) Enable Hysteresis VEN(ON) - VEN(OFF) - 200 - mV td(OFF) Turn-off delay Time from VEN < VEN(OFF) to VOUT = OFF, ILOAD = 1.5A - 1 - td(ON) Turn-on delay Time from VEN >VEN(ON) to VOUT = ON, ILOAD = 800 mA - 25 - VEN = VIN - 1 - VEN = 0V - -1 - VOUT rising threshold where ERROR Flag goes high 78 90 98 VOUT falling threshold where ERROR Flag goes low 74 85 93 ERROR Flag Saturation Voltage ISINK = 1 mA - 12.5 45 mV Ilk ERROR Flag Pin Leakage Current - 1 - nA td ERROR Flag Delay time - 1 - µs ISC ERROR pin = GND Enable Input IEN Enable Pin Current µs nA ERROR Flag VTH VERROR(SAT) (1) (2) (3) (4) (5) Error Flag Threshold (5) VERROR = 5.5V % The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Output voltage line regulation is defined as the change in output voltage from the nominal value (ΔVOUT) due to a change in the voltage at the input (ΔVIN). Output voltage load regulation is defined as the change in output voltage from the nominal value (ΔVOUT) due to a change in the load current at the output (ΔIOUT). Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. For the LP38511-1.8, the minimum VIN operating voltage is the limiting factor. The ERROR Flag thresholds are specified as percentage of the nominal regulated output voltage. See APPLICATION INFORMATION. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 3 LP38511 SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified: VIN = 2.5V, IOUT = 10 mA, CIN = 10 µF, COUT = 10 µF, VEN = VIN. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions Min Typ Max Units VIN = 2.5V f = 120Hz - 73 - VIN = 2.5V f = 1 kHz - 73 - Output Noise Density f = 120Hz - 2 - nV/√Hz Output Noise Voltage BW = 100Hz – 100kHz - 75 - µV (rms) Thermal Shutdown TJ rising - 165 - Thermal Shutdown Hysteresis TJ falling from TSD - 10 - Thermal Resistance Junction to Ambient (6) DDPAK/TO-263 and PFM - 60 - SO PowerPAD-8 - 168 - Thermal Resistance Junction to Case DDPAK/TO-263 and PFM - 3 - SO PowerPAD-8 - 11 - AC Parameters PSRR en Ripple Rejection dB Thermal Characteristics TSD ΔTSD θJA θJC (6) 4 °C °C/W °C/W Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 LP38511 www.ti.com SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. VOUT vs Temperature VOUT vs VIN Figure 3. Figure 4. Ground Pin Current (IGND) vs VIN Ground Pin Current (IGND) vs Temperature Figure 5. Figure 6. Ground Pin Current(IGND) vs Temperature, VEN = 0.5V Enable Thresholds vs Temperature Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 5 LP38511 SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. 6 VOUT vs VEN (td(ON)) VOUT vs VEN (td(OFF)) Figure 9. Figure 10. VOUTERROR Flag Threshold vs Temperature ERROR Flag Low vs Temperature Figure 11. Figure 12. Load regulation vs Temperature Line Regulation vs Temperature Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 LP38511 www.ti.com SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. Current Limit vs Temperature Load Transient, 10 mA to 800 mA COUT = 10 μF Ceramic Figure 15. Figure 16. Load Transient, 10 mA to 800 mA COUT = 10 µF Ceramic + 100 µF Aluminum Load Transient, 250 mA to 800 mA COUT = 10 µF Ceramic Figure 17. Figure 18. Load Transient, 250 mA to 800 mA COUT = 10 μF Ceramic + 100 μF Aluminum Line Transient Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 7 LP38511 SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. 8 PSRR, 10Hz to 1MHz Noise Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 LP38511 www.ti.com SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 BLOCK DIAGRAM IN OUT Thermal Limit Current Limit EN VREF ERROR VREF GND LP38511 APPLICATION INFORMATION EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. Input Capacitor A ceramic input capacitor of at least 10 µF is required. For general usage across all load currents and operating conditions, a 10 µF ceramic input capacitor will provide satisfactory performance. Output Capacitor A ceramic capacitor with a minimum value of 10 µF is required at the output pin for loop stability. It must be located less than 1 cm from the device and connected directly to the output and ground pin using traces which have no other currents flowing through them. As long as the minimum of 10 µF ceramic is met, there is no limitation on any additional capacitance. X7R and X5R dielectric ceramic capacitors are strongly recommended, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. Z5U and Y5V dielectric ceramics are not recommended as the capacitance will drops severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is connected to the output. There are two possible paths for current to flow from the output pin back to the input during a reverse voltage condition. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 9 LP38511 SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com While VIN is high enough to keep the control circuity alive, and the Enable pin is above the VEN(ON) threshold, the control circuitry will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full on condition when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous reverse current should be avoided. The internal PFET pass element in the LP38511 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output voltage to input voltage differential is more than 500 mV (typical) the parasitic diode becomes forward biased and current flows from the output pin to the input through the diode. The current in the parasitic diode should limited to less than 1A continuous and 5A peak. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommended for this protective clamp. SHORT-CIRCUIT PROTECTION The LP38511 is short circuit protected, and in the event of a peak over-current condition the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the POWER DISSIPATION/HEATSINKING section for power dissipation calculations. ENABLE OPERATION The Enable ON threshold is typically 1.2V, and the OFF threshold is typically 1.0V. To ensure reliable operation the Enable pin voltage must rise above the maximum VEN(ON) threshold and must fall below the minimum VEN(OFF) threshold. The Enable threshold has typically 200mV of hysteresis to improve noise immunity. The Enable pin (EN) has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the Enable pin is driven from a single ended device (such as discrete transistor) a pull-up resistor to VIN, or a pull-down resistor to ground, will be required for proper operation. A 1 kΩ to 100 kΩ resistor can be used as the pull-up or pull-down resistor to establish default condition for the EN pin. The resistor value selected should be appropriate to swamp out any leakage in the external single ended device, as well as any stray capacitance. If the Enable pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator output), the pull-up, or pull-down, resistor is not required. If the application does not require the Enable function, the pin should be connected to directly to the adjacent VIN pin. The status of the Enable pin also affects the behavior of the ERROR Flag. While the Enable pin is high the regulator control loop will be active and the ERROR Flag will report the status of the output voltage. When the Enable pin is taken low the regulator control loop is shutdown, the output is turned off, and the ERROR Flag pin is immediately forced low. ERROR FLAG OPERATION When the LP38511 Enable pin is high, the ERROR Flag pin will produce a logic low signal when the output drops by more than 15% from the nominal output voltage. The drop in output voltage may be due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The output voltage will typically need to rise to within 10% (typical) of the nominal output voltage for the ERROR Flag to return to a logic high state. It should also be noted that when the Enable pin is pulled low, the ERROR Flag pin is forced to be low as well. The internal ERROR flag comparator has an open drain output stage. Hence, the ERROR pin requires an external pull-up resistor. The value of the pull-up resistor should be in the range of 10 kΩ to 1 MΩ. The ERROR Flag pin should not be pulled-up to any voltage source higher than VIN as current flow through an internal parasitic diode may cause unexpected behavior. The ERROR Flag must be connected to ground if this function is not used. 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 LP38511 www.ti.com SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 The timing diagram in Figure 23 shows the relationship between the ERROR flag and the output voltage. ~2.50V ~2.25V VIN ~1.55V ~1.25V Power-Up NOM ~90% ~85% Load Transient Line Transient Power-Down VOUT 1.80V VERROR Figure 23. ERROR Flag Operation, see Typical Application Circuit ~2.50V ~2.25V VIN ~1.55V ~1.25V Power-Up NOM ~90% ~85% Load Transient Line Transient Power-Down VOUT ~2.50V VERROR ~1.25V Figure 24. ERROR Flag Operation, biased from VIN POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation (PD(MAX)), maximum ambient temperature (TA(MAX)) of the application, and the thermal resistance (θJA) of the package. Under all possible conditions, the junction temperature (TJ) must be within the range specified in the Operating Ratings. The total power dissipation of the device is given by: PD = ( (VIN−VOUT) x IOUT) + (VIN x IGND) where • IGND is the operating ground current of the device (specified under ELECTRICAL CHARACTERISTICS). (1) The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambient temperature (TA(MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)): ΔTJ = TJ(MAX)− TA(MAX) (2) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = ΔTJ / PD(MAX) (3) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 11 LP38511 SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 www.ti.com HEATSINKING DDPAK/TO-263 PACKAGE The DDPAK/TO-263 and the PFM packages use the copper plane on the PCB as a heatsink. The tab, or DAP, of these packages are soldered to the copper plane for heat sinking. Figure 25 shows a curve for the θJA of DDPAK/TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. Figure 25. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 package As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK/TO-263 package mounted to a two-layer PCB is 32°C/W. Figure 26 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Figure 26. Maximum Power Dissipation vs Ambient Temperature for DDPAK/TO-263 Package 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 LP38511 www.ti.com SNOSAU6E – NOVEMBER 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38511 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LP38511TJ-1.8/NOPB ACTIVE TO-263 NDQ 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L38511TJ -1.8 LP38511TS-1.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP38511 TS-1.8 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of