LP38512TJ-ADJEV

User's Guide SNVA331B – January 2009 – Revised April 2013 AN-1802 LP38512TJ-ADJ Evaluation Board 1 Introduction This board is designed to allow the evaluation of the LP38512TJ-ADJ voltage regulator. Each board is assembled and tested in the factory. This evaluation board has the TO-263 THIN 5-lead package mounted, and the output voltage is set to 1.20 V. 2 General Description The LP38512TJ-ADJ is an adjustable LDO linear regulator capable of suppling up to 1.5A of output current, and incorporates an Enable. The device has been designed to work with 10 µF input and output ceramic capacitors. Footprints areas for CIN and COUT will allow for a variety of sizes. 3 Operation The input voltage, applied between VIN and GND, must be no less than 2.25 V, which is the low end of the operating range voltage, no greater than 5.5 V, which is the high end of the operating range voltage. The input voltage should also be at least 500 mV greater than the set VOUT. Loads can be connected to VOUT with reference to GND. VOUT and VIN test points are provided on the board to allow accurate measurements directly onto the input and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the load. 4 Setting VOUT The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the formula: VOUT = VADJ x (1 + (R1 / R2) ) (1) It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 1.00 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and CFF. ( (R1 x R2) / (R1 + R2) ) ≤ 1.00 kΩ (2) Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give similar results. All trademarks are the property of their respective owners. SNVA331B – January 2009 – Revised April 2013 Submit Documentation Feedback AN-1802 LP38512TJ-ADJ Evaluation Board Copyright © 2009–2013, Texas Instruments Incorporated 1 Selecting CFF www.ti.com Table 1. Suggested Components VOUT R1 R2 CFF FZ 0.80 V 1.07 kΩ 1.78 kΩ 4700 pF 31.6 kHz 1.00 V 1.00 kΩ 1.00 kΩ 4700 pF 33.8 kHz 1.20 V 1.40 kΩ 1.00 kΩ 3300 pF 34.4 kHz 1.50 V 2.00 kΩ 1.00 kΩ 2700 pF 29.5 kHz 1.80 V 2.94 kΩ 1.13 kΩ 1500 pF 36.1 kHz 2.00 V 1.02 kΩ 340Ω 4700 pF 33.2 kHz 2.50 V 1.02 kΩ 255Ω 4700 pF 33.2 kHz 3.00 V 1.00 kΩ 200Ω 4700 pF 33.8 kHz 3.30 V 2.00 kΩ 357Ω 2700 pF 29.5 kHz For additional information on how resistor tolerances affect the calculated VOUT value, see AN-1378 Method for Calculating Output Voltage Tolerances in Adjustable Regulators (SNVA112). The LP38512TJ-ADJ evaluation board is assembled with a 1.40 kΩ ±1% resistor for R1, and a 1.00 kΩ ±1% resistor for R2. This sets VOUT to 1.20 V. VOUT = 500 mV x (1 + (1.40 kΩ / 1.00 kΩ) ) = 1.20 V 5 (3) Selecting CFF A capacitor placed across the gain resistor R1 provides additional phase margin to improve load transient response of the device. This capacitor, CFF, in parallel with R1, forms a zero in the loop response given by the formula in Equation 4: FZ = (1 / (2 x π x CFF x R1) ) (4) The value for CFF should be selected to set a zero frequency (FZ) between 25 kHz and 50 kHz using the formula in Equation 5: CFF = 1 / (2 x π x FZ x R1) (5) The closest standard 10% value is adequate for CFF. The LP38512TJ-ADJ Evaluation board is assembled with a 3300 pF capacitor for CFF. This sets FZ to approximately 34 kHz. FZ = (1 / (2 x π x 3300 pF x 1.40 kΩ ) ) = 34.4 kHz 2 AN-1802 LP38512TJ-ADJ Evaluation Board (6) SNVA331B – January 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Selecting CFF www.ti.com Figure 1. 10 mA to 1.5A Load Transient Response Figure 2. 500 mA to 1.5A Load Transient Response SNVA331B – January 2009 – Revised April 2013 Submit Documentation Feedback AN-1802 LP38512TJ-ADJ Evaluation Board Copyright © 2009–2013, Texas Instruments Incorporated 3 Enable Function 6 www.ti.com Enable Function ON/OFF control is provided by supplying a logic level signal to the Enable pin. A minimum VEN value of 1.2 V is typically required at this pin to enable the LDO output. The LDO output will be shutdown when the VEN value is typically 0.6 V or less. The VEN threshold incorporates approximately 100 mV of hysteresis. Figure 3. VOUT vs VEN The Enable pin has no internal default bias and must not be left floating. The Enable pin must be actively driven to the appropriate voltage level. In applications where the LP38513TJ is operated continuously, the Enable pin can be connected directly to VIN. The LP38512TJ-ADJ evaluation board is assembled with a 10 kΩ resistor (R3) to provide pull-up to VIN. Figure 4. Enable Thresholds 7 Power Dissipation The TO-263 THIN package alone has a junction to ambient thermal resistance (θJA) rating of 67°C/W. When mounted on the LP38512TJ-ADJ evaluation board, the θJA rating is approximately 35°C/W. Although there is only approximately 0.20 square inches (0.45in x 0.45in) of 1 ounce copper area immediately under the package body, the top copper surface area is extended to additional copper area on the bottom of the board by fifteen thermal vias. 4 AN-1802 LP38512TJ-ADJ Evaluation Board SNVA331B – January 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Power Dissipation www.ti.com With the 35°C/W thermal rating, the LP38512TJ-ADJ evaluation board dissipates a maximum of 2.8W with TA = 25°C. For a comparison of the TO-263 THIN package to the standard TO-263 package, see AN-1797 TO-263 THIN Package (SNVA328). Figure 5. Maximum Power Dissipation vs Ambient Temperature 7.1 Connection Diagram LP38512TJ-ADJ EN 1 IN 2 GND 3 OUT 4 ADJ 5 7.2 Exposed DAP Schematic Diagram TP1 TP2 TP3 TP4 LP38512TJ-ADJ 1.20V VIN (J2) IN (2) (4) OUT VOUT (J4) C1 10 PF R3 10 k: R1 1.40 k: EN (1) VEN (J1) GND (3) (5) ADJ DAP C3 3300 pF C2 10 PF R2 1.00 k: GND (J3) Figure 6. Evaluation Board Schematic. SNVA331B – January 2009 – Revised April 2013 Submit Documentation Feedback AN-1802 LP38512TJ-ADJ Evaluation Board Copyright © 2009–2013, Texas Instruments Incorporated 5 PCB Layout 8 www.ti.com PCB Layout 980600064-100 RevA LP38512TJ-ADJ ENABLE VEN U1 R2 1.00 k: LP38512 TJ-ADJ J1 R1 1.40 k: R2 TP1 R3 10 k: R3 TP2 VIN CFF (C3) 3300 pF R1 C3 C2 TP4 C1 J4 J2 VOUT GND VIN VOUT TP3 J3 CIN (C1) 10 PF COUT (C2) 10 PF GND Figure 7. Evaluation Board Component and Pin Layout 1940 mil 1604 mil Figure 8. Top Side Copper Area 6 AN-1802 LP38512TJ-ADJ Evaluation Board SNVA331B – January 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated PCB Layout www.ti.com 1940 mil 1604 mil Figure 9. Bottom Side Copper Area Table 2. Bill of Materials ID Name Description Manufacturer Part Number PCB PCB Printed Circuit Board LP38512TJ-ADJ Evaluation Board Texas Instruments 600064 U1 U1 LP38512 Texas Instruments LP38512 CIN Capacitor: 10 µF; ±10%; MLCC; 10 V; X7R; 1210 C1 C2 COUT Capacitor: 10 µF;, ±10%; MLCC; 10 V; X7R; 1210 C3 CFF Capacitor: 3300 pF;, ±10%; MLCC; 50 V; X7R; 0805 J1 VEN Banana Jack : Insulated Solder Terminal; White J2 VIN Banana Jack : Insulated Solder Terminal; Red 1210ZC106KAT2A AVX 1210ZC106KAT2A KEMET C0805C332K5RAC 108-0901-001 108-0902-001 Johnson Components J3 GND Banana Jack : Insulated Solder Terminal; Black J4 VOUT Banana Jack : Insulated Solder Terminal; Orange 108-0906-001 R1 R1 Resistor: 1.40 kΩ, ±1%; Thick Film; 125 mW; ±100 ppm; 0805 CRCW08051K40FK R2 R2 Resistor: 1.00 kΩ, ±1%; Thick Film; 125 mW; ±100 ppm; 0805 R3 R3 Resistor: 10.0 kΩ, ±1%; Thick Film; 125 mW; ±100 ppm; 0805 TP1 TPEN TP2 TPIN TP3 TPGND TP4 TPOUT Turret Terminal : Mounting Hole Diameter = 0.062” SNVA331B – January 2009 – Revised April 2013 Submit Documentation Feedback 108-0903-001 VISHAY DALE CRCW08051K00FK CRCW080510K0FK Keystone 1593–2 AN-1802 LP38512TJ-ADJ Evaluation Board Copyright © 2009–2013, Texas Instruments Incorporated 7 PCB Layout 8 www.ti.com AN-1802 LP38512TJ-ADJ Evaluation Board SNVA331B – January 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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