User's Guide
SNVA264B – January 2009 – Revised April 2013
AN-1670 LP38513TJ-ADJ Evaluation Board
1
Introduction
This board is designed to allow the evaluation of the LP38513TJ-ADJ voltage regulator. Each board is
assembled and tested in the factory. This evaluation board has the TO-263 THIN 5-lead package
mounted, and the output voltage is set to 1.20V.
2
General Description
The LP38513TJ-ADJ is an adjustable LDO linear regulator capable of suppling up to 3A of output current,
and incorporates an Enable. The device has been designed to work with 10 µF input and output ceramic
capacitors. Footprints areas for CIN and COUT will allow for a variety of sizes.
3
Operation
The input voltage, applied between VIN and GND, must be no less than 2.25V, which is the low end of the
Operating Range voltage, no greater than 5.5V, which is the high end of the Operating Rating voltage.
The input voltage should also be at least 500 mV greater than the set VOUT.
Loads can be connected to VOUT with reference to GND.
VOUT and VIN test points are provided on the board to allow accurate measurements directly onto the input
and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the
load.
4
Setting VOUT
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
VOUT = VADJ x (1 + (R1 / R2))
(1)
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 1.00
kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set
by R1 and CFF.
( (R1 x R2) / (R1 + R2) ) ≤ 1.00 kΩ
(2)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will
give similar results.
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SNVA264B – January 2009 – Revised April 2013
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1
Selecting CFF
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Table 1. Resistor Tolerances
VOUT
R1
R2
CFF
FZ
0.80V
1.07 kΩ
1.78 kΩ
4700 pF
31.6 kHz
1.00V
1.00 kΩ
1.00 kΩ
4700 pF
33.8 kHz
1.20V
1.40 kΩ
1.00 kΩ
3300 pF
34.4 kHz
1.50V
2.00 kΩ
1.00 kΩ
2700 pF
29.5 kHz
1.80V
2.94 kΩ
1.13 kΩ
1500 pF
36.1 kHz
2.00V
1.02 kΩ
340Ω
4700 pF
33.2 kHz
2.50V
1.02 kΩ
255Ω
4700 pF
33.2 kHz
3.00V
1.00 kΩ
200Ω
4700 pF
33.8 kHz
3.30V
2.00 kΩ
357Ω
2700 pF
29.5 kHz
Refer to AN-1378 Method For Calculating Output Voltage Tolerances in Adjustable Regulators (SNVA112)
for additional information on how resistor tolerances affect the calculated VOUT value.
The LP38513TJ-ADJ evaluation board is assembled with a 1.40 kΩ ±1% resistor for R1, and a 1.00 kΩ
±1% resistor for R2. This sets VOUT to 1.20V.
VOUT = 500 mV x (1 + (1.40 kΩ / 1.00 kΩ)) = 1.20V
5
(3)
Selecting CFF
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load
transient response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop
response given by the formula:
FZ = (1 / (2 x π x CFF x R1) )
(4)
The value for CFF should be selected to set a zero frequency (FZ) between 25 kHz and 50 kHz using the
formula:
CFF = 1 / (2 x π x FZ x R1)
(5)
The closest standard 10% value is adequate for CFF.
The LP38513TJ-ADJ evaluation board is assembled with a 3300 pF capacitor for CFF. This sets FZ to
approximately 34 kHz.
FZ = (1 / (2 x π x 3300 pF x 1.40 kΩ ) ) = 34.4 kHz
2
AN-1670 LP38513TJ-ADJ Evaluation Board
(6)
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Enable Function
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Figure 1. 10 mA to 3A Load Transient Response
Figure 2. 1A to 3A Load Transient Response
6
Enable Function
ON/OFF control is provided by supplying a logic level signal to the Enable pin. A minimum VEN value of
1.2V is typically required at this pin to enable the LDO output. The LDO output will be shutdown when the
VEN value is typically 0.6V or less. The VEN threshold incorporates approximately 100 mV of hysteresis.
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3
Power Dissipation
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Figure 3. VOUT vs VEN
The Enable pin has no internal default bias and must not be left floating. The Enable pin must be actively
driven to the appropriate voltage level. In applications where the LP38513TJ is operated continuously the
Enable pin can be connected directly to VIN. The LP38513TJ-ADJ Evaluation board is assembled with a
10 kΩ resistor (R3) to provide pull-up to VIN.
Figure 4. Enable Thresholds
7
Power Dissipation
The TO-263 THIN package alone has a junction to ambient thermal resistance (θJA) rating of 67°C/W.
When mounted on the LP38513TJ-ADJ Evaluation Board the θJA rating is approximately 35°C/W.
Although there is only approximately 0.20 square inches (0.45in x 0.45in) of 1 ounce copper area
immediately under the package body, the top copper surface area is extended to additional copper area
on the bottom of the board by fifteen thermal vias.
With the 35°C/W thermal rating the LP38513TJ-ADJ evaluation board will dissipate a maximum of 2.8W
with TA = 25°C.
For a comparison of the TO-263 THIN package to the standard TO-263 package see AN-1797 TO-263
THIN Package (SNVA328).
4
AN-1670 LP38513TJ-ADJ Evaluation Board
SNVA264B – January 2009 – Revised April 2013
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Power Dissipation
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Figure 5. Maximum Power Dissipation vs Ambient Temperature
LP38513TJ-ADJ
EN 1
IN 2
GND 3
OUT 4
ADJ 5
7.1
Exposed
DAP
Schematic Diagram
TP1 TP2 TP3
TP4
LP38513TJ-ADJ
1.20V
IN (2)
VIN (J2)
(4) OUT
VOUT (J4)
C1
10 PF
R3
10 k:
R1
1.40 k:
EN (1)
VEN (J1)
GND (3)
(5) ADJ
DAP
C3
3300 pF
C2
10 PF
R2
1.00 k:
GND (J3)
Figure 6. Evaluation Board Schematic.
SNVA264B – January 2009 – Revised April 2013
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5
PCB Layout
8
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PCB Layout
980600065-100 RevA
LP38513TJ-ADJ
ENABLE
VEN
U1
R2
1.00 k
LP38513
TJ-ADJ
J1
R1
1.40 k
R2
TP1
R3
10 k
x
x
x
x
R3
CFF (C3)
3300 pF
TP2
VIN
x
R1 C3
C2 TP4
C1
J4
J2
VOUT
GND
VIN
VOUT
TP3
J3
CIN (C1)
10 F
COUT (C2)
10 F
GND
Figure 7. Evaluation Board Component and Pin Layout
1940 mil
1604 mil
Figure 8. Top Side Copper Area
6
AN-1670 LP38513TJ-ADJ Evaluation Board
SNVA264B – January 2009 – Revised April 2013
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Bill of Materials
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1940 mil
1604 mil
Figure 9. Bottom Side Copper Area
9
Bill of Materials
ID
Name
Description
Manufacturer
Part Number
PCB
PCB
Printed Circuit Board LP38513TJ-ADJ
Evaluation Board
Texas Instruments
600065
U1
U1
LP38513
Texas Instruments
LP38513
CIN
Capacitor: 10 µF; ±10%; MLCC; 10V;
X7R; 1210
C1
C2
COUT
Capacitor: 10 µF;, ±10%; MLCC; 10V;
X7R; 1210
C3
CFF
Capacitor: 3300 pF;, ±10%; MLCC;
50V; X7R; 0805
J1
VEN
Banana Jack : Insulated Solder
Terminal; White
J2
VIN
Banana Jack : Insulated Solder
Terminal; Red
1210ZC106KAT2A
AVX
1210ZC106KAT2A
KEMET
C0805C332K5RAC
108-0901-001
108-0902-001
Johnson Components
J3
GND
Banana Jack : Insulated Solder
Terminal; Black
J4
VOUT
Banana Jack : Insulated Solder
Terminal; Orange
108-0906-001
R1
R1
Resistor: 1.40 kΩ, ±1%; Thick Film;
125 mW; ±100 ppm; 0805
CRCW08051K40FK
R2
R2
Resistor: 1.00 kΩ, ±1%; Thick Film;
125 mW; ±100 ppm; 0805
R3
R3
Resistor: 10.0 kΩ, ±1%; Thick Film;
125 mW; ±100 ppm; 0805
TP1
TPEN
TP2
TPIN
TP3
TPGND
TP4
TPOUT
Turret Terminal : Mounting Hole
Diameter = 0.062”
SNVA264B – January 2009 – Revised April 2013
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108-0903-001
VISHAY DALE
CRCW08051K00FK
CRCW080510K0FK
Keystone
1593–2
AN-1670 LP38513TJ-ADJ Evaluation Board
Copyright © 2009–2013, Texas Instruments Incorporated
7
Bill of Materials
8
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AN-1670 LP38513TJ-ADJ Evaluation Board
SNVA264B – January 2009 – Revised April 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
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