LP38841SX-0.8/NOPB

LP38841 www.ti.com SNVS289C – DECEMBER 2004 – REVISED APRIL 2013 LP38841 0.8A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors Check for Samples: LP38841 FEATURES DESCRIPTION • • The LP38841 is a high current, fast response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 2 • • • • • • • • Ideal for Conversion from 1.8V or 1.5V Inputs Designed for Use with low ESR Ceramic Capacitors 0.8V, 1.2V and 1.5V Standard Voltages Available Ultra Low Dropout Voltage (75mV at 0.8A typ) 1.5% Initial Output Accuracy Load Regulation of 0.1%/A (typical) 30nA Quiescent Current in Shutdown (typical) Low Ground Pin Current at all Loads Over Temperature/over Current Protection Available in 5 Lead TO-220 and DDPAK/TO-263 Packages −40°C to +125°C Junction Temperature Range APPLICATIONS The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in TO-220 and DDPAK/TO-263 packages. • Dropout Voltage: 75 mV (typ) at 0.8A load current. • • • • ASIC Power Supplies In: – Desktops, Notebooks, and Graphics Cards, Servers – Gaming Set Top Boxes, Printers and Copiers Server Core and I/O Supplies DSP and FPGA Power Supplies SMPS Post-Regulator Quiescent Current: 30 mA (typ) at full load. Shutdown Current: 30 nA (typ) when S/D pin is low. Precision Output Voltage: 1.5% room temperature accuracy. TYPICAL APPLICATION CIRCUIT LP38841 IN IN BIAS 5V ± 10% 4.7 PF* BIAS 0.1 PF OUT OUT 10 PF Ceramic S/D S/D GND GND GND * Minimum value required if Tantalum capacitor is used (see Application Hints). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated LP38841 SNVS289C – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. CONNECTION DIAGRAM Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View PIN DESCRIPTIONS Pin Name BIAS OUTPUT GND Description The bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and provides drive voltage for the N-FET. The regulated output voltage is connected to this pin. This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and DDPAK/TO-263 packages are at ground potential. Pin three and the tab should be tied together using the PC board copper trace material and connected to circuit ground. INPUT The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin. Because the bias voltage to operate the chip is provided separately, the input voltage can be as low as a few hundred millivolts above the output voltage. SHUTDOWN This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if this function is not used. BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38841 LP38841 www.ti.com SNVS289C – DECEMBER 2004 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Semiconductor Sales Office/ Distributors for availability and specifications. −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) ESD Rating Human Body Model Machine Model (3) Power Dissipation 260°C (2) 2 kV 200V (4) Internally Limited VIN Supply Voltage (Survival) −0.3V to +6V VBIAS Supply Voltage (Survival) −0.3V to +7V Shutdown Input Voltage (Survival) −0.3V to +7V IOUT (Survival) Internally Limited −0.3V to +6V Output Voltage (Survival) −40°C to +150°C Junction Temperature (1) (2) (3) (4) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. The machine model is a 220 pF capacitor discharged directly into each pin. At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be assumed. θJ-A for DDPAK/TO-263 devices is approximately 35°C/W if soldered down to a copper plane which is at least 1 square inch in area. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. RECOMMENDED OPERATING CONDITIONS VIN Supply Voltage (VOUT + VDO) to 5.5V Shutdown Input Voltage 0 to +5.5V IOUT 0.8A −40°C to +125°C Operating Junction Temperature Range VBIAS Supply Voltage 4.5V to 5.5V VOUT 0.8V to 1.5V Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38841 3 LP38841 SNVS289C – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER, VS/D = VBIAS. Min/Max limits are specified through testing, statistical correlation, or design. (1) Symbol VO Parameter Conditions Output Voltage Tolerance 10 mA < IL < 0.8A VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 5.5V (3) ΔVO/ΔVIN Output Voltage Line Regulation ΔVO/ΔIL Output Voltage Load Regulation VDO Dropout Voltage IQ(VIN) Quiescent Current Drawn from VIN Supply (4) (5) Min ISC Quiescent Current Drawn from VBIAS Supply Short-Circuit Current Max 0.8 0.812 0.824 1.182 1.164 1.2 1.218 1.236 1.478 1.455 1.5 1.523 1.545 0.01 Units V %/V 0.1 0.4 1.3 %/A IL = 0.8A 75 120 205 mV 10 mA < IL < 0.8A 30 35 40 mA 0.06 1 30 µA 2 4 6 mA VS/D ≤ 0.3V 0.03 1 30 µA VOUT = 0V 2.6 VS/D ≤ 0.3V IQ(VBIAS) (2) 0.788 0.776 VO(NOM) + 1V ≤ VIN ≤ 5.5V 10 mA < IL < 0.8A Typ 10 mA < IL < 0.8A A Shutdown Input VSDT Output Turn-off Threshold Output = ON Output = OFF 0.7 0.3 0.7 Td (OFF) Turn-OFF Delay RLOAD X COUT