LP38851
www.ti.com
SNVS492C – JUNE 2007 – REVISED APRIL 2013
LP38851 800 mA Fast-Response High-Accuracy Adjustable LDO Linear Regulator with
Enable and Soft-Start
Check for Samples: LP38851
FEATURES
DESCRIPTION
•
•
The LP38851-ADJ is a high current, fast response
regulator which can maintain output voltage
regulation with extremely low input to output voltage
drop. Fabricated on a CMOS process, the device
operates from two input voltages: VBIAS provides
voltage to drive the gate of the N-MOS power
transistor, while VIN is the input voltage which
supplies power to the load. The use of an external
bias rail allows the part to operate from ultra low VIN
voltages. Unlike bipolar regulators, the CMOS
architecture consumes extremely low quiescent
current at any output load current. The use of an NMOS power transistor results in wide bandwidth, yet
minimum external capacitance is required to maintain
loop stability.
1
2
•
•
•
•
•
•
Adjustable VOUT Range of 0.80V to 1.8V
Wide VBIAS Supply Operating Range of 3.0V to
5.5V
Stable with 10µF Ceramic Capacitors
Dropout Voltage of 115 mV (Typical) at 800 mA
Load Current
Precision VADJ across All Line and Load
Conditions:
– ±1.5% VADJ for TJ = 25°C
– ±2.0% VADJ for 0°C ≤ TJ ≤ +125°C
– ±3.0% VADJ for -40°C ≤ TJ ≤ +125°C
Over-Temperature and Over-Current
Protection
Available in 8-Lead SO PowerPad,
7-Lead SFM and 7-Lead PFM Packages
−40°C to +125°C Operating Junction
Temperature Range
APPLICATIONS
•
•
•
•
ASIC Power Supplies in:
– Desktops, Notebooks, and Graphics Cards,
Servers
– Gaming Set Top Boxes, Printers and
Copiers
Server Core and I/O Supplies
DSP and FPGA Power Supplies
SMPS Post-Regulator
The fast transient response of this device makes it
suitable for use in powering DSP, Microcontroller
Core voltages and Switch Mode Power Supply post
regulators. The part is available in PSOP 8–pin, SFM
7–pin, and TO-263 7-pin packages.
• Dropout Voltage: 115 mV (typical) at 800 mA
load current
• Low Ground Pin Current: 10 mA (typical) at 800
mA load current
• Soft-Start: Programmable Soft-Start time
• Precision ADJ Voltage: ±1.5% for TJ = 25°C,
and ±2.0% for 0°C ≤ TJ ≤ +125°C, across all line
and load conditions
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LP38851
SNVS492C – JUNE 2007 – REVISED APRIL 2013
www.ti.com
TYPICAL APPLICATION CIRCUIT
LP38851-ADJ
VIN
IN
VBIAS
VOUT
OUT
CIN
10 PF Ceramic
CFF
R1
BIAS
CBIAS
1 PF
VEN
SS
COUT
10 PF
Ceramic
ADJ
EN
R2
GND
CSS
GND
GND
Connection Diagram
1
2
3
4
5
6
7
TAB
IS
GND
LP38851S-ADJ
SS
EN
IN
GND
ADJ
OUT
BIAS
7 IN
BIAS 3
6 EN
GND 4
5 SS
Figure 3. 8-Lead SO PowerPad - Top View
See DDA Package
TAB
IS
GND
LP38851T-ADJ
1
2
3
4
5
6
7
8 N/C
DAP
Connect to GND
Figure 1. 7-Lead PFM - Top View
See KTW0007B Package
SS
EN
IN
GND
ADJ
OUT
BIAS
ADJ 1
OUT 2
Figure 2. 7-Lead SFM - Top View
See NDZ0007B Package
PIN DESCRIPTIONS
2
SFM
Pin #
PFM
Pin #
SO PowerPad
Pin #
Pin
Symbol
1
1
5
SS
Soft-Start capacitor connection. Used to control the rise time of
VOUT at turn-on.
2
2
6
EN
Device Enable, High = On, Low = Off.
3
3
7
IN
The unregulated voltage input
4
4
4
GND
Ground
5
5
1
ADJ
The feedback connection to set the output voltage
6
6
2
OUT
The regulated output voltage
7
7
3
BIAS
The supply for the internal control and reference circuitry.
-
-
8
N/C
No internal connection
TAB
TAB
-
TAB
The SFM and PFM TAB is a thermal and electrical connection that
is physically attached to the backside of the die, and used as a
thermal heat-sink connection. See APPLICATION INFORMATION
for details.
Pin Description
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP38851
LP38851
www.ti.com
SNVS492C – JUNE 2007 – REVISED APRIL 2013
PIN DESCRIPTIONS (continued)
SFM
Pin #
PFM
Pin #
SO PowerPad
Pin #
Pin
Symbol
-
-
DAP
DAP
Pin Description
The SO PowerPad DAP is a thermal connection only that is
physically attached to the backside of the die, and used as a
thermal heat-sink connection. See APPLICATION INFORMATION
for details.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1)
−65°C to +150°C
Storage Temperature Range
Lead Temperature
Soldering, 5 seconds
ESD Rating
Power Dissipation
Human Body Model
260°C
(2)
(3)
±2 kV
Internally Limited
VIN Supply Voltage (Survival)
−0.3V to +6.0V
VBIAS Supply Voltage (Survival)
−0.3V to +6.0V
VSS SoftStart Voltage (Survival)
−0.3V to +6.0V
VOUT Voltage (Survival)
−0.3V to +6.0V
IOUT Current (Survival)
Internally Limited
Junction Temperature
−40°C to +150°C
(1)
(2)
(3)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For specifications and conditions, see the
Electrical Characteristics.
The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114.
Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to
ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not
exceed the maximum operating rating. See APPLICATION INFORMATION for details.
OPERATING RATINGS
(1)
VIN Supply Voltage
(VOUT + VDO) to VBIAS
0.8V ≤ VOUT ≤ 1.2V
VBIAS Supply Voltage
1.2V < VOUT ≤ 1.8V
VEN Voltage
0 mA to 800 mA
Junction Temperature Range
(2)
4.5V to 5.5V
0.0V to VBIAS
IOUT
(1)
3.0V to 5.5V
(2)
−40°C to +125°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For specifications and conditions, see the
Electrical Characteristics.
Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to
ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not
exceed the maximum operating rating. See APPLICATION INFORMATION for details.
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP38851
3
LP38851
SNVS492C – JUNE 2007 – REVISED APRIL 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF,
CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction
temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only.
Symbol
VADJ
VOUT
ΔVOUT/ΔVIN
ΔVOUT/ΔVBIAS
ΔVOUT/ΔIOUT
VDO
IGND(IN)
Parameter
Conditions
VADJ Accuracy
VOUT Range
VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V
3.0V ≤ VBIAS ≤ 5.5V,
10 mA ≤ IOUT ≤ 800 mA
(1)
VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V
3.0V ≤ VBIAS ≤ 5.5V,
10 mA ≤ IOUT ≤ 800 mA,
0°C ≤ TJ ≤ +125°C
(1)
Min
Typ
Max
492.5
485.0
500.
507.5
515.0
mV
490.0
510.0
0.80
1.20
4.5V ≤ VBIAS ≤ 5.5V
0.80
1.80
V
Line Regulation, VIN (2)
VOUT(NOM)+1V ≤ VIN ≤ VBIAS
-
0.04
-
%/V
Line Regulation, VBIAS (2)
3.0V ≤ VBIAS ≤ 5.5V
-
0.10
-
%/V
10 mA ≤ IOUT ≤ 800 mA
-
0.2
-
%/A
mV
Output Voltage Load Regulation
Dropout Voltage
(3)
(4)
Quiescent Current Drawn from VIN
Supply
IOUT = 800 mA
-
115
150
200
VOUT = 0.80V
VBIAS = 3.0V
10 mA ≤ IOUT ≤ 800 mA
-
7.0
8.5
9.0
mA
1
100
300
μA
Quiescent Current Drawn from
VBIAS Supply
3.0
3.8
4.5
mA
100
170
200
μA
2.20
2.00
2.45
2.70
2.90
V
60
50
150
300
350
mV
-
2.3
-
A
11.0
14.0
17.0
kΩ
-
700
-
μs
-
10 mA ≤ IOUT ≤ 800 mA
-
VEN ≤ 0.5V
UVLO
Under-Voltage Lock-Out Threshold
VBIAS rising until device is functional
UVLO(HYS)
Under-Voltage Lock-Out Hysteresis
VBIAS falling from UVLO threshold until
device is non-functional
Output Short-Circuit Current
VIN = VOUT(NOM) + 1V,
VBIAS = 3.0V, VOUT = 0.0V
ISC
500.
3.0V ≤ VBIAS ≤ 5.5V
VEN ≤ 0.5V
IGND(BIAS)
Units
Soft-Start
rSS
Soft-Start internal resistance
tSS
Soft-Start time
tSS = CSS × rSS × 5
CSS = 10 nF
Enable
VEN = VBIAS
IEN
ENABLE pin Current
0.01
-
VEN = 0.0V, VBIAS = 5.5V
-24
-21
-35
-43
-50
1.00
0.90
1.25
1.50
1.55
V
50
30
100
150
200
mV
VEN(ON)
Enable Voltage Threshold
VEN rising until Output = ON
VEN(HYS)
Enable Voltage Hysteresis
VEN falling from VEN(ON) until Output =
OFF
tOFF
Turn-OFF Delay Time
RLOAD x COUT
