LP38853EVAL

User's Guide SNVA178C – November 2006 – Revised April 2013 AN-1504 LP38853S-ADJ Evaluation Board 1 Introduction This board is designed to allow the evaluation of the LP38853S-ADJ Voltage Regulator. Each board is assembled and tested in the factory. This evaluation board has the TO-263 7-lead package mounted, and the output voltage is set to 1.20V. 2 General Description The LP38853 is a dual-rail adjustable LDO linear regulator capable of suppling up to 3A of output current, and incorporates an Enable function as well as a Soft-Start function. The device has been designed to work with 10 µF input and output ceramic capacitors, and 1µF bias capacitor. Footprints areas for CIN and COUT will allow for a variety of sizes. 3 Operation The input voltage, applied between VIN and GND, should be at least 1.0V greater than VOUT and no greater than the applied VBIAS voltage. The bias voltage, applied between VBIAS and GND should be above the minimum bias voltage of 3.0V, and no more than the maximum of 5.5V. Loads can be connected to VOUT with reference to GND. VOUT and VIN test points are provided on the board to allow accurate measurements directly onto the input and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the load. 4 Setting VOUT The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the formula: VOUT = VADJ × (1 + (R1 / R2)) (1) It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and CFF. The LP38853S-ADJ Evaluation board is assembled with a 1.40 kΩ ±1% resistor for R1, and a 1.00 kΩ ±1% resistor for R2. This sets VOUT to 1.20V. 5 Selecting CFF A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the formula: FZ = (1 / (2 × π × CFF × R1) ) (2) The value for CFF should be selected to set a zero frequency (FZ) between 10 kHz and 15 kHz using the formula: CFF = 1 / (2 × π × FZ × R1) (3) All trademarks are the property of their respective owners. SNVA178C – November 2006 – Revised April 2013 Submit Documentation Feedback AN-1504 LP38853S-ADJ Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 1 Enable Function www.ti.com The closest standard 10% value is usually adequate for CFF. The LP38853-ADJ Evaluation board is assembled with a 0.01 μF capacitor for CFF. This sets FZ to approximately 11.4 kHz. Figure 1. 10mA to 3A Load Transient Response 6 Figure 2. 1A to 3A Load Transient Response Enable Function ON/OFF control is provided by supplying a logic level signal to the Enable pin. A minimum VEN value of 1.3V is typically required at this pin to enable the LDO output. The LDO output will be shutdown when the VEN value is typically 1.0V or less. The VEN threshold incorporates approximately 100mV of hysteresis. In applications where the LP38853 is operated continuously the Enable pin can be connected directly to VBIAS, or left open. The Enable pin has a 200 kΩ internal resistor to VBIAS. If the Enable pin is left open, care should be taken to minimize any capacitance on the Enable pin, as any capacitance will introduce an RC delay time on the Enable function. Figure 3. Enable Thresholds 2 AN-1504 LP38853S-ADJ Evaluation Board SNVA178C – November 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Soft-Start Function www.ti.com 7 Soft-Start Function VREF will rise at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor (CSS) connected to the SS pin. This allows the output voltage to rise in a controlled manner until steadystate regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in current limit. The LP38853S-ADJ Evaluation board is assembled with a 0.01 μF capacitor for CSS. This sets the softstart time to approximately 750 μs. Figure 4. VOUT Soft-Start 8 Power Dissipation The TO-263 package alone has a junction to ambient thermal resistance (θJA) rating of 60°C/W. When mounted on the LP38853S evaluation board the θJA rating is approximately 40°C/W. Although there is only approximately 0.30 square inches of 1 ounce copper area immediately under the tab, the top copper surface area is extended to additional copper area on the bottom of the board by nine thermal vias. With the 40°C/W thermal rating the LP38853S-ADJ evaluation board will dissipate a maximum of 2.5W with TA = 25°C. Figure 5. Maximum Power Dissipation vs Ambient Temperature SNVA178C – November 2006 – Revised April 2013 Submit Documentation Feedback AN-1504 LP38853S-ADJ Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 3 Pin Out 9 www.ti.com Pin Out 1 2 3 4 5 6 7 TAB IS GND LP38853S-ADJ SS EN IN GND ADJ OUT BIAS Figure 6. Pin Out 10 Schematic Diagram TP3 TP7 TP2 TP1 TP4 TP5 TP6 LP38853S-ADJ VIN (J3) IN (3) CFF 0.01 PF R1 1.40 k: VOUT (J6) BIAS (7) VBIAS (J7) VEN (J2) (6) OUT CIN 10 PF CBIAS 1 PF EN (2) SS (1) COUT 10 PF (5) ADJ GND (4) R2 1.00 k: CSS 0.01 PF GND (J4) Figure 7. Evaluation Board Schematic. 4 AN-1504 LP38853S-ADJ Evaluation Board SNVA178C – November 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated PCB Layout www.ti.com 11 PCB Layout TP1 CSS (C5) 0.01 PF CBIAS (C2) 1 PF TP7 U1 TP2 C5 J7 LP38853S -ADJ VEN C2 BIAS CFF (C4) 0.01 PF J2 R2 TP5 EN C4 C1 TP3 VIN C3 R2 1.00 k: R1 R1 1.40 k: TP6 TP4 J3 VBIAS J6 VIN VOUT VOUT GND J4 CIN (C1) 10 PF GND COUT (C3) 10 PF Figure 8. Evaluation Board Component and Pin Layout SNVA178C – November 2006 – Revised April 2013 Submit Documentation Feedback AN-1504 LP38853S-ADJ Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 5 Bill of Materials 12 6 www.ti.com Bill of Materials ID Name Description Manufacturer Part Number U1 U1 LP38853 Texas Instruments LP38853 C1 CIN Capacitor: 10 µF; ±10%; MLCC; 10V; X7R; 1210 1210ZC106KAT2A C2 CBIAS Capacitor: 1 µF;, ±10%; MLCC; 10V; X7R; 0805 0805ZC105KAT2A C3 COUT Capacitor: 10 µF;, ±10%; MLCC; 10V; X7R; 1210 C4 CFF Capacitor: 0.01 µF;, ±10%; MLCC; 10V; X7R; 0805 0805YC103KAT2A C5 CSS Capacitor: 0.01 µF; ±10%;, MLCC; 10V; X7R; 0805 0805YC103KAT2A J2 VEN Banana Jack : Insulated Solder Terminal; White 108-0901-001 J3 VIN Banana Jack : Insulated Solder Terminal; Red 108-0902-001 J4 GND Banana Jack : Insulated Solder Terminal; Black J6 VOUT Banana Jack : Insulated Solder Terminal; Orange 108-0906-001 J7 VBIAS Banana Jack : Insulated Solder Terminal; Blue 108-0910-001 R1 R1 Resistor: 1.40 kΩ, ±1%; Thick Film; 250 mW; ±100 ppm; 0805 R2 R2 TP1 TPSS TP2 TPEN TP3 TPIN TP4 TPGND TP5 TPADJ TP6 TPOUT TP7 TPBIAS Resistor: 1.00 kΩ, ±1%; Thick Film; 250 mW; ±100 ppm; 0805 Turret Terminal : Mounting Hole Diameter = 0.062” AN-1504 LP38853S-ADJ Evaluation Board AVX Johnson Components 1210ZC106KAT2A 108-0903-001 CRCW 0805 1401 F VISHAY DALE Keystone CRCW 0805 1001 F 1593–2 SNVA178C – November 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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