LP38856SX-0.8

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LP38856 SNVS336F – JUNE 2006 – REVISED AUGUST 2015 LP38856 3-A Fast-Response High-Accuracy LDO Linear Regulator With Enable 1 Features 3 Description • • • • • The LP38856 is a high-current, fast-response regulator which can maintain output voltage regulation with an extremely low input-to-output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides power for the internal bias and control circuits, as well as drive for the gate of the N-MOS power transistor, while VIN supplies power to the load. The use of an external bias rail allows the part to operate from ultra-low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 • • • Input Voltage: 1.1 V to 5.5 V Wide VBIAS Supply Operating Range: 3 V to 5.5 V Standard VOUT: 0.8 V and 1.2 V Stable with 10-µF Ceramic Capacitors Dropout Voltage of 240 mV (Typical) at 3-A Load Current Precision Output Voltage Across All Line and Load Conditions: – ±1% for TJ = 25°C – ±2% for 0°C ≤ TJ ≤ +125°C – ±3% for –40°C ≤ TJ ≤ +125°C Overtemperature and Overcurrent Protection –40°C to +125°C Operating Temperature Range The fast transient response of this device makes it suitable for use in powering DSP, microcontroller core voltages, and switch mode power supply post regulators. The LP38856 is available in 5-pin TO-220 and DDPAK/TO-263 packages. • Dropout Voltage: 240 mV (typical) at 3-A load current. • Low Ground Pin Current: 10 mA (typical) at 3-A load current. • Shutdown Current: 1 µA (typical) IIN(GND) when EN pin is low. • Precision Output Voltage: ±1% for TJ = 25°C and ±2% for 0°C ≤ TJ ≤ +125°C, across all line and load conditions. 2 Applications • • • • ASIC Power Supplies In: – Desktops, Notebooks, and Graphics Cards, Servers – Gaming Set Top Boxes, Printers and Copiers Server Core and I/O Supplies DSP and FPGA Power Supplies SMPS Post-Regulator Device Information(1) PART NUMBER LP38856 PACKAGE BODY SIZE (NOM) DDPAK/TO-263 (5) 10.16 mm × 8.42 mm TO-220 (5) 14.986 mm × 10.16 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit LP38856-x.x VIN VBIAS VEN IN VOUT OUT CIN 10 PF Ceramic BIAS CBIAS 1 PF COUT 10 PF Ceramic EN GND GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP38856 SNVS336F – JUNE 2006 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 3 4 4 4 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application ................................................. 12 9 Power Supply Recommendations...................... 14 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Example .................................................... 15 11 Device and Documentation Support ................. 16 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2013) to Revision F • Added Device Information and Pin Configuration and Functions sections, ESD Ratings table, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; remove lead temp from Abs Max (in POA), remove obsolete heatsinking content ...................................................................................................... 1 Changes from Revision D (April 2013) to Revision E • 2 Page Page Changed layout of National data sheet to TI format ............................................................................................................ 14 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F – JUNE 2006 – REVISED AUGUST 2015 5 Pin Configuration and Functions KTT Package 5-Pin DDPAK/TO-263 Top View EN 1 GND 3 OUT 4 TAB IS GND TAB IS GND EN 1 LP38856T-x.x LP38856S-x.x IN 2 NDH Package 5-Pin TO-220 Top View IN 2 GND 3 OUT 4 BIAS 5 BIAS 5 Pin Functions PIN NO. TYPE NAME DESCRIPTION 1 EN I The device enable pin. 2 IN I The unregulated input voltage pin 3 GND — Ground 4 OUT O The regulated output voltage pin 5 BIAS I The supply for the internal control and reference circuitry TAB TAB — The TAB is a thermal connection that is physically attached to the backside of the die, and is used as a thermal heat-sink connection. See the Application and Implementation section for details 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN Power dissipation (3) MAX UNIT Internally limited VIN Supply voltage (survival) –0.3 6 V VBIAS Supply voltage (survival) –0.3 6 V VEN Voltage (survival) –0.3 6 V VOUT Voltage (survival) –0.3 6 V IOUT Current (survival) Internally Limited TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications. Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (RθJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See Application and Implementation for details. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LP38856 3 LP38856 SNVS336F – JUNE 2006 – REVISED AUGUST 2015 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN NOM MAX VIN Supply voltage (VOUT + VDO) VBIAS Supply voltage 3 5.5 VEN Enable input voltage 0.0 VBIAS IOUT Output current 0 3 –40 125 Junction temperature range (1) (2) (2) UNIT VBIAS V mA/A °C Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits (see Electrical Characteristics). Specifications do not apply when operating the device outside of its rated operating conditions. Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (RθJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See Application and Implementation for details. 6.4 Thermal Information LP38856 THERMAL METRIC (1) KTT (DDPAK/TO-263) NDH (TO-220) UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 41.8 32.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 45.0 43.8 °C/W RθJB Junction-to-board thermal resistance 24.8 18.6 °C/W ψJT Junction-to-top characterization parameter 13.1 8.8 °C/W ψJB Junction-to-board characterization parameter 23.8 18.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 1.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics Unless otherwise specified: VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, VEN = VBIAS. Limits apply for TJ = 25°C only unless otherwise specified. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER VOUT Output Voltage Tolerance MIN TYP MAX VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS 3 V ≤ VBIAS ≤ 5.5 V, 10 mA ≤ IOUT ≤ 3 A TEST CONDITIONS –1% 0% +1% VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS 3 V ≤ VBIAS ≤ 5.5 V, 10 mA ≤ IOUT ≤ 3 A TJ = –40°C to 125°C –3% VOUT(NOM) + 1V ≤ VIN ≤ VBIAS 3 V ≤ VBIAS ≤ 5.5 V, 10 mA ≤ IOUT ≤ 3.0A 0°C ≤ TJ ≤ 125°C –2% UNIT 3% 0% 2% ΔVOUT/ΔVIN Line regulation, VIN (1) VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS 0.04 %/V ΔVOUT/ΔVBIAS Line regulation, VBIAS (1) 3 V ≤ VBIAS ≤ 5.5 V 0.10 %/V ΔVOUT/ΔIOUT Output voltage load regulation (2) 10 mA ≤ IOUT ≤ 3 A 0.2 IOUT = 3 A 240 VDO (1) (2) (3) 4 Dropout voltage, VIN − VOUT (3) IOUT = 3 A, TJ = –40°C to 125°C %/A 300 450 mV Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined the as input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop no more than 2% from the nominal value Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F – JUNE 2006 – REVISED AUGUST 2015 Electrical Characteristics (continued) Unless otherwise specified: VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, VEN = VBIAS. Limits apply for TJ = 25°C only unless otherwise specified. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN LP38856-0.8: 10 mA ≤ IOUT ≤ 3 A TYP MAX 7 8.5 LP38856-0.8: 10 mA ≤ IOUT ≤ 3 A TJ = –40°C to 125°C IGND(IN) Ground pin current drawn from VIN supply 9 LP38856-1.2: 10 mA ≤ IOUT ≤ 3 A 11 LP38856-1.2: 10 mA ≤ IOUT ≤ 3 A TJ = –40°C to 125°C 1 VEN ≤ 0.5 V, TJ = –40°C to 125°C 3 10 mA ≤ IOUT ≤ 3 A TJ = –40°C to 125°C Undervoltage lock-out threshold UVLO(HYS) Undervoltage lock-out hysteresis VEN ≤ 0.5 V 100 2.20 VBIAS rising until device is functional TJ = –40°C to 125°C 2 60 2.45 150 Output short-circuit current VIN = VOUT(NOM) + 1 V, VBIAS = 3 V VOUT = 0 V µA mA µA 2.70 2.9 50 ISC 170 200 VBIAS rising until device is functional VBIAS falling from UVLO threshold until device is non-functional mA 3.8 4.5 VEN ≤ 0.5 V, TJ = –40°C to 125°C UVLO 10 300 10 mA ≤ IOUT ≤ 3 A Ground pin current drawn from VBIAS supply 12 15 VEN ≤ 0.5 V IGND(BIAS) UNIT 300 V mV 350 6.2 A ENABLE PIN VEN = VBIAS IEN ENABLE pin current 0.01 VEN = 0 V, VBIAS = 5.5 V –19 VEN = 0 V, VBIAS = 5.5 V TJ = –40°C to 125°C –13 VEN rising until Output = ON 1 VEN rising until Output = ON TJ = –40°C to 125°C 0.9 VEN falling from VEN(ON) until Output = OFF 50 VEN falling from VEN(ON) until Output = OFF TJ = –40°C to 125°C 30 –30 –40 µA –51 1.25 VEN(ON) Enable voltage threshold VEN(HYS) Enable voltage hysteresis tOFF Turn-OFF delay time RLOAD × COUT