LP38858SX-0.8

LP38858 www.ti.com SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 1.5A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start Check for Samples: LP38858 FEATURES DESCRIPTION • • The LP38858 is a high current, fast response regulator which can maintain output voltage regulation with extremely low input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides voltage to drive the gate of the N-MOS power transistor, while VIN is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an NMOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 2 • • • • • • • Standard VOUT Values of 0.8V and 1.2V Wide VBIAS Supply Operating Range of 3.0V to 5.5V Stable with 10µF Ceramic Capacitors Dropout Voltage of 130 mV (Typical) at 1.5A Load Current Precision Output Voltage across All Line and Load Conditions: – ±1.0% VOUT for TJ = 25°C – ±2.0% VOUT for 0°C ≤ TJ ≤ +125°C – ±3.0% VOUT for -40°C ≤ TJ ≤ +125°C Over-Temperature and Over-Current Protection Available in 5 Lead TO-220 and DDPAK/TO-263 Packages Custom VOUT Values between 0.8V and 1.2V are Available −40°C to +125°C Operating Temperature Range The fast transient response of this device makes it suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The LP38858 is available in TO-220 and DDPAK/TO-263 5-Lead packages. Dropout Voltage: 130mV (typical) at 1.5A load current. APPLICATIONS • • • • Low Ground Pin Current: 10 mA (typical) at 1.5A load current. ASIC Power Supplies In: – Desktops, Notebooks, and Graphics Cards, Servers – Gaming Set Top Boxes, Printers and Copiers Server Core and I/O Supplies DSP and FPGA Power Supplies SMPS Post-Regulator Soft-Start: Programmable Soft-Start time. Precision Output Voltage: ±1.0% for TJ = 25°C and ±2.0% for 0°C ≤ TJ ≤ +125°C, across all line and load conditions Typical Application Circuit LP38858-x.x VIN IN VOUT OUT CIN VBIAS 10 PF Ceramic BIAS CBIAS COUT 10 PF Ceramic 1 PF SS GND CSS GND GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LP38858 SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Connection Diagram TAB IS GND SS 1 OUT 4 SS 1 LP38858T-x.x GND 3 LP38858S-x.x IN 2 IN 2 GND 3 OUT 4 BIAS 5 TAB IS GND BIAS 5 Figure 1. DDPAK/TO-263–5 Package (Top View) See Package Number KTT0005B Figure 2. TO220–5 Package (Top View) See Package Number NDH0005D Pin Descriptions TO-220–5 and DDPAK/TO-263–5 Packages Pin # Pin Symbol 1 SS Soft-Start capacitor connection. Used to slow the rise time of VOUT at turn-on. Pin Description 2 IN The unregulated voltage input pin. 3 GND Ground 4 OUT The regulated output voltage pin. 5 BIAS The supply for the internal control and reference circuitry. TAB TAB The TAB is a thermal connection that is physically attached to the backside of the die, and used as a thermal heat-sink connection. See the Application Information section for details. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −65°C to +150°C Storage Temperature Range Lead Temperature Soldering, 5 seconds ESD Rating Human Body Model (3) Power Dissipation (4) 260°C ±2 kV Internally Limited VIN Supply Voltage (Survival) −0.3V to +6.0V VBIAS Supply Voltage (Survival) −0.3V to +6.0V VSS Soft-Start Voltage (Survival) −0.3V to +6.0V −0.3V to +6.0V VOUT Voltage (Survival) IOUT Current (Survival) Internally Limited Junction Temperature −40°C to +150°C (1) (2) (3) (4) 2 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114. The HBM rating for device pin 1 (SS) is ±1.5 kV. Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 LP38858 www.ti.com SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 Operating Ratings (1) VIN Supply Voltage (VOUT + VDO) to VBIAS VBIAS Supply Voltage 3.0V to 5.5V IOUT 0 mA to 1.5A Junction Temperature Range (2) (1) −40°C to +125°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions, see the Electrical Characteristics. Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. (2) Electrical Characteristics Unless otherwise specified: VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions VOUT(NOM) + 1V ≤ VIN ≤ VBIAS, 3.0V ≤ VBIAS ≤ 5.5V, 10 mA ≤ IOUT ≤ 1.5A VOUT VOUT Accuracy MIN TYP MAX -1.0 -3.0 0 1.0 3.0 Units % VOUT(NOM) + 1V ≤ VIN ≤ VBIAS, 3.0V ≤ VBIAS ≤ 5.5V, 10 mA ≤ IOUT ≤ 1.5A, 0°C ≤ TJ ≤ +125°C -2.0 0 2.0 ΔVOUT/ΔVIN Line Regulation, VIN (1) VOUT(NOM) + 1V ≤ VIN ≤ VBIAS - 0.04 - %/V ΔVOUT/ΔVBIAS Line Regulation, VBIAS (1) 3.0V ≤ VBIAS ≤ 5.5V - 0.10 - %/V 10 mA ≤ IOUT ≤ 1.5A - 0.2 - %/A mV ΔVOUT/ΔIOUT Output Voltage Load Regulation (2) (3) VDO Dropout Voltage IGND(IN) Quiescent Current Drawn from VIN Supply IOUT = 1.5A - 130 165 180 LP38858-0.8 10 mA ≤ IOUT ≤ 1.5A - 7.0 8.5 9.0 11 12 15 - 3.0 3.8 4.5 mA 2.20 2.00 2.45 2.70 2.90 V 60 50 150 300 350 mV - 4.5 - A LP38858-0.8 11.0 13.5 16.0 LP38858-1.2 13.5 16.0 18.5 LP38858-0.8, CSS = 10 nF - 675 - LP38858-1.2, CSS = 10 nF - 800 - LP38858-1.2 10 mA ≤ IOUT ≤ 1.5A IGND(BIAS) Quiescent Current Drawn from VBIAS Supply 10 mA ≤ IOUT ≤ 1.5A UVLO Under-Voltage Lock-Out Threshold VBIAS rising until device is functional UVLO(HYS) Under-Voltage Lock-Out Hysteresis VBIAS falling from UVLO threshold until device is non-functional ISC Output Short-Circuit Current VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VOUT = 0.0V mA Soft-Start rSS Soft-Start internal resistance tSS Soft-Start time tSS = CSS × rSS × 5 (1) (2) (3) kΩ μs Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined the as input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop 2% from the nominal value. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 3 LP38858 SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions MIN TYP MAX VIN = VOUT(NOM) + 1V, f = 120 Hz - 80 - VIN = VOUT(NOM) + 1V, f = 1 kHz - 65 - VBIAS = VOUT(NOM) + 3V, f = 120 Hz - 58 - VBIAS = VOUT(NOM) + 3V, f = 1 kHz - 58 - Output Noise Density f = 120 Hz - 1 - Output Noise Voltage VOUT = 1.8V BW = 10 Hz − 100 kHz - 150 - BW = 300 Hz − 300 kHz - 90 - Units AC Parameters PSRR (VIN) Ripple Rejection for VIN Input Voltage PSRR (VBIAS) Ripple Rejection for VBIAS Voltage en dB µV/√Hz µVRMS Thermal Parameters TSD Thermal Shutdown Junction Temperature - 160 - TSD(HYS) Thermal Shutdown Hysteresis - 10 - θJ-A Thermal Resistance, Junction to Ambient (4) TO-220-5 - 60 - DDPAK/TO-263-5 - 60 - θJ-C Thermal Resistance, Junction to Case (4) TO-220-5 - 3 - DDPAK/TO-263-5 - 3 - (4) 4 °C °C/W Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 LP38858 www.ti.com SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = open. VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature Figure 3. Figure 4. VIN Ground Pin Current vs Temperature Load Regulation vs Temperature Figure 5. Figure 6. Dropout Voltage (VDO) vs Temperature Output Current Limit (ISC) vs Temperature Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 5 LP38858 SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = open. 6 VOUT vs Temperature UVLO Thresholds vs Temperature Figure 9. Figure 10. Soft-Start Resistor (rSS) vs Temperature Soft-Start rSS Variation vs Temperature Figure 11. Figure 12. VOUT vs CSS, 10 nF to 47 nF VIN Line Transient Response Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 LP38858 www.ti.com SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = open. VIN Line Transient Response VBIAS Line Transient Response Figure 15. Figure 16. VBIAS Line Transient Response Load Transient Response, COUT = 10 µF Ceramic Figure 17. Figure 18. Load Transient Response, COUT = 10 µF Ceramic Load Transient Response, COUT = 100 µF Ceramic Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 7 LP38858 SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = open. 8 Load Transient Response, COUT = 100 µF Ceramic Load Transient Response, COUT = 100 µF Tantalum Figure 21. Figure 22. Load Transient Response, COUT = 100 µF Tantalum VBIAS PSRR Figure 23. Figure 24. VIN PSRR Output Noise Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 LP38858 www.ti.com SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 Block Diagram OUT IN LP38858-x.x BIAS Under-Voltage Lock-Out Thermal Shut Down rSS VREF SS ILIMIT GND 0.6V APPLICATION INFORMATION EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and returned to the device ground pin with a clean analog ground. Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide sufficient capacitance over temperature. Tantalum capacitors will also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, Tantalum and/or Aluminum, to be added in parallel. Input Capacitor The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended. Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any application where the ambient temperature falls below 0°C. Bias Capacitor The capacitor on the bias pin must be at least 1 µF, and can be any good quality capacitor (ceramic is recommended). Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 9 LP38858 SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com INPUT VOLTAGE The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever values is used for VBIAS. BIAS VOLTAGE The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3.0V to 5.5V to ensure proper operation of the device. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V. As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity. When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the device will be functional, but the operating parameters will not be within the specified limits. SUPPLY SEQUENCING There is no requirement for the order that VIN or VBIAS are applied or removed. One practical limitation is that the Soft-Start circuit starts charging CSS when VBIAS rises above the UVLO threshold. If the application of VIN is delayed beyond this point the benefits of Soft-Start will be compromised. In any case, the output voltage cannot be ensured until both VIN and VBIAS are within the range of specified operating values. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommended for this diode clamp. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold. When VBIAS is above the UVLO threshold the control circuitry is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 μF in this manner will not damage the device as the current will decay rapidly. However, continuous reverse current should be avoided. SOFT-START The LP38858 incorporates a Soft-Start function that reduces the start-up current surge into the output capacitor (COUT) by allowing VOUT to rise slowly to the final value. This is accomplished by controlling VREF at the SS pin. The soft-start timing capacitor (CSS) is internally held to ground until VBIAS rises above the Under-Voltage LockOut threshold (ULVO). VREF will rise at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in current limit. 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 LP38858 www.ti.com SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 Soft-Start Time = CSS × rSS × 5 (1) Since the VOUT rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ), and VOUT will require four additional time constants (4τ) to reach the final value (5τ) . After achieving normal operation, should VBIAS fall below the ULVO threshold the device output will be disabled and the Soft-Start capacitor (CSS) discharge circuit will become active. The CSS discharge circuit will remain active until VBIAS falls to 500 mV (typical). When VBIAS falls below 500 mV (typical), the CSS discharge circuit will cease to function due to a lack of sufficient biasing to the control circuitry. Since VREF appears on the SS pin, any leakage through CSS will cause VREF to fall, and thus affect VOUT. A leakage of 50 nA (about 10 MΩ) through CSS will cause VOUT to be approximately 0.1% lower than nominal, while a leakage of 500 nA (about 1 MΩ) will cause VOUT to be approximately 1% lower than nominal. Typical ceramic capacitors will have a factor of 10X difference in leakage between 25°C and 85°C, so the maximum ambient temperature must be included in the capacitor selection process. Typical CSS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs to 7 ms (5τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100 nF will provide soft-start, but may not be fully discharged if VBIAS falls from the UVLO threshold to less than 500 mV in less than 100 µs. Figure 27 shows the relationship between the COUT value and a typical CSS value. Figure 27. Typical CSS vs COUT Values The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components, other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT. If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value is always recommended. POWER DISSIPATION AND HEAT-SINKING Additional copper area for heat-sinking may be required depending on the maximum device dissipation (PD) and the maximum anticipated ambient temperature (TA) for the device. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is the sum of three different points of dissipation in the device. The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula: PD(PASS) = (VIN - VOUT) × IOUT (2) The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the formula: PD(BIAS) = VBIAS × IGND(BIAS) where • IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 (3) 11 LP38858 SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the formula: PD(IN) = VIN × IGND(IN) where • IGND(IN) is the portion of the operating ground current of the device that is related to VIN (4) The total power dissipation is then: PD = PD(PASS) + PD(BIAS) + PD(IN) (5) The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA) for the application, and the maximum allowable operating junction temperature (TJ(MAX)) . 'TJ = TJ(MAX) - TA(MAX) (6) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: 'TJ TJA d PD (7) Heat-Sinking the TO-220 Package The TO-220-5 package has a θJA rating of 60°C/W and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. If the needed θJA, as calculated above, is greater than or equal to 60°C/W then no additional heat-sinking is required since the package can safely dissipate the heat and not exceed the operating TJ(MAX). If the needed θJA is less than 60°C/W then additional heat-sinking is needed. The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for DDPAK/TO-263 package. The heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, θHA: THA d TJA - (TCH + TJC) where • • • θJA is the required total thermal resistance from the junction to the ambient air θCH is the thermal resistance from the case to the surface of the heart-sink θJC is the thermal resistance from the junction to the surface of the case (8) For this equation, θJC is about 3°C/W for a TO-220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the heat-sink manufacturer datasheet for details and recommendations. Heat-Sinking the DDPAK/TO-263 Package The DDPAK/TO-263 package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. The DDPAK/TO-263 package uses the copper plane on the PCB as a heat-sink. The tab of this package is soldered to the copper plane for heat sinking. shows a curve for the θJA of DDPAK/TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heatsinking. 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 LP38858 www.ti.com SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 Figure 28. θJA vs Copper (1 Ounce) Area for the DDPAK/TO-263 package Figure 28 shows that increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W. Figure 29 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Figure 29. Maximum Power Dissipation vs Ambient Temperature for the DDPAK/TO-263 Package Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 13 LP38858 SNVS462D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38858 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LP38858S-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP38858S -1.2 LP38858SX-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 RoHS-Exempt & Green SN Level-3-245C-168 HR -40 to 125 LP38858S -1.2 LP38858T-1.2/NOPB ACTIVE TO-220 NDH 5 45 RoHS & Green SN Level-1-NA-UNLIM -40 to 125 LP38858T -1.2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of