User's Guide
SNVA165B – June 2006 – Revised April 2013
AN-1480 LP38859S-1.2 Evaluation Board
1
Introduction
This board is designed to enable the evaluation of the LP38859 voltage regulator. Each board is
assembled and tested in the factory. This evaluation board has the TO-263 5–lead package mounted.
2
General Description
The LP38859 is a dual-rail LDO linear regulator capable of supplying up to 3A of output current, and
incorporates a Soft-Start feature.
The device has been designed to work with 10 µF input and output ceramic capacitors, and 1µF bias
capacitors. Footprints areas for CIN and COUT will allow for a variety of sizes.
3
Operation
The input voltage, applied between VIN and GND, should be at least 1.0 V greater than VOUT, and no higher
than the applied VBIAS voltage.
The bias voltage, applied between VBIAS and GND should be above the minimum bias voltage of 3.0 V,
and no higher than the maximum of 5.5 V.
Loads can be connected to VOUT with reference to GND.
VOUT and VIN test points are provided on the board to allow accurate measurements directly on the
evaluation board, eliminating any voltage drop on the PCB traces or connecting wires to the load.
The Soft-Start time for VOUT is an exponential function, and is adjusted by changing the Soft-Start
capacitor (CSS) on device pin one. An internal resistor (rSS) and the external capacitor (CSS) form an RC
circuit. Five RC time constants is considered to be the Soft-Start time.
Soft-Start Time = 5 x rSS x CSS
(1)
The installed soft-start capacitor (CSS) is 10 nF (0.01 μF), and the internal rSS is typically 16 kΩ.
Figure 1. VOUT vs CSS
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SNVA165B – June 2006 – Revised April 2013
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AN-1480 LP38859S-1.2 Evaluation Board
Copyright © 2006–2013, Texas Instruments Incorporated
1
Hardware
4
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Hardware
The schematic is shown in Figure 2 and the layout of the evaluation board is shown in Figure 3.
TP2 TP5
TP3 TP4
LP38859S-1.2
IN (2)
VIN
VOUT
(4) OUT
C1
10 PF
BIAS (5)
VBIAS
C2
1 PF
C3
10 PF
SS (1)
GND (3)
C5
0.01 PF
GND
Figure 2. Evaluation Board Schematic
PCB Layout
C5, 0.010 PF
R
2
C
S
S
TP1
C4
LP38859S1.2
TP5
TP5
C2
C2
R1
R1
TP2
J5
VBIAS
C2, 1 PF
C3
C3
C1
C1
C1, 10 PF
LP38859S-1.2EV
LP3885X-T/X-Rev2
R2 / C5
5
TP2
TP4
TP4
C3, 10 PF
TP3
TP3
J2
J3
J4
VIN
GND
VOUT
Figure 3. Evaluation Board Component and Pin Layout
6
Power Dissipation
The TO-263 package alone has a junction to ambient thermal resistance (θJA) rating of 60°C/W. When
mounted on the LP38859S evaluation board the θJA rating is approximately 37°C/W.
Although there is only approximately 0.28 square inches of copper area immediately under the tab, the top
copper surface area is extended to additional copper area on the bottom of the board by five thermal vias.
2
AN-1480 LP38859S-1.2 Evaluation Board
Copyright © 2006–2013, Texas Instruments Incorporated
SNVA165B – June 2006 – Revised April 2013
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Power Dissipation
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With the 37°C/W thermal rating the LP38859S evaluation board will dissipate a maximum of 2.75W with TA
= 25°C.
Figure 4. Maximum Power Dissipation vs Ambient Temperature
SNVA165B – June 2006 – Revised April 2013
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AN-1480 LP38859S-1.2 Evaluation Board
Copyright © 2006–2013, Texas Instruments Incorporated
3
Bill of Materials (BOM)
7
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Bill of Materials (BOM)
Table 1. Bill of Materials (BOM)
4
ID
Name
Description
U1
U1
LP38859
Texas Instruments
LP38859
C1
CIN
10 µF, 10%, MLCC, 10V, X7R, 1210
AVX
1210ZC106KAT2A
C2
CBIAS
1 µF, 10%, MLCC, 10V, X7R, 0805
AXV
0805ZC105KAT2A
C3
COUT
10 µF, 10%, MLCC, 10V, X7R, 1210
AVX
1210ZC106KAT2A
C4
—
Not Installed
C5
CSS
0.010 µF, 10%, MLCC, 16 V, X7R, 0805
J1
—
Not Installed
J2
VIN
Banana Jack : Insulated Solder Terminal RED
J3
GND
Banana Jack : Insulated Solder Terminal BLACK
J4
VOUT
Banana Jack : Insulated Solder Terminal ORANGE
108–0906–001
J5
VBIAS
Banana Jack : Insulated Solder Terminal BLUE
108–0910–001
R1
—
Not Installed
—
—
R2
—
Not Installed
—
—
TP1
—
Not Installed
—
—
TP2
TPIN
TP3
TPGND
TP4
TPOUT
Keystone
1593-2
TP5
TPBIAS
Turret Terminal :
Mounting Hole Diameter = 0.062”
Manufacturer
Part Number
—
—
AVX
0805YC103KAT2A
—
108–0902–001
Johnson
Components
AN-1480 LP38859S-1.2 Evaluation Board
Copyright © 2006–2013, Texas Instruments Incorporated
108–0903–001
SNVA165B – June 2006 – Revised April 2013
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