LP3905SD-30EV

User's Guide SNVA176A – March 2007 – Revised April 2013 AN-1501 LP3905-30 Evaluation Board 1 General Information The evaluation board is a complete circuit allowing full operation of the LP3905 within the recommended application circuit. Each board is pre-assembled and tested in the factory. The board contains the LP390530 in a 14 lead WSON package with all the associated passive components to enable all features of the device to be tested. LP3905 is optimized for low power handheld applications. This device provides two 600 mA DC/DC Buck regulators, and two 100 mA linear regulators as configured on the board. The LP3905 additionally features two enable pins allowing control over the device outputs. 2 Operational Information The circuit used in the evaluation board is that shown on the device datasheet. Lk4 1 Enable 2 3 LDO2 Output 0.47 PF 4 VINLDO1&2 1.0 PF 5 LDO1 Output 0.47 PF 6 LDO GND 7 Enable LP3905 EN2 FB2 TGND GND_B2 LDO2 SW2 Vin2 Vin1 LDO1 SW1 GND GND_B1 EN1 FB1 14 Buck2 Sense 13 12 10 PF 2.2 PH 11 10 VINBuck1&2 2.2 PH 10 PF 10 PF 9 1 3 Buck1 Output Buck1 Sense 8 PAD Lk1 2 Lk2 4 Buck2 Output Buck GND Lk3 Buck Gnd Plane GND LDO Gnd Plane Figure 1. Evaluation Board Schematic All trademarks are the property of their respective owners. SNVA176A – March 2007 – Revised April 2013 Submit Documentation Feedback AN-1501 LP3905-30 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 1 Connection Information www.ti.com The LP3905-30 has fixed output voltages as listed in Table 1. Table 1. LP3905-30 Output Voltages O/P Voltage (V) Buck1 1.2 Buck2 1.875 LDO1 2.8 LDO2 2.8 The board is fitted with 0.47µF capacitors on the outputs of the LDO’s and thus the load current for these LDO’s should not exceed 100mA. The device has 1MΩ internal resistors from EN1 and EN2 to GND. 3 Connection Information Connect a supply voltage (3.0V to 5.5V) to either of the VIN pins on the evaluation board. LK4 hardwired on the board connects both the BUCK supply side to the LDO supply side. These supplies are both required to correctly power the device. Supply ground may be connected at either GND or BKGND. LK3 which is hardwired on the eval board connects the BUCK gnd to the LDO gnd. For best results in current measurements on the Buck outputs, use 4 wire measurement techniques to eliminate any voltage drop on the PCB traces or connecting wires to the loads. For this the instrument sense connection should be connected to the corresponding buck ‘S’ (sense) connection on the evaluation board. Input leads should be kept reasonably short to minimize inductance. ON/OFF control is provided by logic signals on EN1 and EN2. A minimum of 1.2V is required on these pins to enable the corresponding outputs. The outputs will be shutdown with the enable pins set to 0.4V or less. If ON/OFF control is not required, then either or both enable pins may be connected to VIN either externally or by using the on-board connection matrix. A number of control options are provided on board by either hardwiring or using reconfigurable links on the 4-way matrix. Table 2. Link Matrix Details 2 Link Link Connection Description 1-2 3-4 EN1 and EN2 connect to VIN supply. All outputs power on with the supply voltage. 3-4 - EN1 connects to EN2 and may be driven externally from one source to control all outputs. 1-2 - EN1 conencts to VIN. Buck1, LDO1, and LDO2 outputs are enabled at device power up. Buck 2 should be enabled separately using an external source connected to EN2. 1-3 - EN2 conencts to VIN. Buck 2 is enabled at device power up. Buck1, LDO1, and LDO2 outputs should be enabled using an external source connected to EN1. - - Both EN1 and EN2 can be driven separately from external sources connected at the board inputs EN1 and EN2. AN-1501 LP3905-30 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated SNVA176A – March 2007 – Revised April 2013 Submit Documentation Feedback PCB Layout www.ti.com VIN EN2 EN2 pin EN1 Vin pin 1 EN1 pin 2 3 4 Header pins on square grid Figure 2. Link Matrix Diagram 4 PCB Layout Figure 3. PCB Component and Pin Layout Board SIze 1.5" × 1.3" 5 Bill of Materials Table 3. Bill of Materials for LP3905-30 WSON Evaluation Board Item Type Value U1 Qty Part Number Suggested Manufacturer Suggested Footprint 1 LP3905 Texas Instruments NHL0014B L1,L2 Inductor 1.0µF 1 DO3314-222MLB Coilcraft C1, C3 Capacitor 0.47µF 2 GRM188R61A474 KA61D Murata 0603 C4, C5, C6 Capacitor 10µF 3 GRM21BR61A106 KE19L Murata 0805 C2 Capacitor 1.0nF 1 GRM188R61A105 KA61D Murata 0603 SNVA176A – March 2007 – Revised April 2013 Submit Documentation Feedback AN-1501 LP3905-30 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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