LP3905SD-A3EV

User's Guide SNVA186B – March 2007 – Revised April 2013 AN-1527 LP3905-A3 Application Board 1 General Information The evaluation board is a complete circuit allowing full operation of the LP3905 within the recommended application circuit. Each board is pre-assembled and tested in the factory. The board contains the LP3905A3 in a 14 lead WSON package with all the associated passive components to enable all features of the device to be tested. LP3905 is optimized for low power handheld applications. This device provides two 600mA DC/DC Buck regulators, and two 100mA linear regulators as configured on the board. The LP3905-A3 allows the two buck output voltages to be set by the user. This option is a variation on the LP3905 device that has 4 fixed output voltages. The LP3905 additionally features two enable pins allowing control over the device outputs. R3 1 Enable 2 3 LDO2 Output 0.47 PF LDO1 Output C2 14 C8 FB2 TGND GND_B2 LDO2 SW2 R4 4 1.0 PF 5 0.47 PF Vin1 Vin2 SW1 LDO1 12 L2 10 PF C6 11 10 C5 2.2 PH 10 PF 10 PF L1 C3 6 7 Enable GND GND_B1 EN1 FB1 Buck2 Sense 13 2.2 PH C1 VINLDO1&2 LP3905-A3 EN2 9 C4 8 Buck2 Output VINBuck1&2 Buck1 Output Buck1 Sense R2 C7 PAD R1 Buck Gnd Plane LDO Gnd Plane Figure 1. Evaluation Board Schematic All trademarks are the property of their respective owners. SNVA186B – March 2007 – Revised April 2013 Submit Documentation Feedback AN-1527 LP3905-A3 Application Board Copyright © 2007–2013, Texas Instruments Incorporated 1 Operational Information 2 www.ti.com Operational Information The LP3905-A3 evaluation board has the output voltages set as follows: Table 1. LP3905-A3 Output Voltages O/P Voltage (V) Buck1 1.5 Buck2 1.85 LDO1 3.0 LDO2 2.8 The board is fitted with 0.47µF capacitors on the outputs of the LDO’s and thus the load current for these LDO’s should not exceed 100mA. The device has 1MΩ internal resistors from EN1 and EN2 to GND. 3 Output Voltage Pre-Set For initial use the LP3905-A3 sample board has been pre-set to 1.5V and 1.85V. The outputs of these two regulators may be set via the selection of the external resistor network forming the output feedback between the output voltage side of the inductor and the feedback pins (FB1, FB2) of the device and the feedback pins and ground. The user should thus alter the values of R1, R2 and C7 to give the desired output voltage on Buck1 and R3, R4, and C8 to change the output voltage on Buck2. 4 Output Voltage Selection L1 VOUT SW 2.2 PH C1 R1F FB COUT 10 PF C2 R2F LP3905 Figure 2. Adjustable Buck Components showing Resistor Feedback Network The recommended resistance between FB and GND is around 200kΩ. At this level the current through the resistor network is low but does not give rise to noise problems. The feedback node voltage is 0.5V and hence a 200kΩ resistor will result in a 2.5µA current. 2 AN-1527 LP3905-A3 Application Board Copyright © 2007–2013, Texas Instruments Incorporated SNVA186B – March 2007 – Revised April 2013 Submit Documentation Feedback Output Voltage Selection www.ti.com The formula for output voltage selection is: R1F R2F § © § © VOUT = VFB x 1+ (1) where: VOUT = output voltage (Volts) VFB = feedback voltage (0.5V) R1F = feedback resistor (VOUT to FB) R2F = feedback resistor (FB to GND) For any output voltage greater than or equal to 1.0V, a capacitor should be added across R1F. The chosen value of the capacitor is governed by the formula: C1 = 1 (2 x S x R1F x 45 x 103) (2) The value of this capacitor may be chosen from Table 2 giving the recommended component values for specified output voltages. C2 shown between the FB node and GND is only required at higher output voltages. Table 2. Recommended Component Values for Specified Output Voltages VOUT (V) R1F (kΩ) R2F (kΩ) C1 (pF) C2 (pF) 1.0 200 200 18 none 1.2 280 200 12 none 1.4 357 200 10 none 1.5 365 182 10 none 1.6 442 200 8.2 none 1.85 536 200 6.8 none 2.5 402 100 8.2 none 2.8 464 100 8.2 33 3.3 562 100 6.8 33 SNVA186B – March 2007 – Revised April 2013 Submit Documentation Feedback AN-1527 LP3905-A3 Application Board Copyright © 2007–2013, Texas Instruments Incorporated 3 Connection Information 5 www.ti.com Connection Information Connect a supply voltage (3.0V to 5.5V) to either of the VIN pins on the evaluation board. LK4 hardwired on the board connects both the BUCK supply side to the LDO supply side. These supplies are both required to correctly power the device. Supply ground may be connected at either GND or BKGND. LK3 which is hardwired on the eval board connects the BUCK gnd to the LDO gnd. For best results in current measurements on the Buck outputs, use 4 wire measurement techniques to eliminate any voltage drop on the PCB traces or connecting wires to the loads. For this the instrument sense connection should be connected to the corresponding buck ‘S’ (sense) connection on the evaluation board. Input leads should be kept reasonably short to minimize inductance. ON/OFF control is provided by logic signals on EN1 and EN2. A minimum of 1.2V is required on these pins to enable the corresponding outputs. The outputs will be shutdown with the enable pins set to 0.4V or less. If ON/OFF control is not required, then either or both enable pins may be connected to VIN either externally or by using the on-board connection matrix. A number of control options are provided on board by either hardwiring or using reconfigurable links on the 4-way matrix. Table 3. Link Matrix Details Link Link Connection Description 1-2 3-4 EN1 and EN2 connect to VIN supply. All outputs power on with the supply voltage. 3-4 - EN1 connects to EN2 and may be driven externally from one source to control all outputs. 1-2 - EN1 conencts to VIN. Buck1, LDO1, and LDO2 outputs are enabled at device power up. Buck 2 should be enabled separately using an external source connected to EN2. 1-3 - EN2 conencts to VIN. Buck 2 is enabled at device power up. Buck1, LDO1, and LDO2 outputs should be enabled using an external source connected to EN1. - - Both EN1 and EN2 can be driven separately from external sources connected at the board inputs EN1 and EN2. VIN EN2 Vin pin EN2 pin EN1 1 2 EN1 pin 3 4 Header pins on square grid Figure 3. Link Matrix Diagram 4 AN-1527 LP3905-A3 Application Board Copyright © 2007–2013, Texas Instruments Incorporated SNVA186B – March 2007 – Revised April 2013 Submit Documentation Feedback PCB Layout www.ti.com 6 PCB Layout Figure 4. PCB Component and Pin Layout Board SIze 1.5" x 1.3" 7 Bill of Materials Table 4. Bill of Materials for LP3905-A3 WSON Evaluation Board Item Type Value U1 L1,L2 (1) Inductor 2.2µF Qty Part Number Suggested Manufacturer Footprint 1 LP3905 Texas Instruments NHL0014B 1 DO3314-222MLB (1) Coilcraft (1) C1, C3 Capacitor 0.47µF 2 GRM188R61A474KA61D Murata 0603 C4, C5, C6 Capacitor 10µF 3 GRM21BR61A106KE19L (1) Murata 0805 C2 Capacitor 1.0nF 1 GRM188R61A105KA61D (1) Murata 0603 C7 Capacitor 10pF 1 GRM1885C1H100JZ01B (1) Murata 0603 (1) C8 Capacitor 6.8pF 1 Murata 0603 R1 Resistor 182Ω 1 GRM1885C1H6R8DZ01B CRCW06031823F (1) Vishay 0603, 1% R2 Resistor 365Ω 1 CRCW06033653F (1) Vishay 0603, 1% (1) Vishay 0603, 1% Vishay 0603, 1% R3 Resistor 200Ω 1 CRCW06032003F R4 Resistor 536Ω 1 CRCW06035363F (1) or similar SNVA186B – March 2007 – Revised April 2013 Submit Documentation Feedback AN-1527 LP3905-A3 Application Board Copyright © 2007–2013, Texas Instruments Incorporated 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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