User's Guide
SNVA233A – September 2007 – Revised April 2013
AN-1619 Evaluation Kit for LP3907 — Programmable
Power Management Unit with 12C Compatible Interface
1
LP3907 Overview
The LP3907 is a multi-function, programmable Power Management Unit, optimized for low power FPGAs,
microprocessors and DSPs. This device integrates two highly efficient 1A/600mA step-down DC/DC
converters with dynamic voltage management (DVM), two 300mA Linear Regulators and a 400kHz I2C
compatible interface to allow a host controller access to the internal control registers of the LP3907. The
LP3907 additionally features programmable power-on sequencing and a tiny 4 x 4 x 0.8mm WQFN 24–pin
package.
2
Evaluation Kit Overview
The LP3907 Evaluation Kit is based on a modular system, where the actual evaluation board is connected
to the PC via a USB – I2C interface board.
The kit supports complete functional evaluation of the LP3907 circuit. The evaluation kit consists of:
• LP3907 evaluation board with USB interface
• USB Interface cable
• Evaluation software for PC
• LP3907 datasheet
• Evaluation Manual (this document)
All trademarks are the property of their respective owners.
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1
Evaluation Kit Setup
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Figure 1. LP3907 Evaluation Board with Intergrated USB Interface
3
Evaluation Kit Setup
Please use ESD protection to prevent any unwanted damaging ESD events!
The LP3907 Evaluation Board should contain a USB interface to the left, as shown in Figure 2.
Connect this setup to the USB port of a PC using the included USB cable. When the USB board is
plugged in for the first time, the operating system prompts for “New hardware found” and installs the USB
driver. If this does not happen, try unplugging and plugging in the cable again.
Run the LP3907 evaluation software directly from the delivered CD by double clicking its icon. However,
we recommend that it be copied to the PC’s hard disk and run from there.
The software runs on WinXP and Windows 2000. Note: Win XP OS administrator rights may be required
to run the software.
4
Cautionary Notes
Always disconnect the USB cable from the board when changing the supply jumper setting (USBPower
jumper). Failure to do so may stop the USB board from responding.
If the USB interface is not responding or the software hangs up, press the reset button shown below, or
disconnect the USB cable for 5 seconds. Details of the operation of the USB interface board can be found
in the accompanying USB interface manual.
The evaluation software allows control of all registers necessary to control the device through sliders and
buttons. Direct Register Programming (described in Section 6.1.1) should only be used for debugging
purposes.
The GUI can be used in conjunction with an external supply, as long as the USB cable is plugged into the
board, and the USBPOWER jumper is removed.
If the user is using an external supply and the cable is NOT plugged into the board, be sure to
remove the jumpers connecting the USB interface to the chip – USBPOWER, GND plane, SDA, SCL,
and all of the ADC jumpers.
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Unit with 12C Compatible Interface
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Getting Started
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SDA, SCL, and ADC jumpers
USB Interface Reset
USBPower Jumper
GND Plane Connection
Figure 2. USB Interface Settings
5
Getting Started
Because of internal pullups, the LP3907 should become active as soon as the USB cable is plugged in.
To avoid damaging any parts, be sure to read the section describing how to power the board on Powering
the LP3907 Board.
For a quick start, make sure to short (connect) all jumpers except for JP8 & JP7 on the LP3907 Evaluation
board. Those jumpers short circuit the LDO output to GND for internal test purposes. Also please
disregard the 4 pin USB programming interface.
For a quick verification of a clean power up, start up the GUI, and the interface control at the bottom
should read “OK”. For more information on powering up the LP3907 through a charger adapter please
refer to the Powering the LP3907 Board section the LP3907 Dual High-Current Step-Down DC/DC and
Dual Linear Regulator with I2C-Compatible Interface (SNVS511) data sheet provided in the LP3907
Evaluation Kit CD.
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Getting Started
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4 pin USB programming interface
JP8 and JP7
Figure 3. Starting Jumper Settings
Figure 4. LP3907 Evaluation Software User Interface
4
AN-1619 Evaluation Kit for LP3907 — Programmable Power Management
Unit with 12C Compatible Interface
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Using the Evaluation Software
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6
Using the Evaluation Software
6.1
Register Interface (Direct Write and Read)
A register control established through an I2C compatible serial interface allows the user to directly program
the registers by writing to and reading from the memory map registers. This provides the user with added
flexibility in controlling the different functions of the LP3907. However, we caution the user to use this
function only for debugging purposes, because sending wrong values could damage the part. Sliders and
buttons provided below will accomplish the same commands in a more interactive way, and is also less
prone to mistakes.
6.1.1
Using the Register Controls
Direct Register Access (left section of Figure 5) is divided into two parts: Direct Register Write on the left
and Direct Register Read on the right. To write to a specific register, simply type the register address in
hexadecimal into the box, set the value through the specific bit buttons, and click “Write”. To read a value
in binary, type in the register address in hexadecimal into the box on the right and click “Read”.
For example, to turn off all regulators except the LDO1 regulator, this could be done by typing in the
number 10 into the “Addr (HEX):” box, clicking binary placeholder number 4, and then clicking store. The
register should reflect the stored value assigned (00010000) when the user clicks the button “Read.”
Please note that the same function could be more easily implemented through the graphical interfaces,
and is in the users’ best interest use Direct Register Access only when necessary.
The register profile interface allows the user to save all his/her settings for use at a later time. The GUI is
programmed to accommodate saving two sets of profiles.
Figure 5. Register Interface
6.2
Chip Control Interface
If the IC changes state and/or if the user assigns a new value to a register, the GUI may not reflect those
changes if the “Auto Poll” button is not enabled. By hitting the “Read All” button, the user will manually
renew the GUI so that it reflects the most current state of the IC.
The “Auto Poll” check box refreshes the GUI every second to ensure that it mirrors the current state of the
chip. The checkbox is on by default so that the user can constantly monitor the status of the IC. Similarly,
the “Auto Write” check box will enable the signals generated from using the sliders or buttons to be sent to
the chip. The check box is on by default, and should be unchecked if the user wishes not to change the
settings on the chip.
The “Defaults” button will set all registers on the chip to the default settings when clicked. The “Measure”
button will update the values measured on the chip by ADCs on the USB interface.
The Quit button allows the user to exit the program.
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Using the Evaluation Software
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Figure 6. Chip Control Interface
6.3
Regulator Output Voltage Selection
The output voltages of all the LDO and buck converters can be programmed through I2C control registers
by simply moving the slider. The buck regulators have two sliders and a Hold/Ramp button to control its
output voltage. This prevents the user from scaling the bucks to the second voltage if the Hold/Ramp
button is not depressed. The output of the buck regulator will reflect the setting of the slider that has its
radio button clicked (V1 or V2).
The buck regulators also have a Hold/Ramp slider that determines how fast the regulators scale to the
2nd programmed voltage. The ramp time is measured from the time the chip receives the I2C signals from
clicking the opposing radio button.
All of the regulators can also be hardware enabled or disabled via different configuration settings on the
20 pin header (described in the Hardware section of this report). The buck regulators also have additional
enable test points on the board.
The user can also force the bucks into PWM mode. Clicking the Force PWM check box on the GUI forces
the respective regulator to stay in PWM mode even in the case of a light load (PFM mode). Forced PWM
will be disabled by clicking the “Force PWM” check-box again.
The buck converters have a slider interface to provide an adjustable output voltage. By sliding the bar to
the bottom of the slider, the user can use an external resistor divider network for setting the Bucks output
voltage.
Force PWM mode is not recommended when a battery is powering the system.
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The USB interface also contains ADCs to measure the output voltage of the regulators. To do so, simply
connect the USB interface ADC jumpers shown in Figure 8. To measure the external voltages again,
simply click the “Measure” button on the GUI.
Figure 7. Regulator Output Voltage Selection Interface
USB interface ADC jumpers
Figure 8. USB Interface ADC Jumpers
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Using the Evaluation Hardware
6.4
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Buck and EN_T Control
The Control/Status Bits Control menu controls the following aspects of the chip:
1. Temp – Reflects the status of the regulators. If a buck or LDO regulator falls out of regulation because
of the temperature, it will be shown in that panel.
2. System Delay Sequence – Allows for the user to program a preset delay sequence for the startup of
the chip.
3. Enable ext clock for bucks – If checked, the user must input a 13MHz clock to the SYNC pin of the
IC. If unchecked, the bucks will run internally with a 2MHz clock.
4. Spread Spectrum, SS modulation – May help to reduce noise from the buck switchers. Described in
detail in the “Spread Spectrum” section off the LP3907 datasheet.
5. Bypass UVLO – This option disables the Under-Voltage Lock Out feature, which automatically
disables the regulators when the supply is less than 2.8V.
6. POR Delay– This option sets the delay time of the Power-On Reset function. More details can be
found in the “Flexible Power-On Reset” section of the datasheet.
Figure 9. Interrupt Control Interface
7
Using the Evaluation Hardware
7.1
Powering the LP3907 Board
We recommend that the user power the LP3907 through an external power supply if any loads are
attached to the regulators. In case no external power supply is available (as for showroom purposes), the
USB interface can be used to power the chip.
7.1.1
External supply
The LP3907 Evaluation board can be powered using a battery or wall adapter as described in previous
sections. Simply apply the voltage to the VDD_M pin referenced to GND_M.
Before applying power to VDD_M, be sure to disconnect the USBPOWER jumper. Failure to do so
may damage the USB chip and/or the IC. Full functionality of the GUI will still be available if powered by
an external power supply.
Also note that if the supply to VDD_M is close to 2.8V with a heavy load current on the regulators, the chip
is in danger of powering down due to UVLO. To disable UVLO, check the “Bypass UVLO” feature.
7.1.2
USB Interface Supply
In case the external supply or battery is not available, the USB board can be used to power the LP3907
chip. Simply connect the USBPOWER jumper to the 5V pin on the LP3907 evaluation board.
NOTE: External power supplies should be DISCONNECTED from the VDD_M pin if powering from
the USB.
The USB interface card can provide the following voltages :
• 5V from USB interface (default setting) -- USBPOWER needs to be set to 5V
• 3.3V -- USBPOWER needs to be set to 3.3V. Useful if the user wants to provide a lower voltage to the
8
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IC.
USB Interface Reset
USBPower Jumper
GND plane connection
Figure 10. USB Interface Settings
7.2
Enable Configurations Through the 20 Pin Header
The following diagram shows how to enable or disable different regulators by jumpering pins in the 20 pin
header.
One practical use of grounding the enable pins of the regulators is to signal a System Delay Sequence
(EN_T). One practical use of grounding the enable pins of the regulators is to signal a System Delay
Sequence (EN_T). Powering the chip through EN_T assertion is described in more detail in the “Power
On” section of the data sheet.
Figure 11. Top View of Header Connection
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Using the Evaluation Hardware
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Figure 12. Jumper Settings to Disable All Regulators and EN_T
7.3
LP3907 Hardware Block Description
The evaluation board is fully populated with the LP3907.
The LP3907 Evaluation board is designed to allow the user to test each function independently as well as
in the system. Jumpers 1-6 as described in the Jumper table allow the VDD and GND path of each of the
blocks to be separated from the rest of the blocks. To look at each of the blocks, follow the instructions
below:
1. Start with all the jumpers connected. (Without USBPOWER, JP7 and JP8)
2. Use the provided GUI to disable the desired block.
3. Remove the connecting jumpers (JP1, JP2, JP4, or JP6) based on the jumper table to isolate the
power and ground planes of the block under test.
4. Connect a power supply (VOUT+ 0.3V) to the input of the desired block referenced to its corresponding
ground.
5. Enable the block and proceed with normal testing.
The output voltage of the Low dropout regulators can be accessed at the ‘Turrets’ (LDO1 and LDO2)
referenced to GND_M. These are marked on the silk screen of the evaluation board.
The output voltage of the two Buck Regulators can be accessed at the ‘Turrets’ VBUCK1, VBUCK2
referenced to GND_SW1, and GND_SW2.
External power supplies can be attached to VDD_M referenced to GND_M. The voltage supplied to the
system must be between the range of 2.7V (with UVLO bypassed) to 5.5V.
SMB Connectors
The SMB connectors above VBUCK1 and VBUCK2 are connected to the SW pin of Buck1 and Buck2,
respectively. This will allow the user to monitor the switching of the regulators.
Resistive Pull-ups
The two I2C compatible signals SDA and SCL can be accessed externally via turrets I2C SCL, and I2C
SDA. Both lines are pulled up via 22K resistors R1, R2.
External Control Resistor Divider
Each of the Buck Switch Regulators has the option to be externally compensated through the external
resistive feedback network shown in Figure 13.
If the user wishes to have the chip internally compensated with factory programmed settings, then a 0
ohm resistor should be placed across R14 for Buck1 and R11 for Buck2.
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Buck 1 External Control Network
Buck 2 External Control Network
USBPower Jumper
Figure 13. Buck Regulator Feedback Network
Table 1. Jumper Settings
JUMPER
PURPOSE
NOTE
JP 1-6
These jumpers connect different Vins to the
system VDD (VDD_M):
JP1 connects VIN1 to VDD_M
JP2 connects VIN2 to VDD_M
JP3 connects the Buck core VDD to VDD_M
JP4 connects VINLDO1 to VDD_M
JP5 connects VINLDO12 to VDD_M
JP6 connects VINLDO2 to VDD_M
JP1 and JP2 allow the bucks to be powered from the system
power.
JP4 and JP6 allow the LDOs to be powered from the system
power.
JP3 and JP5 powers the internal bias and error amplifiers from
the system power. The voltage applied to AVDD and VINLDO12
should be in the range of 2.7 – 5.5V.
JP 7-8
These jumpers connect the output of LDO1
and LDO2 to GND:
JP7 connects LDO2 to GND
JP8 connects LDO1 to GND
These jumpers are used to connect the output of the respective
LDOs to GND for short circuit testing purposes.
JP 9–12
These jumpers tie the enables of each
regulator to VDD:
JP9 — LDO1
JP10 — LDO2
JP11 — Buck1
JP12 — Buck2
When connected, these jumpers ehable the regulators. If
disconnected, the regulator will power off.
JP50
This jumper connects the GND of the USB
interface with GND_M.
This jumper must be connected for USB interface functionality.
This jumper must be removed if powering from an external
power supply.
USBPOWER
This jumper allows the USB to power the
board.
This jumper should be disconnected if powering from an external
power supply.
It should be set to 5.0V if powering from the USB.
SDA, SCL
These jumpers allow the GUI to interface with
the chip.
Connect these jumpers for the GUI to work.
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Table 1. Jumper Settings (continued)
*ADC
These jumpers connect outputs of various
regulators to the ADCs of the USB.
Needs to be jumpered to measure the voltages of different
regulators from the GUI.
ENLDO2
ENLDO1
LDO2
LDO1
0.47 PF-25V-X7R-S
0.47 PF-25V-X7R-S
C5
C6
GND
VINLDO1
VINLDO2
JP1 VDD_M VDD_M
C1
1 PF-16V-X7R-S
VINLDO2
24
GND
LDO2
23
ENLDO2
22
ENLDO1
21
LDO1
20
C7
1 PF-16V-X7R-S
VINLDO1
19
VINLDO12
1
GND_L
18
JP3
VDD_M
JP4
VDD_M
BUCK CORE VDD
TO MAIN VDD
AVDD
GND
R15
NPOR
100k
EN_T
2
SCL
17
NPOR
3
SDA
16
LP3907
24 Pin LLP
GND_SW1
4
BUCK1
GND
1
VBUCK1
VIN1
VIN BUCK2
TO MAIN VDD
GND
EN_T
VDD_M
VIN BUCK1
TO MAIN VDD
VDD_M VDD_M
VIN2
GND_LF
C2
1 PF-16V-X7R-S
C3
10 PF-16V-X7R-S
JP2
GND
VINLDO12
GND_SW1
VIN1
L3
2
VDD_M
22K-S
R1
VDD_M
SW2
14
GND
2
L2
1
2.2 PH
SMB
JACK
VIN1
6
C4
10 PF-16V-X7R-S
GND
VIN2
13
7
ENSW1
8
FB1
9
GND_C
10
AVDD
11
FB2
VDD_M
LDO1/2 CORE VDD
TO MAIN VDD
JP6 VDD_M
VINLDO2
S2
GND
JP5
VINLDO12
GND_SW2
S1
SMB
JACK
LDO1 FET VDD
TO MAIN VDD
VINLDO1
22K-S
GND_SW2
15
SW1
5
2.2 PH
R2
GND
BUCK2
VBUCK2
C8
10 PF-16V-X7R-S
NOTE: VDD_M CONNECTS THE MAIN
VDD PLANE TO VARIOUS BLOCKS.
TO ISOLATE ANY BLOCK FROM VDD
SIMPLY DISCONNECT THE
CORRESPONDING JUMPER.
JP7
VIN2
LDO2
C9
10 PF-16V-X7R-S
LDO1
JP8
GND
JP9
VDD_M
JP10
VDD_M
JP11
VDD_M
JP12
VDD_M
GND
GND
12
ENSW2
ENSW1
ENSW2
C10
LDO2 FET VDD
TO MAIN VDD
ENLDO1
C13
ENLDO2
Generic
R14
Generic
R11
VBUCK1
Generic
C11
Generic
R12
Generic
C12
Generic
R13
Generic
VBUCK2
Generic
ENSW1
ENSW2
GND_M GND_M
GND_M
GND
GND
C14
10 PF-16V-X7R-S
GND
GND
Figure 14. LP3907 Evaluation Board Schematic
12
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Gerber Files
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8
Gerber Files
The LP3907 is a four-layer board. Below are the Gerber files for the board. The accompanying CD has the
Gerber files in Cadence allegro format.
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Gerber Files
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PCB Layout Considerations
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9
PCB Layout Considerations
The evaluation board layers from top to bottom are:
1. Top, component side
2. Ground plane
3. Mid signal section
4. Bottom, solder side
For good performance of the circuit, it is essential to place the input and output capacitors very close to
the circuit and use wide routing for the traces allowing high currents.
Sensitive components should be placed far from those components with high pulsating current.
Decoupling capacitors should be close to circuit’s VIN pins. Digital and analog ground should be routed
separately and connected together in a star connection.
It’s good practice to minimize high current and switching current paths.
9.1
Low Drop Out Regulators
Place the filter capacitors very close to the input and output pins. Use large trace width for high current
carrying traces and the returns to ground.
9.2
Buck Regulators
Place the supply bypass, filter capacitor, and inductor close together and keep the traces short. The traces
between these components carry relatively high switching current and act as antennas. Following these
rules reduces radiated noise.
Arrange the components so that the switching current loops curl in the same direction.
Connect the buck ground and the ground of the capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then connect this back to the general board system ground plane at
a single point. Place the pseudo-ground plane below these components and then have it tied to system
ground of the output capacitor outside of the current loops. This prevents the switched current from
injecting noise into the system ground. These components along with the inductor and output should be
placed on the same side of the circuit board, and their connections should be made on the same layer.
Route noise sensitive traces such as the voltage feedback path away from the inductor. This is done by
routing it on the bottom layer or by adding a grounded copper area between switching node and feedback
path. To reduce noisy traces between the power components, keep any digital lines away from this
section. Keep the Feedback node as small as possible so that the ground pin and ground traces will shield
it from the SW or buck output.
Use wide traces between the power components and for power connections to the DC-DC converter
circuit to reduce voltage errors caused by resistive losses.
For the sense lines, make sure to use a Kelvin contact connection.
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List of Main Components for LP3907 Evaluation Board (not including USB interface)
10
List of Main Components for LP3907 Evaluation Board (not including USB interface)
Reference Designator
Value, Size, Tolerance
Description
Vendor
C6,C7,C10
1uF, 16V, X7R, 08051
C2012X7R1C105K
TDK
C1–C5
10uF, 16V, X7R 01206
C3216X7R1C106M
TDK
C8,C9
0.47uF, 25V, X7R 0805
C2012X7R1E474K
TDK
R1,R2
22K OHM 1/10W 1% 0603
SMD
MCR03EZPFX2202
Rohm
R11, R13
0 OHM 0603 SMD
MCR03EZPJ000
Rohm
SMB Connector 131-1701-206
Emerson
S1,S2
16
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L2,L3
2.2 uH @ I sat 2A
Buck boost inductor NP04SZB
2R2N
Taiyo Yuden
WQFN package
4x4mm WQFN-24 package
Power management IC
Texas Instruments LP3907
AN-1619 Evaluation Kit for LP3907 — Programmable Power Management
Unit with 12C Compatible Interface
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Copyright © 2007–2013, Texas Instruments Incorporated
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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www.ti.com/computers
DLP® Products
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RFID
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www.ti.com/omap
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